[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image |
|
Date: |
Thu, 16 Dec 2021 23:16:01 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 73944a4bf4ab259b489af8128b4aec525484d642
https://github.com/qemu/qemu/commit/73944a4bf4ab259b489af8128b4aec525484d642
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-11-13 (Sat, 13 Nov 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This has really just one fix from Stefan, the rest is housekeeping.
The full changelog is:
Alexey Kardashevskiy (3):
Revert "make: Define default rule for .c when V=1 or V=2"
js2x: Fix compile and cleanup
version: update to 20211112
Stefan Berger (1):
tcgbios: Disable platform hierarchy in case of failure
Thomas Huth (8):
Mention the CR vs. LF problem in the documentation
slof/fs/accept: Replace TABs with spaces
Fix the URL to the Linux kernel coding style
lib/libc/README.txt: Fix "cannel" typo
travis.yml: Fix keywords
travis.yml: Update to Focal Fossa
travis.yml: Compile-test the qemu build
Silence some trivial compiler warning in the js2x code
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Commit: 2307ddc15b4f966f9de2066fe399bc723a452e28
https://github.com/qemu/qemu/commit/2307ddc15b4f966f9de2066fe399bc723a452e28
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
Merge tag 'qemu-slof-20211112' of github.com:aik/qemu into ppc-next
* tag 'qemu-slof-20211112' of github.com:aik/qemu:
pseries: Update SLOF firmware image
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 81fa8f265e698b741cbb954b7fd8db227525b3ef
https://github.com/qemu/qemu/commit/81fa8f265e698b741cbb954b7fd8db227525b3ef
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
Log Message:
-----------
hw/ppc/mac.h: Remove MAX_CPUS macro
The mac.h header defines a MAX_CPUS macro. This is confusingly named,
because it suggests it's a generic setting, but in fact it's used
by only the g3beige and mac99 machines. It's also using a single
macro for two values which aren't inherently the same -- if one
of these two machines was updated to support SMP configurations
then it would want a different max_cpus value to the other.
Since the macro is used in only two places, just expand it out
and get rid of it. If hypothetical future work to support SMP
in these boards needs a compile-time-known limit on the number
of CPUs, we can give it a suitable name at that point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211105184216.120972-1-peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a9911b2dd37b52748f06fa21f28cfb4d299f7a35
https://github.com/qemu/qemu/commit/a9911b2dd37b52748f06fa21f28cfb4d299f7a35
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Fixed call to deferred exception
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruction,
it's always 0.
Because of this helper_float_check_status would change the FI bit to 0
as this bit checks if the last operation was inexact and
float_flag_inexact is always 0.
These instructions also don't throw exceptions correctly since
helper_float_check_status throw exceptions based on fp_status.
This commit created a new helper, helper_fpscr_check_status that checks
FPSCR value instead of fp_status and checks for a larger variety of
exceptions than do_float_check_status.
Since fp_status isn't used, gen_reset_fpstatus() was removed.
The hardware used to compare QEMU's behavior to was a Power9.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 75bf9c760d9cdf72b842f2afb2bd5e0278cc0695
https://github.com/qemu/qemu/commit/75bf9c760d9cdf72b842f2afb2bd5e0278cc0695
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
Log Message:
-----------
test/tcg/ppc64le: test mtfsf
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fcca1605a84dce9ff9ea4ef1adc65b5130a37d1e
https://github.com/qemu/qemu/commit/fcca1605a84dce9ff9ea4ef1adc65b5130a37d1e
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they are marked as
reserved in the PowerISA and bit 28 is a reserved extension of the DRN
field (bits 29:31) but can't be set using mtfsfi, while the other DRN
bits may be set using mtfsfi instruction, so bit 28 was also added to
the mask.
Although this is a difference reported in the bug, since it's a reserved
bit it may be a "don't care" case, as put in the bug report. Looking at
the ISA it doesn't explicitly mention this bit can't be set, like it
does for FEX and VX, so I'm unsure if this is necessary.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 46f5cdf8b3b02bfb876a6cfd01376f3119b25bb6
https://github.com/qemu/qemu/commit/46f5cdf8b3b02bfb876a6cfd01376f3119b25bb6
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Expand Mask
Implement the following PowerISA v3.1 instructions:
vexpandbm: Vector Expand Byte Mask
vexpandhm: Vector Expand Halfword Mask
vexpandwm: Vector Expand Word Mask
vexpanddm: Vector Expand Doubleword Mask
vexpandqm: Vector Expand Quadword Mask
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 01d17978def808bffa6257bff786fdce256b3154
https://github.com/qemu/qemu/commit/01d17978def808bffa6257bff786fdce256b3154
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Extract Mask
Implement the following PowerISA v3.1 instructions:
vextractbm: Vector Extract Byte Mask
vextracthm: Vector Extract Halfword Mask
vextractwm: Vector Extract Word Mask
vextractdm: Vector Extract Doubleword Mask
vextractqm: Vector Extract Quadword Mask
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9a0748880f023478de68e0fcd17a9324afd34a66
https://github.com/qemu/qemu/commit/9a0748880f023478de68e0fcd17a9324afd34a66
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Mask Move insns
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e8799ecfefa8223f9f2b7c54b48a8e96a16e652f
https://github.com/qemu/qemu/commit/e8799ecfefa8223f9f2b7c54b48a8e96a16e652f
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/misc/ivshmem.c
Log Message:
-----------
ivshmem.c: change endianness to LITTLE_ENDIAN
The ivshmem device, as with most PCI devices, uses little endian byte
order. However, the endianness of its mmio_ops is marked as
DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big
endian hosts but also with PowerPC little endian hosts as well, since
the Power architecture in QEMU uses big endian hardware (XIVE controller,
PCI Host Bridges, etc) even if the host is in little endian byte order.
As it is today, the IVPosition of the device will be byte swapped when
running in Power BE and LE. This can be seen by changing the existing
qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION
regs in test_ivshmem_server() right after the VM ids assert. For x86_64
the VM id values read are '0' and '1', for ppc64 (tested in a Power8
RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server)
the ids will be '0' and '0x1000000'.
Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of
both endianness, and every other big-endian architecture that might use
this device, without impacting x86 users.
Fixes: cb06608e17f8 ("ivshmem: convert to memory API")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2d1c130e8a98bba10063b61277048bc5057b147d
https://github.com/qemu/qemu/commit/2d1c130e8a98bba10063b61277048bc5057b147d
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M tests/qtest/ivshmem-test.c
Log Message:
-----------
ivshmem-test.c: enable test_ivshmem_server for ppc64 arch
This test, if enabled by hand, was failing when the ivhsmem device was
being declared as DEVICE_NATIVE_ENDIAN with the following error:
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server:
**
ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server:
assertion failed (ret != 0): (0 != 0)
Aborted
After the endianness change done in the previous patch, we can verify in
both a a Power 9 little-endian host and in a Power 8 big-endian host
that this test is now passing:
$ QTEST_QEMU_BINARY=./ppc64-softmmu/qemu-system-ppc64
./tests/qtest/ivshmem-test -m slow
/ppc64/ivshmem/single: OK
/ppc64/ivshmem/hotplug: OK
/ppc64/ivshmem/memdev: OK
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server: OK
Let's keep it that way by officially enabling it for ppc64.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c9c8ef1e3dd52083cb6860a38340d1df62d3bbe0
https://github.com/qemu/qemu/commit/c9c8ef1e3dd52083cb6860a38340d1df62d3bbe0
Author: Christophe Lombard <clombard@linux.vnet.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
pci-host: Allow extended config space access for PowerNV PHB4 model
The PCIe extended configuration space on the device is not currently
accessible to the host. if by default, it is still inaccessible for
conventional for PCIe buses, add the current flag
PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended
config space access.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211109145053.43524-1-clombard@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e1ca90a068d0be91c6a3b725e0fb5fa7366948b7
https://github.com/qemu/qemu/commit/e1ca90a068d0be91c6a3b725e0fb5fa7366948b7
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs: Minor updates on the powernv documentation.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
[ clg: replaced Power9 by POWER9 ]
Message-Id:
<c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 11efdcdab8955aefdb4d01265fae5c92516d1bf5
https://github.com/qemu/qemu/commit/11efdcdab8955aefdb4d01265fae5c92516d1bf5
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: add a friendly warning when accel=kvm is used
If one tries to use -machine powernv9,accel=kvm in a Power9 host, a
cryptic error will be shown:
qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only
"-cpu host" is possible
qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid
argument
Appending '-cpu host' will throw another error:
qemu-system-ppc64: invalid chip model 'host' for powernv9 machine
The root cause is that in IBM PowerPC we have different specs for the bare-metal
and the guests. The bare-metal follows OPAL, the guests follow PAPR. The kernel
KVM modules presented in the ppc kernels implements PAPR. This means that we
can't use KVM accel when using the powernv machine, which is the emulation of
the bare-metal host.
All that said, let's give a more informative error in this case.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211130133153.444601-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0bcbeb7a1040383ccc8bf263706f75af85762389
https://github.com/qemu/qemu/commit/0bcbeb7a1040383ccc8bf263706f75af85762389
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs/system/ppc/powernv.rst: document KVM support status
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211130133153.444601-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 674c827bc7b0959549913df404151324814c076c
https://github.com/qemu/qemu/commit/674c827bc7b0959549913df404151324814c076c
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: fix "system-id" FDT when -uuid is set
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens because we're using fdt_property_string(), which is a
sequential write function that is supposed to be used when we're
building a new FDT, in a case where read/writing into an existing FDT.
Fix it by using fdt_setprop_string() instead.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211207094858.744386-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c632757ca91cd4cd864cd7fe5a9fc7475bae746a
https://github.com/qemu/qemu/commit/c632757ca91cd4cd864cd7fe5a9fc7475bae746a
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
docs: Introducing pseries documentation.
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
to this documentation, so that we only need to keep it updated in one
place.
0. https://wiki.qemu.org/Documentation/Platforms/POWER
1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id:
<66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 460688406761ca660466711766217f5a9e0fe25a
https://github.com/qemu/qemu/commit/460688406761ca660466711766217f5a9e0fe25a
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: rSTify ppc-spapr-hcalls.txt
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
[ clg: - replaced lingua by terminology
- add a new line at EOF ]
Message-Id:
<e20319dcf0ec37bedd915c740c3813eb0e58ead4.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d3632213902b15cb7235ec1b33dd41995e30dc3b
https://github.com/qemu/qemu/commit/d3632213902b15cb7235ec1b33dd41995e30dc3b
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4510aa241dacb8a2b8d14c322c43a2c12b3c18f8
https://github.com/qemu/qemu/commit/4510aa241dacb8a2b8d14c322c43a2c12b3c18f8
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
Link new ppc-spapr-hcalls.rst file to pseries.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8f4ff0b6ec36f38284f86a2ecfbb267d8db53288
https://github.com/qemu/qemu/commit/8f4ff0b6ec36f38284f86a2ecfbb267d8db53288
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Extend float_exception_flags to 16 bits
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 64d168f33ddb6afe0832c7b657d94f27e8e75c1d
https://github.com/qemu/qemu/commit/64d168f33ddb6afe0832c7b657d94f27e8e75c1d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf - Inf
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 62d517c665244a7f8c482e6405042464a7ce606b
https://github.com/qemu/qemu/commit/62d517c665244a7f8c482e6405042464a7ce606b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf * 0
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 675e91b6a36f321f2f34a8e811d40e4e78a2f362
https://github.com/qemu/qemu/commit/675e91b6a36f321f2f34a8e811d40e4e78a2f362
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flags specific to Inf / Inf and 0 / 0
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 611f4043a19d1dfce13db06f415903a7f811c089
https://github.com/qemu/qemu/commit/611f4043a19d1dfce13db06f415903a7f811c089
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to sqrt(-x)
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b706ff09aeaab22959f380a7c2a57b9098296d00
https://github.com/qemu/qemu/commit/b706ff09aeaab22959f380a7c2a57b9098296d00
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to convert non-nan to int
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f8eedeae8ebd48031803052583f4f6a4accacb7f
https://github.com/qemu/qemu/commit/f8eedeae8ebd48031803052583f4f6a4accacb7f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to signaling nans
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6e8336959213f0a77af34857ae3b0334b93fd9f9
https://github.com/qemu/qemu/commit/6e8336959213f0a77af34857ae3b0334b93fd9f9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_addsub for new flags
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: abfa0efe85cd530cb7f59b21655d2d458b406158
https://github.com/qemu/qemu/commit/abfa0efe85cd530cb7f59b21655d2d458b406158
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_mul for new flags
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8a97cb701d08f533405369bfda956313b2e560d7
https://github.com/qemu/qemu/commit/8a97cb701d08f533405369bfda956313b2e560d7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_div for new flags
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a5b14e2963cf8c2772437927110da45b31d9b055
https://github.com/qemu/qemu/commit/a5b14e2963cf8c2772437927110da45b31d9b055
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Move float_check_status from FPU_FCTI to translate
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_helper_* calls in gen_compute_fprf_float64
and protect only the first with set_fprf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 88ba16815262865539ed9ee2694b9fef7a64375b
https://github.com/qemu/qemu/commit/88ba16815262865539ed9ee2694b9fef7a64375b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_cvt for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5d2aa384990f180a57b5f8ad87c2092304cad580
https://github.com/qemu/qemu/commit/5d2aa384990f180a57b5f8ad87c2092304cad580
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Fix VXCVI return value
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3e18fa1574b28525ab52daa3875274afca9e9e2a
https://github.com/qemu/qemu/commit/3e18fa1574b28525ab52daa3875274afca9e9e2a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Remove inline from do_fri
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 07f1fbfadde022e28ae2e870389101e076697405
https://github.com/qemu/qemu/commit/07f1fbfadde022e28ae2e870389101e076697405
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use FloatRoundMode in do_fri
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c6f11593e28717397de82e77fd5d4e41dc5cbcc8
https://github.com/qemu/qemu/commit/c6f11593e28717397de82e77fd5d4e41dc5cbcc8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Tidy inexact handling in do_fri
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d7c78a45701231c7ee104d44ad59f3b43141aa99
https://github.com/qemu/qemu/commit/d7c78a45701231c7ee104d44ad59f3b43141aa99
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Clean up do_fri
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bb41409772f176e7966c345605ad5603a6b76103
https://github.com/qemu/qemu/commit/bb41409772f176e7966c345605ad5603a6b76103
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fmadd for new flags
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd,
whereas the previous *_maddsub_update_excp assumed it true.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2ff73ee5b7737bb965acaeed490bcd7d598f7435
https://github.com/qemu/qemu/commit/2ff73ee5b7737bb965acaeed490bcd7d598f7435
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_fmadd
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f29be6e65fe58c43fe631927f3239875721c968e
https://github.com/qemu/qemu/commit/f29be6e65fe58c43fe631927f3239875721c968e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Do not call do_float_check_status from do_fmadd
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 327267778a0b275d1360fdfa4121a3d66af82c35
https://github.com/qemu/qemu/commit/327267778a0b275d1360fdfa4121a3d66af82c35
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_frsp
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c4d715f91efe2cfe31594138d98574d5bb3d22d2
https://github.com/qemu/qemu/commit/c4d715f91efe2cfe31594138d98574d5bb3d22d2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update do_frsp for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ce3f24966d0d7773a9acb0cf88ad42789151e506
https://github.com/qemu/qemu/commit/ce3f24966d0d7773a9acb0cf88ad42789151e506
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble in do_frsp
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ba9654415861af4a9828da22a480aeef48e470fa
https://github.com/qemu/qemu/commit/ba9654415861af4a9828da22a480aeef48e470fa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update sqrt for new flags
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6ae1d1abf64814524f6c9c8c2894ac7ae4765a54
https://github.com/qemu/qemu/commit/6ae1d1abf64814524f6c9c8c2894ac7ae4765a54
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update xsrqpi and xsrqpxp to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 84b50739bb4971adf77124cd0379115989c2c763
https://github.com/qemu/qemu/commit/84b50739bb4971adf77124cd0379115989c2c763
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fre to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2810b5043c907d6876ae2d33a7875632d656d0b6
https://github.com/qemu/qemu/commit/2810b5043c907d6876ae2d33a7875632d656d0b6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float64r32 arithmetic routines
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its float32 operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 224e49cb74200726c2e960ab194f8f3ee7fcfd6c
https://github.com/qemu/qemu/commit/224e49cb74200726c2e960ab194f8f3ee7fcfd6c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fmadds et al
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f76ee2b6b542e476b914f0d4fae2d74321cbc229
https://github.com/qemu/qemu/commit/f76ee2b6b542e476b914f0d4fae2d74321cbc229
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fsqrts
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 57c7b0d6d9493481ab39f2ec0fa85f61cac71b5b
https://github.com/qemu/qemu/commit/57c7b0d6d9493481ab39f2ec0fa85f61cac71b5b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fadds, fsubs, fdivs
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f6311162d87a596240e4b6f111fa49bfad31e847
https://github.com/qemu/qemu/commit/f6311162d87a596240e4b6f111fa49bfad31e847
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fmuls
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8fa51eefc4e3c7d1b5beb1034ca952c975415fe9
https://github.com/qemu/qemu/commit/8fa51eefc4e3c7d1b5beb1034ca952c975415fe9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for frsqrtes
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0b4a72e1a98452544eddede2b8df485f891affa5
https://github.com/qemu/qemu/commit/0b4a72e1a98452544eddede2b8df485f891affa5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fres to new flags and float64r32
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8493993a14f66b5cb15b56be4934c7307d68aecf
https://github.com/qemu/qemu/commit/8493993a14f66b5cb15b56be4934c7307d68aecf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only ones set within the register, and then a bitwise equality.
Fixes a bug in which a single-precision NaN is considered !SP,
because float64_eq(nan, nan) is always false.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9529626fd30782e2e50cc55d82ba57c4ce716972
https://github.com/qemu/qemu/commit/9529626fd30782e2e50cc55d82ba57c4ce716972
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable software TLB for the 7450 family
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
3.15. With no known support in firmware or OS, this means that no code
for any of the 7450 CPUs is ever ran in QEMU.
Since the implementation in QEMU of the 7400 MMU is the same as the
7450, except for the software TLB vs. hardware TLB search, this patch
changes all 7450 cpus to the 7400 MMU model. This has the practical
effect of disabling the software TLB feature while keeping other
aspects of address translation working as expected.
This allow us to run software on the 7450 family again.
*- note that the 7448 is currently aliased in QEMU for a 7400, so it
is unaffected by this change.
1- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 14fd9979230903ff6b17ba4d62e462d9d0337ab0
https://github.com/qemu/qemu/commit/14fd9979230903ff6b17ba4d62e462d9d0337ab0
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable unused facilities in the e600 CPU
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 665a0ac25e33cad9834fb7268eba91233632b301
https://github.com/qemu/qemu/commit/665a0ac25e33cad9834fb7268eba91233632b301
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove the software TLB model of 7450 CPUs
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 03a9ebf698f01f1ff619e9e8b42112f32c2f2dde
https://github.com/qemu/qemu/commit/03a9ebf698f01f1ff619e9e8b42112f32c2f2dde
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Fix MPCxxx FPU interrupt address
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 87d8350e11aa891651719c7100e8c2a34ca481e2
https://github.com/qemu/qemu/commit/87d8350e11aa891651719c7100e8c2a34ca481e2
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove 603e exception model
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9391a8c0dadbec8413a6e470c7714731a641ab05
https://github.com/qemu/qemu/commit/9391a8c0dadbec8413a6e470c7714731a641ab05
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Set 601v exception model id
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4534247913be0a2fe5ab6f0f7134f0f4b72301ac
https://github.com/qemu/qemu/commit/4534247913be0a2fe5ab6f0f7134f0f4b72301ac
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: remove 401/403 CPUs
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211202191108.1291515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 909714aa44a330be689e16966b038b2807c9df76
https://github.com/qemu/qemu/commit/909714aa44a330be689e16966b038b2807c9df76
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Change kernel load address
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=1000000\0"
"fdt_addr_r=1800000\0"
"ramdisk_addr_r=1900000\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.
Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.
Change the kernel load address to match U-Boot expectations and fix
loading.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1ddeaba73c4c9b69edf09fa9de7f59b719723c36
https://github.com/qemu/qemu/commit/1ddeaba73c4c9b69edf09fa9de7f59b719723c36
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc: Mark the 'taihu' machine as deprecated
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added by this board. The users
can use the 'ref405ep' machine to test their PPC405 code instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211203164904.290954-2-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0d64f431b03ac67cc53ded5b4e35d4bb59bd6633
https://github.com/qemu/qemu/commit/0d64f431b03ac67cc53ded5b4e35d4bb59bd6633
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc: Add trace-events for DCR accesses
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 970e8f2e3f251b595b93937276b30182ae90749f
https://github.com/qemu/qemu/commit/970e8f2e3f251b595b93937276b30182ae90749f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: Convert printfs to trace-events
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d91ee79bd7469e6addd1211a441cfb2de67c94f9
https://github.com/qemu/qemu/commit/d91ee79bd7469e6addd1211a441cfb2de67c94f9
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 41fc41a13fe3bad87a0d6e8091b82d878f4b1f7e
https://github.com/qemu/qemu/commit/41fc41a13fe3bad87a0d6e8091b82d878f4b1f7e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change ppc405ep_init() return value
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2ae7a048bfd819b597c4350f927ebc2331a3cd4b
https://github.com/qemu/qemu/commit/2ae7a048bfd819b597c4350f927ebc2331a3cd4b
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Add some address space definitions
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 90318b5bf011089e724f1b3bef7a161b3fc1264d
https://github.com/qemu/qemu/commit/90318b5bf011089e724f1b3bef7a161b3fc1264d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Remove flash support
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for about 10 years.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b2b90ed32447b58ad0e02ec1af49ef2347e43957
https://github.com/qemu/qemu/commit/b2b90ed32447b58ad0e02ec1af49ef2347e43957
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Rework FW load
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffffffc where nothing is currently mapped. Support must
have been broken these last years.
Since we can not find a "ppc405_rom.bin" firmware file, request one to
be specified on the command line. A consequence of this change is that
the machine can be booted directly from Linux without any FW being
loaded. This is still broken and the CPU start address will be fixed
in the next changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: aa68ca2486957c8853b9e6422988a6bf441fae3c
https://github.com/qemu/qemu/commit/aa68ca2486957c8853b9e6422988a6bf441fae3c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Introduce ppc405_set_default_bootinfo()
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d2c56fbfac9f913b1615fc9a4af7a9d07d9a7076
https://github.com/qemu/qemu/commit/d2c56fbfac9f913b1615fc9a4af7a9d07d9a7076
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Fix boot from kernel
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset handler to setup the registers and to start the CPU
from the Linux kernel entry point.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 120a096a247bbd8db2d5eb64aac43e67369cdaeb
https://github.com/qemu/qemu/commit/120a096a247bbd8db2d5eb64aac43e67369cdaeb
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change default PLL values at reset
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bceb475b023787e0068cdd41efdc35ded0b19b60
https://github.com/qemu/qemu/commit/bceb475b023787e0068cdd41efdc35ded0b19b60
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
Log Message:
-----------
ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7819f58079d36643b9543010c382bcb8605bb923
https://github.com/qemu/qemu/commit/7819f58079d36643b9543010c382bcb8605bb923
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Add update of bi_procfreq field
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 123f4bcb18c4afc9a28892a45db01cb5976cd922
https://github.com/qemu/qemu/commit/123f4bcb18c4afc9a28892a45db01cb5976cd922
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by changing these instructions to use
GEN_VSX_HELPER_X3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 79b7bf87bee78ca0c2540766b317cf084e94714f
https://github.com/qemu/qemu/commit/79b7bf87bee78ca0c2540766b317cf084e94714f
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move xs{max,min}[cj]dp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5b4589fbca9746a3829d43da60a61adb523b5e1c
https://github.com/qemu/qemu/commit/5b4589fbca9746a3829d43da60a61adb523b5e1c
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: fix xscvqpdp register access
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 18f37d371068579ef5f65a7fd740703de13723c9
https://github.com/qemu/qemu/commit/18f37d371068579ef5f65a7fd740703de13723c9
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: move xscvqpdp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c361e5b85601764b500928ea77734e0817739bea
https://github.com/qemu/qemu/commit/c361e5b85601764b500928ea77734e0817739bea
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix e6500 boot
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is the IVOR
for VPU. This is because QEMU knows only knows about the VPU interrupt
for the 7400s. In theory, we should not be raising _that_ VPU
interrupt, but instead another one specific for the e6500.
We unfortunately cannot register e6500-specific VPU/VPUA interrupts
because the SPEU/EFPDI interrupts also use IVOR32/33. These are
present only in the e500v1/2 versions. From the user manual:
e500v1, e500v2: only SPEU/EFPDI/EFPRI
e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA
e6500: only VPU/VPUA
So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code
to convert the VPU #73 to a #32 when we're in the e6500. Since the
handling for SPEU and VPU is the same this is the only change that's
needed. The EFPDI is not implemented and will cause an abort. I don't
think it worth it changing the error message to take VPUA into
consideration, so I'm not changing anything there.
This bug was discussed in the thread:
https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html
1- https://git.kernel.org/torvalds/c/cd66cc2ee52
Reported-by: <mario@locati.it>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9303838b79e8f2544992a2576df0b2708fad3541
https://github.com/qemu/qemu/commit/9303838b79e8f2544992a2576df0b2708fad3541
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5a5316547120354c3cba1c823647c805eca4139b
https://github.com/qemu/qemu/commit/5a5316547120354c3cba1c823647c805eca4139b
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/meson.build
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
Log Message:
-----------
target/ppc: introduce PMUEventType and PMU overflow timers
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are
inactive due to frozen counter bits state are of type
'PMU_EVENT_INACTIVE'. Other types added in this patch are
PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added
later on.
Let's also add the required PMU cycle overflow timers. They will be used
to trigger cycle overflows when cycle events are being sampled. This
timer will call cpu_ppc_pmu_timer_cb(), which in turn calls
fire_PMC_interrupt(). Both functions are stubs that will be implemented
later on when EBB support is added.
Two new helper files are created to host this new logic.
cpu_ppc_pmu_init() will init all overflow timers during CPU init time.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cdd19150af26a584fdef6e8c49bbfd864c082ded
https://github.com/qemu/qemu/commit/cdd19150af26a584fdef6e8c49bbfd864c082ded
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 75f07e2501f80353ab1cf55cf01eb92ddd53bcc3
https://github.com/qemu/qemu/commit/75f07e2501f80353ab1cf55cf01eb92ddd53bcc3
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on PMCs r/w
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the required wiring for that and make our lives a bit easier in the
next patches.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5199bf112065f70b0cf14ae0bd90036b8d78a2f5
https://github.com/qemu/qemu/commit/5199bf112065f70b0cf14ae0bd90036b8d78a2f5
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on MMCR1 write
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to
control the PMU. These three registers aren't being handled in this
initial implementation, so for now we're controlling all the PMU
aspects using MMCR0, MMCR1 and the PMCs.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0c5d4d8dd80c6c425a64697cd8bdff6ccd4bd953
https://github.com/qemu/qemu/commit/0c5d4d8dd80c6c425a64697cd8bdff6ccd4bd953
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: enable PMU counter overflow with cycle events
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.
For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer to expire in the moment the overflow would be occuring. The
timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will
trigger the PMU alert and, if the conditions are met, an EBB exception.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 420c1ad8acb2ec4f09a10eb61274ab5065db217e
https://github.com/qemu/qemu/commit/420c1ad8acb2ec4f09a10eb61274ab5065db217e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: enable PMU instruction count
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated in
each translation block right before exiting it.
A new pmu_count_insns() helper in translation.c was added to do that.
After verifying that the PMU is counting instructions, call
helper_insns_inc(). This new helper from power8-pmu.c will add the
instructions to the relevant counters. It'll also be responsible for
triggering counter negative overflows as it is already being done with
cycles.
To verify whether the PMU is counting instructions or now, a new hflags
named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal
state of the PMU. We're be using this flag to avoid calling
helper_insn_inc() when we do not have a valid instruction event being
sampled.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 95ad68d1713b77d4f8fc0dc269e49b662592b267
https://github.com/qemu/qemu/commit/95ad68d1713b77d4f8fc0dc269e49b662592b267
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 65477f4361cb869666848b6dc8d7a1bbb2b8a818
https://github.com/qemu/qemu/commit/65477f4361cb869666848b6dc8d7a1bbb2b8a818
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
Log Message:
-----------
PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The following operations happens during an EBB:
- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).
The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].
This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.
[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9fdb5e11253f1decfd637e11a795670b62a98da9
https://github.com/qemu/qemu/commit/9fdb5e11253f1decfd637e11a795670b62a98da9
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under PHB3
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 84f25ad28a34aef86734619b1db2a22f9bc29d32
https://github.com/qemu/qemu/commit/84f25ad28a34aef86734619b1db2a22f9bc29d32
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
Log Message:
-----------
ppc/pnv: Use the chip class to check the index of PHB3 devices
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a817051fb40194250f05bab71dccd155a895698c
https://github.com/qemu/qemu/commit/a817051fb40194250f05bab71dccd155a895698c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Drop the "num-phbs" property
It is never used.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0bdfbffd156fa5644318f4db2bca33ffe4f50d81
https://github.com/qemu/qemu/commit/0bdfbffd156fa5644318f4db2bca33ffe4f50d81
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3_pbcq.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3dc0498f1963bb2f29993260c124eab631efa39e
https://github.com/qemu/qemu/commit/3dc0498f1963bb2f29993260c124eab631efa39e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 50d04841471eee886c4c308e8e78c65f75a173e3
https://github.com/qemu/qemu/commit/50d04841471eee886c4c308e8e78c65f75a173e3
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 chip. Use that instead of num_phbs which fits POWER8 chips.
This will ease adding support for user created devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fa566a7395c57e868ae9b1458fdcb50b5ec8aa2d
https://github.com/qemu/qemu/commit/fa566a7395c57e868ae9b1458fdcb50b5ec8aa2d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d4d0325380b85ffb1cbdd1760a3f018d0b0cbfe1
https://github.com/qemu/qemu/commit/d4d0325380b85ffb1cbdd1760a3f018d0b0cbfe1
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under the PHB4 model
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ff8e25c867fd9469f3ea106713570d284b489698
https://github.com/qemu/qemu/commit/ff8e25c867fd9469f3ea106713570d284b489698
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a num_stack class attribute
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d36f3265f0b9b7562aa7a9a1d8ea87b76a2bdae4
https://github.com/qemu/qemu/commit/d36f3265f0b9b7562aa7a9a1d8ea87b76a2bdae4
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Compute the PHB index from the PHB4 PEC model
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 which has a different layout of stacks: 3 per PECs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 52bf7590013f62250af8b8ac523c85937bcca410
https://github.com/qemu/qemu/commit/52bf7590013f62250af8b8ac523c85937bcca410
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Remove "system-memory" property from PHB4 PEC
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fc6f3a23d8ff25e8004576630f9a90a522ca8b83
https://github.com/qemu/qemu/commit/fc6f3a23d8ff25e8004576630f9a90a522ca8b83
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move realize of PEC stacks under the PEC model
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 292c21ede9b6618ab0f51cbfa0efeb1464232506
https://github.com/qemu/qemu/commit/292c21ede9b6618ab0f51cbfa0efeb1464232506
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0afbf81147f636785fa9a4ae0bcab714078f1d62
https://github.com/qemu/qemu/commit/0afbf81147f636785fa9a4ae0bcab714078f1d62
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-16 (Thu, 16 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
M docs/system/ppc/powernv.rst
M docs/system/ppc/pseries.rst
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M hw/misc/ivshmem.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb3_pbcq.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/trace-events
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M include/hw/pci-host/pnv_phb3.h
M include/hw/pci-host/pnv_phb4.h
M include/hw/ppc/pnv.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/meson.build
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu-regs.c.inc
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
M target/ppc/spr_tcg.h
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
M tests/qtest/ivshmem-test.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
Log Message:
-----------
Merge tag 'pull-ppc-20211216' of https://github.com/legoater/qemu into staging
ppc 7.0 queue:
* General cleanup for Mac machines (Peter)
* Fixes for FPU exceptions (Lucas)
* Support for new ISA31 instructions (Matheus)
* Fixes for ivshmem (Daniel)
* Cleanups for PowerNV PHB (Christophe and Cedric)
* Updates of PowerNV and pSeries documentation (Leonardo and Daniel)
* Fixes for PowerNV (Daniel)
* Large cleanup of FPU implementation (Richard)
* Removal of SoftTLBs support for PPC74x CPUs (Fabiano)
* Fixes for exception models in MPCx and 60x CPUs (Fabiano)
* Removal of 401/403 CPUs (Cedric)
* Deprecation of taihu machine (Thomas)
* Large rework of PPC405 machine (Cedric)
* Fixes for VSX instructions (Victor and Matheus)
* Fix for e6500 CPU (Fabiano)
* Initial support for PMU (Daniel)
# gpg: Signature made Thu 16 Dec 2021 11:33:49 AM PST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20211216' of https://github.com/legoater/qemu: (101 commits)
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
ppc/pnv: Move realize of PEC stacks under the PEC model
ppc/pnv: Remove "system-memory" property from PHB4 PEC
ppc/pnv: Compute the PHB index from the PHB4 PEC model
ppc/pnv: Introduce a num_stack class attribute
ppc/pnv: Introduce a "chip" property under the PHB4 model
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
ppc/pnv: Drop the "num-phbs" property
ppc/pnv: Use the chip class to check the index of PHB3 devices
ppc/pnv: Introduce a "chip" property under PHB3
PPC64/TCG: Implement 'rfebb' instruction
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
target/ppc: enable PMU instruction count
target/ppc: enable PMU counter overflow with cycle events
target/ppc: PMU: update counters on MMCR1 write
target/ppc: PMU: update counters on PMCs r/w
target/ppc: PMU basic cycle count for pseries TCG
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/29eb5c2c86f9...0afbf81147f6