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[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image |
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Date: |
Wed, 15 Dec 2021 17:02:57 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 73944a4bf4ab259b489af8128b4aec525484d642
https://github.com/qemu/qemu/commit/73944a4bf4ab259b489af8128b4aec525484d642
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-11-13 (Sat, 13 Nov 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This has really just one fix from Stefan, the rest is housekeeping.
The full changelog is:
Alexey Kardashevskiy (3):
Revert "make: Define default rule for .c when V=1 or V=2"
js2x: Fix compile and cleanup
version: update to 20211112
Stefan Berger (1):
tcgbios: Disable platform hierarchy in case of failure
Thomas Huth (8):
Mention the CR vs. LF problem in the documentation
slof/fs/accept: Replace TABs with spaces
Fix the URL to the Linux kernel coding style
lib/libc/README.txt: Fix "cannel" typo
travis.yml: Fix keywords
travis.yml: Update to Focal Fossa
travis.yml: Compile-test the qemu build
Silence some trivial compiler warning in the js2x code
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Commit: ed60537093183decb4f977d3614c3f5303b715bc
https://github.com/qemu/qemu/commit/ed60537093183decb4f977d3614c3f5303b715bc
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
Merge tag 'qemu-slof-20211112' of github.com:aik/qemu into ppc-next
* tag 'qemu-slof-20211112' of github.com:aik/qemu:
pseries: Update SLOF firmware image
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fb77ad445072748d9dc275f9fda053d5fbaafb47
https://github.com/qemu/qemu/commit/fb77ad445072748d9dc275f9fda053d5fbaafb47
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
Log Message:
-----------
hw/ppc/mac.h: Remove MAX_CPUS macro
The mac.h header defines a MAX_CPUS macro. This is confusingly named,
because it suggests it's a generic setting, but in fact it's used
by only the g3beige and mac99 machines. It's also using a single
macro for two values which aren't inherently the same -- if one
of these two machines was updated to support SMP configurations
then it would want a different max_cpus value to the other.
Since the macro is used in only two places, just expand it out
and get rid of it. If hypothetical future work to support SMP
in these boards needs a compile-time-known limit on the number
of CPUs, we can give it a suitable name at that point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211105184216.120972-1-peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4e7289960d2ed8b59fa73af48ac3be1b5a780c1c
https://github.com/qemu/qemu/commit/4e7289960d2ed8b59fa73af48ac3be1b5a780c1c
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Fixed call to deferred exception
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruction,
it's always 0.
Because of this helper_float_check_status would change the FI bit to 0
as this bit checks if the last operation was inexact and
float_flag_inexact is always 0.
These instructions also don't throw exceptions correctly since
helper_float_check_status throw exceptions based on fp_status.
This commit created a new helper, helper_fpscr_check_status that checks
FPSCR value instead of fp_status and checks for a larger variety of
exceptions than do_float_check_status.
Since fp_status isn't used, gen_reset_fpstatus() was removed.
The hardware used to compare QEMU's behavior to was a Power9.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-2-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dd54e9feb79e3b626a933f5df4a746dfc5511535
https://github.com/qemu/qemu/commit/dd54e9feb79e3b626a933f5df4a746dfc5511535
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
Log Message:
-----------
test/tcg/ppc64le: test mtfsf
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-3-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5bb48517ecdc73c42cb46d2a6ab2f1dbad7d335f
https://github.com/qemu/qemu/commit/5bb48517ecdc73c42cb46d2a6ab2f1dbad7d335f
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.c
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: ppc_store_fpscr doesn't update bits 0 to 28 and 52
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they are marked as
reserved in the PowerISA and bit 28 is a reserved extension of the DRN
field (bits 29:31) but can't be set using mtfsfi, while the other DRN
bits may be set using mtfsfi instruction, so bit 28 was also added to
the mask.
Although this is a difference reported in the bug, since it's a reserved
bit it may be a "don't care" case, as put in the bug report. Looking at
the ISA it doesn't explicitly mention this bit can't be set, like it
does for FEX and VX, so I'm unsure if this is necessary.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 851bdd37bb9b05dafe80d3870e2b2d41e68cb567
https://github.com/qemu/qemu/commit/851bdd37bb9b05dafe80d3870e2b2d41e68cb567
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Expand Mask
Implement the following PowerISA v3.1 instructions:
vexpandbm: Vector Expand Byte Mask
vexpandhm: Vector Expand Halfword Mask
vexpandwm: Vector Expand Word Mask
vexpanddm: Vector Expand Doubleword Mask
vexpandqm: Vector Expand Quadword Mask
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 456f5d2fc28fc99ede678f8818fb632ca00c42a4
https://github.com/qemu/qemu/commit/456f5d2fc28fc99ede678f8818fb632ca00c42a4
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Extract Mask
Implement the following PowerISA v3.1 instructions:
vextractbm: Vector Extract Byte Mask
vextracthm: Vector Extract Halfword Mask
vextractwm: Vector Extract Word Mask
vextractdm: Vector Extract Doubleword Mask
vextractqm: Vector Extract Quadword Mask
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c3e58a0a05c78b01179e0790acc52e541cdf6b62
https://github.com/qemu/qemu/commit/c3e58a0a05c78b01179e0790acc52e541cdf6b62
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vmx-impl.c.inc
Log Message:
-----------
target/ppc: Implement Vector Mask Move insns
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2a2ee86088ca75d7e81bbd8cd45a0bfae813f62a
https://github.com/qemu/qemu/commit/2a2ee86088ca75d7e81bbd8cd45a0bfae813f62a
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/misc/ivshmem.c
Log Message:
-----------
ivshmem.c: change endianness to LITTLE_ENDIAN
The ivshmem device, as with most PCI devices, uses little endian byte
order. However, the endianness of its mmio_ops is marked as
DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big
endian hosts but also with PowerPC little endian hosts as well, since
the Power architecture in QEMU uses big endian hardware (XIVE controller,
PCI Host Bridges, etc) even if the host is in little endian byte order.
As it is today, the IVPosition of the device will be byte swapped when
running in Power BE and LE. This can be seen by changing the existing
qtest 'ivshmem-test' to run in ppc64 hosts and printing the IVPOSITION
regs in test_ivshmem_server() right after the VM ids assert. For x86_64
the VM id values read are '0' and '1', for ppc64 (tested in a Power8
RHEL 7.9 BE server) and ppc64le (tested in a Power9 RHEL 8.6 LE server)
the ids will be '0' and '0x1000000'.
Change this device to LITTLE_ENDIAN fixes the issue for Power hosts of
both endianness, and every other big-endian architecture that might use
this device, without impacting x86 users.
Fixes: cb06608e17f8 ("ivshmem: convert to memory API")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/168
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cb3154d4d3bc2d364e07f1c1ad7a58f07e13fa8e
https://github.com/qemu/qemu/commit/cb3154d4d3bc2d364e07f1c1ad7a58f07e13fa8e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/qtest/ivshmem-test.c
Log Message:
-----------
ivshmem-test.c: enable test_ivshmem_server for ppc64 arch
This test, if enabled by hand, was failing when the ivhsmem device was
being declared as DEVICE_NATIVE_ENDIAN with the following error:
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server:
**
ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server:
assertion failed (ret != 0): (0 != 0)
Aborted
After the endianness change done in the previous patch, we can verify in
both a a Power 9 little-endian host and in a Power 8 big-endian host
that this test is now passing:
$ QTEST_QEMU_BINARY=./ppc64-softmmu/qemu-system-ppc64
./tests/qtest/ivshmem-test -m slow
/ppc64/ivshmem/single: OK
/ppc64/ivshmem/hotplug: OK
/ppc64/ivshmem/memdev: OK
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server: OK
Let's keep it that way by officially enabling it for ppc64.
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211124092948.335389-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 428998904bee5bc490eb63c22c5d27b5ea3fcd04
https://github.com/qemu/qemu/commit/428998904bee5bc490eb63c22c5d27b5ea3fcd04
Author: Christophe Lombard <clombard@linux.vnet.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4.c
Log Message:
-----------
pci-host: Allow extended config space access for PowerNV PHB4 model
The PCIe extended configuration space on the device is not currently
accessible to the host. if by default, it is still inaccessible for
conventional for PCIe buses, add the current flag
PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended
config space access.
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211109145053.43524-1-clombard@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a5a7093618302ede47e8d22114502e336ba4e864
https://github.com/qemu/qemu/commit/a5a7093618302ede47e8d22114502e336ba4e864
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs: Minor updates on the powernv documentation.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
[ clg: replaced Power9 by POWER9 ]
Message-Id:
<c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 97921e07e0b5f0f2d7a371e234027ae78ff8bb9f
https://github.com/qemu/qemu/commit/97921e07e0b5f0f2d7a371e234027ae78ff8bb9f
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: add a friendly warning when accel=kvm is used
If one tries to use -machine powernv9,accel=kvm in a Power9 host, a
cryptic error will be shown:
qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only
"-cpu host" is possible
qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Invalid
argument
Appending '-cpu host' will throw another error:
qemu-system-ppc64: invalid chip model 'host' for powernv9 machine
The root cause is that in IBM PowerPC we have different specs for the bare-metal
and the guests. The bare-metal follows OPAL, the guests follow PAPR. The kernel
KVM modules presented in the ppc kernels implements PAPR. This means that we
can't use KVM accel when using the powernv machine, which is the emulation of
the bare-metal host.
All that said, let's give a more informative error in this case.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20211130133153.444601-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2ac1266a8f8614bc57d7e1114c556d6a4e250488
https://github.com/qemu/qemu/commit/2ac1266a8f8614bc57d7e1114c556d6a4e250488
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/ppc/powernv.rst
Log Message:
-----------
docs/system/ppc/powernv.rst: document KVM support status
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211130133153.444601-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2317ce666337c23d2291deff0d68ceb2d9c1d1c0
https://github.com/qemu/qemu/commit/2317ce666337c23d2291deff0d68ceb2d9c1d1c0
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv.c: fix "system-id" FDT when -uuid is set
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens because we're using fdt_property_string(), which is a
sequential write function that is supposed to be used when we're
building a new FDT, in a case where read/writing into an existing FDT.
Fix it by using fdt_setprop_string() instead.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211207094858.744386-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 69521a52ae00f940f6407dfd9d5a2b867f3e9e83
https://github.com/qemu/qemu/commit/69521a52ae00f940f6407dfd9d5a2b867f3e9e83
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
docs: Introducing pseries documentation.
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
to this documentation, so that we only need to keep it updated in one
place.
0. https://wiki.qemu.org/Documentation/Platforms/POWER
1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id:
<66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 459b9d7ec4230043396a5708917534afab4efefa
https://github.com/qemu/qemu/commit/459b9d7ec4230043396a5708917534afab4efefa
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: rSTify ppc-spapr-hcalls.txt
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
[ clg: replaced lingua by terminology ]
Message-Id:
<e20319dcf0ec37bedd915c740c3813eb0e58ead4.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fcd4fdc24c2814810fb3fab072aaac1fe3aebcc4
https://github.com/qemu/qemu/commit/fcd4fdc24c2814810fb3fab072aaac1fe3aebcc4
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
Log Message:
-----------
docs: Rename ppc-spapr-hcalls.txt to ppc-spapr-hcalls.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2776112a7f843229d93651be152b3b2696fc14b2
https://github.com/qemu/qemu/commit/2776112a7f843229d93651be152b3b2696fc14b2
Author: Leonardo Garcia <lagarcia@br.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/ppc/pseries.rst
Log Message:
-----------
Link new ppc-spapr-hcalls.rst file to pseries.rst.
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id:
<7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ed827c5519d45cdfb593dfe404edd23f4e5bb357
https://github.com/qemu/qemu/commit/ed827c5519d45cdfb593dfe404edd23f4e5bb357
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Extend float_exception_flags to 16 bits
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-2-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: df7e619210161f02a4376b96412f2d83b1751058
https://github.com/qemu/qemu/commit/df7e619210161f02a4376b96412f2d83b1751058
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf - Inf
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-3-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c61f6754060d85ff1a4325e97d4199702278f8b0
https://github.com/qemu/qemu/commit/c61f6754060d85ff1a4325e97d4199702278f8b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to Inf * 0
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-4-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5735d70a18efd5778bd986b237686dff8836ed03
https://github.com/qemu/qemu/commit/5735d70a18efd5778bd986b237686dff8836ed03
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flags specific to Inf / Inf and 0 / 0
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-5-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 446d37c2c931d1efd4efb8063b1fd16e39dae1b3
https://github.com/qemu/qemu/commit/446d37c2c931d1efd4efb8063b1fd16e39dae1b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to sqrt(-x)
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-6-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5bad095b4a4544c6a3915629f261480eb86a587f
https://github.com/qemu/qemu/commit/5bad095b4a4544c6a3915629f261480eb86a587f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to convert non-nan to int
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-7-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 85543880e66900eb49d9398fc5f5a5cf08a2e4f5
https://github.com/qemu/qemu/commit/85543880e66900eb49d9398fc5f5a5cf08a2e4f5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Add flag specific to signaling nans
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-8-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a868a577cbed8c2227efe482d37cf17f48938ba3
https://github.com/qemu/qemu/commit/a868a577cbed8c2227efe482d37cf17f48938ba3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_addsub for new flags
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-9-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0ff2d75f23e1c2ea72059dc3038a73486785bed2
https://github.com/qemu/qemu/commit/0ff2d75f23e1c2ea72059dc3038a73486785bed2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_mul for new flags
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-10-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7782a30a1cdaa6c255e8c8a5167469b95b003a0d
https://github.com/qemu/qemu/commit/7782a30a1cdaa6c255e8c8a5167469b95b003a0d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_op_div for new flags
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-11-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 89ac442c7e1c627632c95e7872c5bd7bff9d01b9
https://github.com/qemu/qemu/commit/89ac442c7e1c627632c95e7872c5bd7bff9d01b9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Move float_check_status from FPU_FCTI to translate
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_helper_* calls in gen_compute_fprf_float64
and protect only the first with set_fprf.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-12-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4787f42fe94a3a03a4f5a57bdd347436289fac02
https://github.com/qemu/qemu/commit/4787f42fe94a3a03a4f5a57bdd347436289fac02
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update float_invalid_cvt for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-13-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c63dce3d57d25de46f13012d0e7182e1ad782a06
https://github.com/qemu/qemu/commit/c63dce3d57d25de46f13012d0e7182e1ad782a06
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Fix VXCVI return value
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-14-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 039f881aa09b40645f1e9aed10fe6dfad08f6f5a
https://github.com/qemu/qemu/commit/039f881aa09b40645f1e9aed10fe6dfad08f6f5a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Remove inline from do_fri
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-15-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c55d876e997db678671a59b42f5bd81da619c50e
https://github.com/qemu/qemu/commit/c55d876e997db678671a59b42f5bd81da619c50e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use FloatRoundMode in do_fri
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211119160502.17432-16-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 3c2365f9b34b532808d89629e2e6059983258b14
https://github.com/qemu/qemu/commit/3c2365f9b34b532808d89629e2e6059983258b14
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Tidy inexact handling in do_fri
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-17-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 992ba1cf31eab9e19e382e20dd8f831f32d11740
https://github.com/qemu/qemu/commit/992ba1cf31eab9e19e382e20dd8f831f32d11740
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Clean up do_fri
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-18-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f0b59d0e9ce49609ebf94e61d63a200e58de4944
https://github.com/qemu/qemu/commit/f0b59d0e9ce49609ebf94e61d63a200e58de4944
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fmadd for new flags
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd,
whereas the previous *_maddsub_update_excp assumed it true.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-19-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 153334a1cab38639f83866881ac0ed7b646a0609
https://github.com/qemu/qemu/commit/153334a1cab38639f83866881ac0ed7b646a0609
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_fmadd
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-20-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9de0e444dbb26b5c1e85ef3ba54ef6bb073fc943
https://github.com/qemu/qemu/commit/9de0e444dbb26b5c1e85ef3ba54ef6bb073fc943
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Do not call do_float_check_status from do_fmadd
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-21-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fadb3c39e0e9e330dde104007c7275747de4a0dd
https://github.com/qemu/qemu/commit/fadb3c39e0e9e330dde104007c7275747de4a0dd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Split out do_frsp
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-22-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8df0167566ee37886744aacd76264374dc24a57e
https://github.com/qemu/qemu/commit/8df0167566ee37886744aacd76264374dc24a57e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update do_frsp for new flags
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-23-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 351ce3386f0c0fa1b37fbe937208deea9a3cf904
https://github.com/qemu/qemu/commit/351ce3386f0c0fa1b37fbe937208deea9a3cf904
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble in do_frsp
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-24-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 52801238f3d9d3becb1519b6836b8e4f17e875a4
https://github.com/qemu/qemu/commit/52801238f3d9d3becb1519b6836b8e4f17e875a4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update sqrt for new flags
Now that vxsqrt and vxsnan are computed directly by softfloat,
we don't need to recompute it. Split out float_invalid_op_sqrt
to be used in several places. This fixes VSX_SQRT, which did
not order its tests correctly to eliminate NaN with sign set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-25-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c924763e8ede34dcec852dc615c9161116000d33
https://github.com/qemu/qemu/commit/c924763e8ede34dcec852dc615c9161116000d33
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update xsrqpi and xsrqpxp to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-26-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d893d69b3f458d6772691f27cd779c7b1923016a
https://github.com/qemu/qemu/commit/d893d69b3f458d6772691f27cd779c7b1923016a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fre to new flags
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-27-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 27c5518e6275a40399b46e46df34d1c4fa3c9e84
https://github.com/qemu/qemu/commit/27c5518e6275a40399b46e46df34d1c4fa3c9e84
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float64r32 arithmetic routines
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its float32 operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-28-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8a954b4a2a290d227cecf2942fb79dc3600a7738
https://github.com/qemu/qemu/commit/8a954b4a2a290d227cecf2942fb79dc3600a7738
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fmadds et al
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-29-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ec0c313cdc3ccd6d77212849391c5b4b77802825
https://github.com/qemu/qemu/commit/ec0c313cdc3ccd6d77212849391c5b4b77802825
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fsqrts
Use float64r32_sqrt. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-30-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e2423c1847edb44ca88f5d68ff660d0a125a59c9
https://github.com/qemu/qemu/commit/e2423c1847edb44ca88f5d68ff660d0a125a59c9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helpers for fadds, fsubs, fdivs
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-31-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 03386ec3563f9179e3e539b96081ec52620f6505
https://github.com/qemu/qemu/commit/03386ec3563f9179e3e539b96081ec52620f6505
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for fmuls
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-32-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7d107e1ab45dfdc4e2b58db127782ff521bb9d58
https://github.com/qemu/qemu/commit/7d107e1ab45dfdc4e2b58db127782ff521bb9d58
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: Add helper for frsqrtes
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 32, but perform the
operation with float64r32_div for consistency.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-33-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: df64d9b4b350ecdd09ccafbe0b00a19599ce538b
https://github.com/qemu/qemu/commit/df64d9b4b350ecdd09ccafbe0b00a19599ce538b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Update fres to new flags and float64r32
There is no double-rounding bug here, because the result is
merely an estimate to within 1 part in 256, but perform the
operation with float64r32_div for consistency.
Use float_flag_invalid_snan instead of recomputing the
snan-ness of the operand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-34-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: acfaa3fc472de8f47684bd1ceb92c94441db9c6f
https://github.com/qemu/qemu/commit/acfaa3fc472de8f47684bd1ceb92c94441db9c6f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only ones set within the register, and then a bitwise equality.
Fixes a bug in which a single-precision NaN is considered !SP,
because float64_eq(nan, nan) is always false.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211119160502.17432-35-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 24333a776c3a14f6cf207383b9fe178b811bbd3a
https://github.com/qemu/qemu/commit/24333a776c3a14f6cf207383b9fe178b811bbd3a
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable software TLB for the 7450 family
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
have not heard of any other software that is used with those CPUs in
QEMU. A current discussion [2] shows that the 7450 software TLB is
unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
3.15. With no known support in firmware or OS, this means that no code
for any of the 7450 CPUs is ever ran in QEMU.
Since the implementation in QEMU of the 7400 MMU is the same as the
7450, except for the software TLB vs. hardware TLB search, this patch
changes all 7450 cpus to the 7400 MMU model. This has the practical
effect of disabling the software TLB feature while keeping other
aspects of address translation working as expected.
This allow us to run software on the 7450 family again.
*- note that the 7448 is currently aliased in QEMU for a 7400, so it
is unaffected by this change.
1- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 643884a170bb111c069cba208235bbffdd604654
https://github.com/qemu/qemu/commit/643884a170bb111c069cba208235bbffdd604654
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Disable unused facilities in the e600 CPU
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9ab3ac241031038deb9df812578e7ba96eed2af0
https://github.com/qemu/qemu/commit/9ab3ac241031038deb9df812578e7ba96eed2af0
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Remove the software TLB model of 7450 CPUs
(Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447, 7447a and 7448)
The QEMU-side software TLB implementation for the 7450 family of CPUs
is being removed due to lack of known users in the real world. The
last users in the code were removed by the two previous commits.
A brief history:
The feature was added in QEMU by commit 7dbe11acd8 ("Handle all MMU
models in switches...") with the mention that Linux was not able to
handle the TLB miss interrupts and the MMU model would be kept
disabled.
At some point later, commit 8ca3f6c382 ("Allow selection of all
defined PowerPC 74xx (aka G4) CPUs.") enabled the model for the 7450
family without further justification.
We have since the year 2011 [1] been unable to run OpenBIOS in the
7450s and have not heard of any other software that is used with those
CPUs in QEMU. Attempts were made to find a guest OS that implemented
the TLB miss handlers and none were found among Linux 5.15, FreeBSD 13,
MacOS9, MacOSX and MorphOS 3.15.
All CPUs that registered this feature were moved to an MMU model that
replaces the software TLB with a QEMU hardware TLB
implementation. They can now run the same software as the 7400 CPUs,
including the OSes mentioned above.
References:
- https://bugs.launchpad.net/qemu/+bug/812398
https://gitlab.com/qemu-project/qemu/-/issues/86
- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
message id: 20211119134431.406753-1-farosas@linux.ibm.com
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6884e86c5d1e50404de9893c79fddd9381ec23c9
https://github.com/qemu/qemu/commit/6884e86c5d1e50404de9893c79fddd9381ec23c9
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Fix MPCxxx FPU interrupt address
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f20ecf721d9829f64309b533a37d9c9cb2543f0b
https://github.com/qemu/qemu/commit/f20ecf721d9829f64309b533a37d9c9cb2543f0b
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Remove 603e exception model
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 97b1cffb023b23af14d5ea2188ff80ccb3e4d621
https://github.com/qemu/qemu/commit/97b1cffb023b23af14d5ea2188ff80ccb3e4d621
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Set 601v exception model id
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211208123029.2052625-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9cc8a1b85c11e0dbacc35ef9fee86a5f68bcf450
https://github.com/qemu/qemu/commit/9cc8a1b85c11e0dbacc35ef9fee86a5f68bcf450
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: remove 401/403 CPUs
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211202191108.1291515-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 48dc996ad004d9ca768c04f9ffd09507450eec4c
https://github.com/qemu/qemu/commit/48dc996ad004d9ca768c04f9ffd09507450eec4c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Change kernel load address
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=1000000\0"
"fdt_addr_r=1800000\0"
"ramdisk_addr_r=1900000\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.
Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.
Change the kernel load address to match U-Boot expectations and fix
loading.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b052efc5a83ffda9e98c4da324ce14047c1672cc
https://github.com/qemu/qemu/commit/b052efc5a83ffda9e98c4da324ce14047c1672cc
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc: Mark the 'taihu' machine as deprecated
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added by this board. The users
can use the 'ref405ep' machine to test their PPC405 code instead.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211203164904.290954-2-thuth@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f15ef556fbef4330edbb6a7b5523eb7d88953c8d
https://github.com/qemu/qemu/commit/f15ef556fbef4330edbb6a7b5523eb7d88953c8d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc: Add trace-events for DCR accesses
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c090c0c7abbf92e413d911cb9cc50b8bf75ef428
https://github.com/qemu/qemu/commit/c090c0c7abbf92e413d911cb9cc50b8bf75ef428
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
M hw/ppc/trace-events
Log Message:
-----------
ppc/ppc405: Convert printfs to trace-events
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4d79fef8d4feb3c5135657bc2eb5907d0bfd1290
https://github.com/qemu/qemu/commit/4d79fef8d4feb3c5135657bc2eb5907d0bfd1290
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Drop flag parameter in ppc405_set_bootinfo()
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9876494c0fe60a50955fe6fb5ebc189b4507e4a4
https://github.com/qemu/qemu/commit/9876494c0fe60a50955fe6fb5ebc189b4507e4a4
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change ppc405ep_init() return value
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 856517777cd8d19793a3526c8933788b33fea611
https://github.com/qemu/qemu/commit/856517777cd8d19793a3526c8933788b33fea611
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Add some address space definitions
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 16f0b04c18621e11537cdd580abfdb95e09e812c
https://github.com/qemu/qemu/commit/16f0b04c18621e11537cdd580abfdb95e09e812c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Remove flash support
It is currently impossible to find a "ppc405_rom.bin" firmware file or
a full flash image for the PPC405EP evalution board. Even if it should
be technically possible to recreate such an image, it's unlikely that
anyone will do it since the board is obsolete and support in QEMU has
been broken for about 10 years.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 87ef6fda8a9b8e2f78e8bbfd36bdd8f56b6cc15a
https://github.com/qemu/qemu/commit/87ef6fda8a9b8e2f78e8bbfd36bdd8f56b6cc15a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Rework FW load
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffffffc where nothing is currently mapped. Support must
have been broken these last years.
Since we can not find a "ppc405_rom.bin" firmware file, request one to
be specified on the command line. A consequence of this change is that
the machine can be booted directly from Linux without any FW being
loaded. This is still broken and the CPU start address will be fixed
in the next changes.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6b5fd05db0c5dad257e5a92e7339f922ed6e0954
https://github.com/qemu/qemu/commit/6b5fd05db0c5dad257e5a92e7339f922ed6e0954
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Introduce ppc405_set_default_bootinfo()
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8191a1ec8a32e14f2fd91893224890039cf1d1b9
https://github.com/qemu/qemu/commit/8191a1ec8a32e14f2fd91893224890039cf1d1b9
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
ppc/ppc405: Fix boot from kernel
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset handler to setup the registers and to start the CPU
from the Linux kernel entry point.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 57a94fe5aac9365c75c08f270393a300f790e15a
https://github.com/qemu/qemu/commit/57a94fe5aac9365c75c08f270393a300f790e15a
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Change default PLL values at reset
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c93537df7e3033c29ae9eafdea97b3ad206932d1
https://github.com/qemu/qemu/commit/c93537df7e3033c29ae9eafdea97b3ad206932d1
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405.h
Log Message:
-----------
ppc/ppc405: Fix bi_pci_enetaddr2 field in U-Boot board information
The board information for the 405EP first appeared in commit 04f20795ac81
("Move PowerPC 405 specific definitions into a separate file ...")
An Ethernet address is a 6 byte number. Fix that.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211206103712.1866296-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 78f10ad1fa7e8551f2df6ecc8665ca3b68914360
https://github.com/qemu/qemu/commit/78f10ad1fa7e8551f2df6ecc8665ca3b68914360
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
ppc/ppc405: Add update of bi_procfreq field
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 44185a8bc7ae00b8db167360b799afe12c2b88e7
https://github.com/qemu/qemu/commit/44185a8bc7ae00b8db167360b799afe12c2b88e7
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: Fix xs{max, min}[cj]dp to use VSX registers
PPC instruction xsmaxcdp, xsmincdp, xsmaxjdp, and xsminjdp are using
vector registers when they should be using VSX ones. This happens
because the instructions are using GEN_VSX_HELPER_R3, which adds 32
to the register numbers, effectively making them vector registers.
This patch fixes it by changing these instructions to use
GEN_VSX_HELPER_X3.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-2-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 16253642d7ab4b23d5d7003d8c7ce0eb6743b2af
https://github.com/qemu/qemu/commit/16253642d7ab4b23d5d7003d8c7ce0eb6743b2af
Author: Victor Colombo <victor.colombo@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: Move xs{max,min}[cj]dp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Victor Colombo <victor.colombo@eldorado.org.br>
Message-Id: <20211213120958.24443-3-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 703b04764bdb7e5cf9ffe69b368bd80bb70d16a8
https://github.com/qemu/qemu/commit/703b04764bdb7e5cf9ffe69b368bd80bb70d16a8
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/translate/vsx-impl.c.inc
Log Message:
-----------
target/ppc: fix xscvqpdp register access
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-4-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a2f5fc80a1ab5150ddfe3bb7a8701a2eb5e9a4cf
https://github.com/qemu/qemu/commit/a2f5fc80a1ab5150ddfe3bb7a8701a2eb5e9a4cf
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
Log Message:
-----------
target/ppc: move xscvqpdp to decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211213120958.24443-5-victor.colombo@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b342aa38bd60ab223b3af7d8678ad6569df6910b
https://github.com/qemu/qemu/commit/b342aa38bd60ab223b3af7d8678ad6569df6910b
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Fix e6500 boot
When Altivec support was added to the e6500 kernel in 2012[1], the
QEMU code was not changed, so we don't register the VPU/VPUA
exceptions for the e6500:
qemu: fatal: Raised an exception without defined vector 73
Note that the error message says 73, instead of 32, which is the IVOR
for VPU. This is because QEMU knows only knows about the VPU interrupt
for the 7400s. In theory, we should not be raising _that_ VPU
interrupt, but instead another one specific for the e6500.
We unfortunately cannot register e6500-specific VPU/VPUA interrupts
because the SPEU/EFPDI interrupts also use IVOR32/33. These are
present only in the e500v1/2 versions. From the user manual:
e500v1, e500v2: only SPEU/EFPDI/EFPRI
e500mc, e5500: no SPEU/EFPDI/EFPRI/VPU/VPUA
e6500: only VPU/VPUA
So I'm leaving IVOR32/33 as SPEU/EFPDI, but altering the dispatch code
to convert the VPU #73 to a #32 when we're in the e6500. Since the
handling for SPEU and VPU is the same this is the only change that's
needed. The EFPDI is not implemented and will cause an abort. I don't
think it worth it changing the error message to take VPUA into
consideration, so I'm not changing anything there.
This bug was discussed in the thread:
https://lists.gnu.org/archive/html/qemu-ppc/2021-06/msg00222.html
1- https://git.kernel.org/torvalds/c/cd66cc2ee52
Reported-by: <mario@locati.it>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213133542.2608540-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: bfd8ef8982d20294122744d2f108d52085f471ad
https://github.com/qemu/qemu/commit/bfd8ef8982d20294122744d2f108d52085f471ad
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp"
This reverts commit 336e91f85332dda0ede4c1d15b87a19a0fb898a2.
It breaks the --disable-tcg build:
../target/ppc/excp_helper.c:463:29: error: implicit declaration of
function ‘cpu_ldl_code’ [-Werror=implicit-function-declaration]
We should not have TCG code in powerpc_excp because some kvm-only
routines use it indirectly to dispatch interrupts. See
kvm_handle_debug, spapr_mce_req_event and
spapr_do_system_reset_on_cpu.
We can re-introduce the change once we have split the interrupt
injection code between KVM and TCG.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20211209173323.2166642-1-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f86faa46a0bae7e8d192c619d1c3c2c7af88561d
https://github.com/qemu/qemu/commit/f86faa46a0bae7e8d192c619d1c3c2c7af88561d
Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/fpu_helper.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/non_signalling_xscv.c
Log Message:
-----------
target/ppc: do not silence SNaN in xscvspdpn
The non-signalling versions of VSX scalar convert to shorter/longer
precision insns doesn't silence SNaNs in the hardware. To better match
this behavior, use the non-arithmetic conversion of helper_todouble
instead of float32_to_float64. A test is added to prevent future
regressions.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[ clg: Fixed spelling in commit log ]
Message-Id: <20211214144459.1086343-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c2b94a1093cf2fcbf1fed05be8fa44fd807a30db
https://github.com/qemu/qemu/commit/c2b94a1093cf2fcbf1fed05be8fa44fd807a30db
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/meson.build
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
Log Message:
-----------
target/ppc: introduce PMUEventType and PMU overflow timers
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) will be of type 'PMU_EVENT_INVALID'. Events that are
inactive due to frozen counter bits state are of type
'PMU_EVENT_INACTIVE'. Other types added in this patch are
PMU_EVENT_CYCLES and PMU_EVENT_INSTRUCTIONS. More types will be added
later on.
Let's also add the required PMU cycle overflow timers. They will be used
to trigger cycle overflows when cycle events are being sampled. This
timer will call cpu_ppc_pmu_timer_cb(), which in turn calls
fire_PMC_interrupt(). Both functions are stubs that will be implemented
later on when EBB support is added.
Two new helper files are created to host this new logic.
cpu_ppc_pmu_init() will init all overflow timers during CPU init time.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 434c15a7bcde876351116dd468188d68b810f516
https://github.com/qemu/qemu/commit/434c15a7bcde876351116dd468188d68b810f516
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU basic cycle count for pseries TCG
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x80000000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
check the current MMCR0 and MMCR1 value and return the appropriate
PMUEventType. For PMCs 1-4, event 0x2 is the implementation dependent
value of PMU_EVENT_INSTRUCTIONS and event 0x1E is the implementation
dependent value of PMU_EVENT_CYCLES. These events are supported by IBM
Power chips since Power8, at least, and the Linux Perf driver makes use
of these events until kernel v5.15. For PMC1, event 0xF0 is the
architected PowerISA event for cycles. Event 0xFE is the architected
PowerISA event for instructions;
- if the counter is frozen, either via the global MMCR0_FC bit or its
individual frozen counter bits, PMU_EVENT_INACTIVE is returned;
- pmu_update_cycles() will go through each counter and update the
values of all PMCs that are counting cycles. This function will be
called every time a MMCR0 update is done to keep counters values
up to date. Upcoming patches will use this function to allow the
counters to be properly updated during read/write of the PMCs
and MMCR1 writes.
Given that the base CPU frequency is fixed at 1Ghz for both powernv and
pseries clock, cycle calculation assumes that 1 nanosecond equals 1 CPU
cycle. Cycle value is then calculated by adding the elapsed time, in
nanoseconds, of the last cycle update done via pmu_update_cycles().
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 95db4d7f6f6c9643b801103bca53f2cdbcf6170e
https://github.com/qemu/qemu/commit/95db4d7f6f6c9643b801103bca53f2cdbcf6170e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on PMCs r/w
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the required wiring for that and make our lives a bit easier in the
next patches.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e8e2752eff92620352ea76173448091cc2fbc1cb
https://github.com/qemu/qemu/commit/e8e2752eff92620352ea76173448091cc2fbc1cb
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/helper.h
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
Log Message:
-----------
target/ppc: PMU: update counters on MMCR1 write
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses MMCRA, MMCR2 and MMCR3 to
control the PMU. These three registers aren't being handled in this
initial implementation, so for now we're controlling all the PMU
aspects using MMCR0, MMCR1 and the PMCs.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 16f43b8a320e3c96da2bf97f6bb65f4c854b3b2e
https://github.com/qemu/qemu/commit/16f43b8a320e3c96da2bf97f6bb65f4c854b3b2e
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/power8-pmu.c
Log Message:
-----------
target/ppc: enable PMU counter overflow with cycle events
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert
can trigger an event-based exception (to be implemented in the next patches)
if the MMCR0_EBE bit is set.
For now, overflowing the counter when the PMC is counting cycles will
just trigger a performance monitor alert. This is done by starting the
overflow timer to expire in the moment the overflow would be occuring. The
timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will
trigger the PMU alert and, if the conditions are met, an EBB exception.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 624586e53b8bde75a8c08b0b9a8cb6443c123892
https://github.com/qemu/qemu/commit/624586e53b8bde75a8c08b0b9a8cb6443c123892
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/power8-pmu-regs.c.inc
M target/ppc/power8-pmu.c
M target/ppc/power8-pmu.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: enable PMU instruction count
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated in
each translation block right before exiting it.
A new pmu_count_insns() helper in translation.c was added to do that.
After verifying that the PMU is counting instructions, call
helper_insns_inc(). This new helper from power8-pmu.c will add the
instructions to the relevant counters. It'll also be responsible for
triggering counter negative overflows as it is already being done with
cycles.
To verify whether the PMU is counting instructions or now, a new hflags
named 'HFLAGS_INSN_CNT' is introduced. This flag will match the internal
state of the PMU. We're be using this flag to avoid calling
helper_insn_inc() when we do not have a valid instruction event being
sampled.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0f44b28dae3ffb38aaef1ae3373c90d18f5097fc
https://github.com/qemu/qemu/commit/0f44b28dae3ffb38aaef1ae3373c90d18f5097fc
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/power8-pmu.c
M target/ppc/spr_tcg.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 278dd31f371afac8b6aed6bb8ea65ecfdd7476a1
https://github.com/qemu/qemu/commit/278dd31f371afac8b6aed6bb8ea65ecfdd7476a1
Author: Daniel Henrique Barboza <danielhb413@gmail.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
Log Message:
-----------
PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The following operations happens during an EBB:
- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).
The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].
This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.
[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1449d845a8c5a9238ff21f1124a54f8936f10208
https://github.com/qemu/qemu/commit/1449d845a8c5a9238ff21f1124a54f8936f10208
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb3.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under PHB3
This change will help us move the mapping of XSCOM regions under the
PHB3 realize routine, which will be necessary for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 14d7a6b23429607c0660f35cfc21bc64aee2ef2b
https://github.com/qemu/qemu/commit/14d7a6b23429607c0660f35cfc21bc64aee2ef2b
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3.c
Log Message:
-----------
ppc/pnv: Use the chip class to check the index of PHB3 devices
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ef87c2842ebef6f11e53a16f00e172a970865325
https://github.com/qemu/qemu/commit/ef87c2842ebef6f11e53a16f00e172a970865325
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Drop the "num-phbs" property
It is never used.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 8c698f45432896b75eaa81c804e4a6adebc96585
https://github.com/qemu/qemu/commit/8c698f45432896b75eaa81c804e4a6adebc96585
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb3_pbcq.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
This change will help us providing support for user created PHB3
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7af638c6e5c6563023ada6d773cab94c0eb0bf10
https://github.com/qemu/qemu/commit/7af638c6e5c6563023ada6d773cab94c0eb0bf10
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
When -nodefaults is supported for PHB3 devices, the phbs array under
the chip will be empty. This will break the XICSFabric handlers, and
all interrupt delivery, and the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PHB3 devices instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-7-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 06a8f3e83ca6ea5c4801476172509f3dccf1e678
https://github.com/qemu/qemu/commit/06a8f3e83ca6ea5c4801476172509f3dccf1e678
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 chip. Use that instead of num_phbs which fits POWER8 chips.
This will ease adding support for user created devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6c729a02d7243e0a1a4cd433152bcd6c66da2ce1
https://github.com/qemu/qemu/commit/6c729a02d7243e0a1a4cd433152bcd6c66da2ce1
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-9-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 68edb1537a413f1111a626d4471d05517915f63c
https://github.com/qemu/qemu/commit/68edb1537a413f1111a626d4471d05517915f63c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a "chip" property under the PHB4 model
And check the PEC index using the chip class.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-10-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5cb6c81d60b460fe6aa3a581d9699a7da780a653
https://github.com/qemu/qemu/commit/5cb6c81d60b460fe6aa3a581d9699a7da780a653
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
M include/hw/pci-host/pnv_phb4.h
Log Message:
-----------
ppc/pnv: Introduce a num_stack class attribute
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-11-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 437684122b5afa0f3adca673364190e3f4d469f1
https://github.com/qemu/qemu/commit/437684122b5afa0f3adca673364190e3f4d469f1
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Compute the PHB index from the PHB4 PEC model
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
The routine pnv_pec_phb_offset() is a bit complex but it also prepares
ground for PHB5 which has a different layout of stacks: 3 per PECs.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b113f89629e55acaf4e1bd49b564e7f72cb7f550
https://github.com/qemu/qemu/commit/b113f89629e55acaf4e1bd49b564e7f72cb7f550
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Remove "system-memory" property from PHB4 PEC
This is not useful and will be in the way for support of user created
PHB4 devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ac4f91e7fbef1223d915627de27890a3afdc2e64
https://github.com/qemu/qemu/commit/ac4f91e7fbef1223d915627de27890a3afdc2e64
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Move realize of PEC stacks under the PEC model
This change will help us providing support for user created PHB4
devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cdf906d7ea79afb3283b57e3cf1b89f1334f7f2b
https://github.com/qemu/qemu/commit/cdf906d7ea79afb3283b57e3cf1b89f1334f7f2b
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
When -nodefaults is supported for PHB4 devices, the pecs array under
the chip will be empty. This will break the 'info pic' HMP command.
Do a QOM loop on the chip children and look for PEC PHB4 devices
instead.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211213132830.108372-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 7df5dd3261197b8b6a87f725bc91e98e0779056e
https://github.com/qemu/qemu/commit/7df5dd3261197b8b6a87f725bc91e98e0779056e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/about/deprecated.rst
A docs/specs/ppc-spapr-hcalls.rst
R docs/specs/ppc-spapr-hcalls.txt
M docs/system/ppc/powernv.rst
M docs/system/ppc/pseries.rst
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M hw/misc/ivshmem.c
M hw/pci-host/pnv_phb3.c
M hw/pci-host/pnv_phb3_pbcq.c
M hw/pci-host/pnv_phb4.c
M hw/pci-host/pnv_phb4_pec.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M hw/ppc/ppc405.h
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/trace-events
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M include/hw/pci-host/pnv_phb3.h
M include/hw/pci-host/pnv_phb4.h
M include/hw/ppc/pnv.h
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/meson.build
M target/ppc/mmu_common.c
M target/ppc/mmu_helper.c
M target/ppc/power8-pmu-regs.c.inc
A target/ppc/power8-pmu.c
A target/ppc/power8-pmu.h
M target/ppc/spr_tcg.h
M target/ppc/translate.c
A target/ppc/translate/branch-impl.c.inc
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/vmx-impl.c.inc
M target/ppc/translate/vsx-impl.c.inc
M target/ppc/translate/vsx-ops.c.inc
M tests/qtest/ivshmem-test.c
M tests/tcg/ppc64/Makefile.target
M tests/tcg/ppc64le/Makefile.target
A tests/tcg/ppc64le/mtfsf.c
A tests/tcg/ppc64le/non_signalling_xscv.c
Log Message:
-----------
Merge tag 'pull-ppc-20211215' of https://github.com/legoater/qemu into staging
ppc 7.0 queue:
* General cleanup for Mac machines (Peter)
* Fixes for FPU exceptions (Lucas)
* Support for new ISA31 instructions (Matheus)
* Fixes for ivshmem (Daniel)
* Cleanups for PowerNV PHB (Christophe and Cedric)
* Updates of PowerNV and pSeries documentation (Leonardo and Daniel)
* Fixes for PowerNV (Daniel)
* Large cleanup of FPU implementation (Richard)
* Removal of SoftTLBs support for PPC74x CPUs (Fabiano)
* Fixes for exception models in MPCx and 60x CPUs (Fabiano)
* Removal of 401/403 CPUs (Cedric)
* Deprecation of taihu machine (Thomas)
* Large rework of PPC405 machine (Cedric)
* Fixes for VSX instructions (Victor and Matheus)
* Fix for e6500 CPU (Fabiano)
* Initial support for PMU (Daniel)
# gpg: Signature made Tue 14 Dec 2021 11:23:59 PM PST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20211215' of https://github.com/legoater/qemu: (102 commits)
ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices
ppc/pnv: Move realize of PEC stacks under the PEC model
ppc/pnv: Remove "system-memory" property from PHB4 PEC
ppc/pnv: Compute the PHB index from the PHB4 PEC model
ppc/pnv: Introduce a num_stack class attribute
ppc/pnv: Introduce a "chip" property under the PHB4 model
ppc/pnv: Introduce version and device_id class atributes for PHB4 devices
ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices
ppc/pnv: Use QOM hierarchy to scan PHB3 devices
ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize()
ppc/pnv: Drop the "num-phbs" property
ppc/pnv: Use the chip class to check the index of PHB3 devices
ppc/pnv: Introduce a "chip" property under PHB3
PPC64/TCG: Implement 'rfebb' instruction
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
target/ppc: enable PMU instruction count
target/ppc: enable PMU counter overflow with cycle events
target/ppc: PMU: update counters on MMCR1 write
target/ppc: PMU: update counters on PMCs r/w
target/ppc: PMU basic cycle count for pseries TCG
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e630bc7ec9dd...7df5dd326119
- [Qemu-commits] [qemu/qemu] 73944a: pseries: Update SLOF firmware image,
Richard Henderson <=