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[Qemu-commits] [qemu/qemu] 229c57: hw/intc: clean-up error reporting for
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 229c57: hw/intc: clean-up error reporting for failed ITS cmd |
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Date: |
Wed, 15 Dec 2021 10:39:49 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 229c57b1986484ea2cd1eb744e3492af7eee063e
https://github.com/qemu/qemu/commit/229c57b1986484ea2cd1eb744e3492af7eee063e
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/intc/arm_gicv3_its.c
Log Message:
-----------
hw/intc: clean-up error reporting for failed ITS cmd
While trying to debug a GIC ITS failure I saw some guest errors that
had poor formatting as well as leaving me confused as to what failed.
As most of the checks aren't possible without a valid dte split that
check apart and then check the other conditions in steps. This avoids
us relying on undefined data.
I still get a failure with the current kvm-unit-tests but at least I
know (partially) why now:
Exception return from AArch64 EL1 to AArch64 EL1 PC 0x40080588
PASS: gicv3: its-trigger: inv/invall: dev2/eventid=20 now triggers an LPI
ITS: MAPD devid=2 size = 0x8 itt=0x40430000 valid=0
INT dev_id=2 event_id=20
process_its_cmd: invalid command attributes: invalid dte: 0 for 2 (MEM_TX: 0)
PASS: gicv3: its-trigger: mapd valid=false: no LPI after device unmap
SUMMARY: 6 tests, 1 unexpected failures
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211112170454.3158925-1-alex.bennee@linaro.org
Cc: Shashi Mallela <shashi.mallela@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0b052414bdd4bc8d688a0eaf62f7a9ac417848a5
https://github.com/qemu/qemu/commit/0b052414bdd4bc8d688a0eaf62f7a9ac417848a5
Author: Joel Stanley <joel@jms.id.au>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: Add new boards
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be
removed in v7.0.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20211117065752.330632-2-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 38b1ed6c908c4a7d39897808d0a5c5fd5931d5a7
https://github.com/qemu/qemu/commit/38b1ed6c908c4a7d39897808d0a5c5fd5931d5a7
Author: Joel Stanley <joel@jms.id.au>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: Update OpenBMC image URL
This is the latest URL for the OpenBMC CI. The old URL still works, but
redirects.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-3-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d5dcb8512098ac9dd5ee20f065ac516942d4a26
https://github.com/qemu/qemu/commit/9d5dcb8512098ac9dd5ee20f065ac516942d4a26
Author: Joel Stanley <joel@jms.id.au>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: Give an example of booting a kernel
A common use case for the ASPEED machine is to boot a Linux kernel.
Provide a full example command line.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-4-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: b662fac6aa800669d3a802f1ddaa1910a42b77ab
https://github.com/qemu/qemu/commit/b662fac6aa800669d3a802f1ddaa1910a42b77ab
Author: Joel Stanley <joel@jms.id.au>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs: aspeed: ADC is now modelled
Move it to the supported list.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-id: 20211117065752.330632-5-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ab08c3467605365b44fab1b66bb6254db86814f6
https://github.com/qemu/qemu/commit/ab08c3467605365b44fab1b66bb6254db86814f6
Author: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/char/stm32f2xx_usart.c
Log Message:
-----------
Fix STM32F2XX USART data register readout
Fix issue where the data register may be overwritten by next character
reception before being read and returned.
Signed-off-by: Olivier Hériveaux <olivier.heriveaux@ledger.fr>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211128120723.4053-1-olivier.heriveaux@ledger.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a1d742d88b7c4aef31c265ee931dfc51ec4be017
https://github.com/qemu/qemu/commit/a1d742d88b7c4aef31c265ee931dfc51ec4be017
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
A hw/intc/arm_gicv3_cpuif_common.c
M hw/intc/meson.build
Log Message:
-----------
hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c
gicv3_set_gicv3state() is used by arm_gicv3_common.c in
arm_gicv3_common_realize(). Since we want to restrict
arm_gicv3_cpuif.c to TCG, extract gicv3_set_gicv3state()
to a new file. Add this file to the meson 'specific'
source set, since it needs access to "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a8a5546798c3b59d2a6c37734ec1804e706d84e1
https://github.com/qemu/qemu/commit/a8a5546798c3b59d2a6c37734ec1804e706d84e1
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/intc/Kconfig
M hw/intc/arm_gicv3.c
M hw/intc/meson.build
Log Message:
-----------
hw/intc/arm_gicv3: Introduce CONFIG_ARM_GIC_TCG Kconfig selector
The TYPE_ARM_GICV3 device is an emulated one. When using
KVM, it is recommended to use the TYPE_KVM_ARM_GICV3 device
(which uses in-kernel support).
When using --with-devices-FOO, it is possible to build a
binary with a specific set of devices. When this binary is
restricted to KVM accelerator, the TYPE_ARM_GICV3 device is
irrelevant, and it is desirable to remove it from the binary.
Therefore introduce the CONFIG_ARM_GIC_TCG Kconfig selector
which select the files required to have the TYPE_ARM_GICV3
device, but also allowing to de-select this device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211115223619.2599282-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3b39ba360d5606c8a321e611ad855891b13d08cf
https://github.com/qemu/qemu/commit/3b39ba360d5606c8a321e611ad855891b13d08cf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Hoist pc_next to a local variable in aarch64_tr_translate_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bf9dd2aa5fd88f0c161ff857342484f0fb42ff3f
https://github.com/qemu/qemu/commit/bf9dd2aa5fd88f0c161ff857342484f0fb42ff3f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Hoist pc_next to a local variable in arm_tr_translate_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0bb72bca7cb1cd282d2a55549db06a54d0319d7f
https://github.com/qemu/qemu/commit/0bb72bca7cb1cd282d2a55549db06a54d0319d7f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Hoist pc_next to a local variable in thumb_tr_translate_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 258a00e5a4a59dd4b0360a0aa4b8263b44d55cd0
https://github.com/qemu/qemu/commit/258a00e5a4a59dd4b0360a0aa4b8263b44d55cd0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Split arm_pre_translate_insn
Create arm_check_ss_active and arm_check_kernelpage.
Reverse the order of the tests. While it doesn't matter in practice,
because only user-only has a kernel page and user-only never sets
ss_active, ss_active has priority over execution exceptions and it
is best to keep them in the proper order.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 485088f7425ec7f99d3f21cafb028aa92639618d
https://github.com/qemu/qemu/commit/485088f7425ec7f99d3f21cafb028aa92639618d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Advance pc for arch single-step exception
The size of the code covered by a TranslationBlock cannot be 0;
this is checked via assert in tb_gen_code.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 936a6b86030a0db172b09a1ea953091a1555611e
https://github.com/qemu/qemu/commit/936a6b86030a0db172b09a1ea953091a1555611e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/tlb_helper.c
Log Message:
-----------
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
We will reuse this section of arm_deliver_fault for
raising pc alignment faults.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ee03027a2cef00f977a3d28242c0a250b8552495
https://github.com/qemu/qemu/commit/ee03027a2cef00f977a3d28242c0a250b8552495
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M linux-user/aarch64/cpu_loop.c
M target/arm/helper.h
M target/arm/syndrome.h
M target/arm/tlb_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Take an exception if PC is misaligned
For A64, any input to an indirect branch can cause this.
For A32, many indirect branch paths force the branch to be aligned,
but BXWritePC does not. This includes the BX instruction but also
other interworking changes to PC. Prior to v8, this case is UNDEFINED.
With v8, this is CONSTRAINED UNPREDICTABLE and may either raise an
exception or force align the PC.
We choose to raise an exception because we have the infrastructure,
it makes the generated code for gen_bx simpler, and it has the
possibility of catching more guest bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7055fe4baf4d8b331863e51a15e93d3bdea29e36
https://github.com/qemu/qemu/commit/7055fe4baf4d8b331863e51a15e93d3bdea29e36
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/gdbstub.c
M target/arm/machine.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Assert thumb pc is aligned
Misaligned thumb PC is architecturally impossible.
Assert is better than proceeding, in case we've missed
something somewhere.
Expand a comment about aligning the pc in gdbstub.
Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8dc89f1faa28af0df92d6c63ff249849a3e9c80e
https://github.com/qemu/qemu/commit/8dc89f1faa28af0df92d6c63ff249849a3e9c80e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Suppress bp for exceptions with more priority
Both single-step and pc alignment faults have priority over
breakpoint exceptions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0bdce4861f924a5efd5c57a7a40f2d8a4269fa80
https://github.com/qemu/qemu/commit/0bdce4861f924a5efd5c57a7a40f2d8a4269fa80
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/pcalign-a64.c
M tests/tcg/arm/Makefile.target
A tests/tcg/arm/pcalign-a32.c
Log Message:
-----------
tests/tcg: Add arm and aarch64 pc alignment tests
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e0e875a68a1cc699658a40b8449267c7460de60f
https://github.com/qemu/qemu/commit/e0e875a68a1cc699658a40b8449267c7460de60f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/i386/tcg/translate.c
Log Message:
-----------
target/i386: Use assert() to sanity-check b1 in SSE decode
In the SSE decode function gen_sse(), we combine a byte
'b' and a value 'b1' which can be [0..3], and switch on them:
b |= (b1 << 8);
switch (b) {
...
default:
unknown_op:
gen_unknown_opcode(env, s);
return;
}
In three cases inside this switch, we were then also checking for
"if (b1 >= 2) { goto unknown_op; }".
However, this can never happen, because the 'case' values in each place
are 0x0nn or 0x1nn and the switch will have directed the b1 == (2, 3)
cases to the default already.
This check was added in commit c045af25a52e9 in 2010; the added code
was unnecessary then as well, and was apparently intended only to
ensure that we never accidentally ended up indexing off the end
of an sse_op_table with only 2 entries as a result of future bugs
in the decode logic.
Change the checks to assert() instead, and make sure they're always
immediately before the array access they are protecting.
Fixes: Coverity CID 1460207
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9cafc0735f5451dd6c8845f2a5c2c73bd7a7580c
https://github.com/qemu/qemu/commit/9cafc0735f5451dd6c8845f2a5c2c73bd7a7580c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M include/hw/i386/microvm.h
M include/hw/i386/x86.h
Log Message:
-----------
include/hw/i386: Don't include qemu-common.h in .h files
The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
include/hw/i386/x86.h and include/hw/i386/microvm.h break this rule.
In fact, the include is not required at all, so we can just drop it
from both files.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211129200510.1233037-2-peter.maydell@linaro.org
Commit: 70a37f7faacbff7dcafdd444db15a264e02b8db5
https://github.com/qemu/qemu/commit/70a37f7faacbff7dcafdd444db15a264e02b8db5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M linux-user/hexagon/cpu_loop.c
M target/hexagon/cpu.h
Log Message:
-----------
target/hexagon/cpu.h: don't include qemu-common.h
The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
Move the include to linux-user/hexagon/cpu_loop.c, which needs it for
the declaration of cpu_exec_step_atomic().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20211129200510.1233037-3-peter.maydell@linaro.org
Commit: d073949f9c2327eddfd9361aa1d94cd129ed4948
https://github.com/qemu/qemu/commit/d073949f9c2327eddfd9361aa1d94cd129ed4948
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/rx/cpu.h
Log Message:
-----------
target/rx/cpu.h: Don't include qemu-common.h
The qemu-common.h header is not supposed to be included from any
other header files, only from .c files (as documented in a comment at
the start of it).
Nothing actually relies on target/rx/cpu.h including it, so we can
just drop the include.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-4-peter.maydell@linaro.org
Commit: 3508c0fac2b7055a341d30e67968506c7ed4f797
https://github.com/qemu/qemu/commit/3508c0fac2b7055a341d30e67968506c7ed4f797
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/arm/boot.c
M hw/arm/digic_boards.c
M hw/arm/highbank.c
M hw/arm/npcm7xx_boards.c
M hw/arm/sbsa-ref.c
M hw/arm/stm32f405_soc.c
M hw/arm/vexpress.c
M hw/arm/virt.c
Log Message:
-----------
hw/arm: Don't include qemu-common.h unnecessarily
A lot of C files in hw/arm include qemu-common.h when they don't
need anything from it. Drop the include lines.
omap1.c, pxa2xx.c and strongarm.c retain the include because they
use it for the prototype of qemu_get_timedate().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-id: 20211129200510.1233037-5-peter.maydell@linaro.org
Commit: 52a9f60935d394953dd6b47d01bb7eb47bc2592f
https://github.com/qemu/qemu/commit/52a9f60935d394953dd6b47d01bb7eb47bc2592f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct calculation of tlb range invalidate length
The calculation of the length of TLB range invalidate operations
in tlbi_aa64_range_get_length() is incorrect in two ways:
* the NUM field is 5 bits, but we read only 4 bits
* we miscalculate the page_shift value, because of an
off-by-one error:
TG 0b00 is invalid
TG 0b01 is 4K granule size == 4096 == 2^12
TG 0b10 is 16K granule size == 16384 == 2^14
TG 0b11 is 64K granule size == 65536 == 2^16
so page_shift should be (TG - 1) * 2 + 12
Thanks to the bug report submitter Cha HyunSoo for identifying
both these errors.
Fixes: 84940ed82552d3c ("target/arm: Add support for FEAT_TLBIRANGE")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/734
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211130173257.1274194-1-peter.maydell@linaro.org
Commit: 530cd6c26df47c4f294c6335c9829e6c968fe7a8
https://github.com/qemu/qemu/commit/530cd6c26df47c4f294c6335c9829e6c968fe7a8
Author: Patrick Venture <venture@google.com>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/net/npcm7xx_emc.c
Log Message:
-----------
hw/net: npcm7xx_emc fix missing queue_flush
The rx_active boolean change to true should always trigger a try_read
call that flushes the queue.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20211203221002.1719306-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cf1a5cc935c0a9e3952eaac480ba02361662a29f
https://github.com/qemu/qemu/commit/cf1a5cc935c0a9e3952eaac480ba02361662a29f
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/virt-acpi-build.c
Log Message:
-----------
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
When a virtio-iommu is instantiated, describe it using the ACPI VIOT
table.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-2-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 092cba0350f073d465492c39210a006e5cb18f63
https://github.com/qemu/qemu/commit/092cba0350f073d465492c39210a006e5cb18f63
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/arm/virt.c
M hw/virtio/virtio-iommu-pci.c
Log Message:
-----------
hw/arm/virt: Remove device tree restriction for virtio-iommu
virtio-iommu is now supported with ACPI VIOT as well as device tree.
Remove the restriction that prevents from instantiating a virtio-iommu
device under ACPI.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-3-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 80d28ccdb99de4f256f03977471dbf6544bb0df8
https://github.com/qemu/qemu/commit/80d28ccdb99de4f256f03977471dbf6544bb0df8
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Reject instantiation of multiple IOMMUs
We do not support instantiating multiple IOMMUs. Before adding a
virtio-iommu, check that no other IOMMU is present. This will detect
both "iommu=smmuv3" machine parameter and another virtio-iommu instance.
Fixes: 70e89132c9 ("hw/arm/virt: Add the virtio-iommu device tree mappings")
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-4-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 317500fea815937ecb1b4e2e04b5159ae8bf3b79
https://github.com/qemu/qemu/commit/317500fea815937ecb1b4e2e04b5159ae8bf3b79
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Use object_property_set instead of qdev_prop_set
To propagate errors to the caller of the pre_plug callback, use the
object_poperty_set*() functions directly instead of the qdev_prop_set*()
helpers.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-5-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 641f32f6845048eff0e1d729d1be7e26ea3784c5
https://github.com/qemu/qemu/commit/641f32f6845048eff0e1d729d1be7e26ea3784c5
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
A tests/data/acpi/q35/DSDT.viot
A tests/data/acpi/q35/VIOT.viot
A tests/data/acpi/virt/VIOT
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: allow updates of VIOT expected data files
Create empty data files and allow updates for the upcoming VIOT tests.
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-6-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 39d7554b2009157571089ab4c7a3630e0090edd7
https://github.com/qemu/qemu/commit/39d7554b2009157571089ab4c7a3630e0090edd7
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/qtest/bios-tables-test.c
Log Message:
-----------
tests/acpi: add test case for VIOT
Add two test cases for VIOT, one on the q35 machine and the other on
virt. To test complex topologies the q35 test has two PCIe buses that
bypass the IOMMU (and are therefore not described by VIOT), and two
buses that are translated by virtio-iommu.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-7-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cf7a348837f43672f721c7d8e9d88c921424fe88
https://github.com/qemu/qemu/commit/cf7a348837f43672f721c7d8e9d88c921424fe88
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/data/acpi/q35/DSDT.viot
M tests/data/acpi/q35/VIOT.viot
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: add expected blobs for VIOT test on q35 machine
Add expected blobs of the VIOT and DSDT table for the VIOT test on the
q35 machine.
Since the test instantiates a virtio device and two PCIe expander
bridges, DSDT.viot has more blocks than the base DSDT.
The VIOT table generated for the q35 test is:
[000h 0000 4] Signature : "VIOT" [Virtual I/O
Translation Table]
[004h 0004 4] Table Length : 00000070
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 3D
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 2] Node count : 0003
[026h 0038 2] Node offset : 0030
[028h 0040 8] Reserved : 0000000000000000
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
[031h 0049 1] Reserved : 00
[032h 0050 2] Length : 0010
[034h 0052 2] PCI Segment : 0000
[036h 0054 2] PCI BDF number : 0010
[038h 0056 8] Reserved : 0000000000000000
[040h 0064 1] Type : 01 [PCI Range]
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
[044h 0068 4] Endpoint start : 00003000
[048h 0072 2] PCI Segment start : 0000
[04Ah 0074 2] PCI Segment end : 0000
[04Ch 0076 2] PCI BDF start : 3000
[04Eh 0078 2] PCI BDF end : 30FF
[050h 0080 2] Output node : 0030
[052h 0082 6] Reserved : 000000000000
[058h 0088 1] Type : 01 [PCI Range]
[059h 0089 1] Reserved : 00
[05Ah 0090 2] Length : 0018
[05Ch 0092 4] Endpoint start : 00001000
[060h 0096 2] PCI Segment start : 0000
[062h 0098 2] PCI Segment end : 0000
[064h 0100 2] PCI BDF start : 1000
[066h 0102 2] PCI BDF end : 10FF
[068h 0104 2] Output node : 0030
[06Ah 0106 6] Reserved : 000000000000
And the DSDT diff is:
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/q35/DSDT, Fri Dec 10 15:03:08 2021
+ * Disassembly of /tmp/aml-H9Y5D1, Fri Dec 10 15:02:27 2021
*
* Original Table Header:
* Signature "DSDT"
- * Length 0x00002061 (8289)
+ * Length 0x000024B6 (9398)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0xFA
+ * Checksum 0xA7
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -3114,6 +3114,339 @@
}
}
+ Scope (\_SB)
+ {
+ Device (PC30)
+ {
+ Name (_UID, 0x30) // _UID: Unique ID
+ Name (_BBN, 0x30) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible
ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System
Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766")
/* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PC30._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0030, // Range Minimum
+ 0x0030, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Device (PC20)
+ {
+ Name (_UID, 0x20) // _UID: Unique ID
+ Name (_BBN, 0x20) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible
ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System
Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766")
/* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PC20._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0020, // Range Minimum
+ 0x0020, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Device (PC10)
+ {
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_BBN, 0x10) // _BBN: BIOS Bus Number
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID:
Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible
ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System
Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766")
/* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PC10._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0010, // Range Minimum
+ 0x0010, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ }
+ }
+
Scope (\_SB.PCI0)
{
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
@@ -3121,9 +3454,9 @@
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
- 0x00FF, // Range Maximum
+ 0x000F, // Range Maximum
0x0000, // Translation Offset
- 0x0100, // Length
+ 0x0010, // Length
,, )
IO (Decode16,
0x0CF8, // Range Minimum
@@ -3278,6 +3611,26 @@
}
}
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ }
+
+ Device (S18)
+ {
+ Name (_ADR, 0x00030000) // _ADR: Address
+ }
+
+ Device (S20)
+ {
+ Name (_ADR, 0x00040000) // _ADR: Address
+ }
+
+ Device (S28)
+ {
+ Name (_ADR, 0x00050000) // _ADR: Address
+ }
+
Method (PCNT, 0, NotSerialized)
{
}
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-8-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aed176558806674d030a8305d989d4e6a5073359
https://github.com/qemu/qemu/commit/aed176558806674d030a8305d989d4e6a5073359
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M tests/data/acpi/virt/VIOT
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: add expected blob for VIOT test on virt machine
The VIOT blob contains the following:
[000h 0000 4] Signature : "VIOT" [Virtual I/O
Translation Table]
[004h 0004 4] Table Length : 00000058
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 66
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 2] Node count : 0002
[026h 0038 2] Node offset : 0030
[028h 0040 8] Reserved : 0000000000000000
[030h 0048 1] Type : 03 [VirtIO-PCI IOMMU]
[031h 0049 1] Reserved : 00
[032h 0050 2] Length : 0010
[034h 0052 2] PCI Segment : 0000
[036h 0054 2] PCI BDF number : 0008
[038h 0056 8] Reserved : 0000000000000000
[040h 0064 1] Type : 01 [PCI Range]
[041h 0065 1] Reserved : 00
[042h 0066 2] Length : 0018
[044h 0068 4] Endpoint start : 00000000
[048h 0072 2] PCI Segment start : 0000
[04Ah 0074 2] PCI Segment end : 0000
[04Ch 0076 2] PCI BDF start : 0000
[04Eh 0078 2] PCI BDF end : 00FF
[050h 0080 2] Output node : 0030
[052h 0082 6] Reserved : 000000000000
Acked-by: Ani Sinha <ani@anisinha.ca>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Message-id: 20211210170415.583179-9-jean-philippe@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: aab8cfd4c3614a049b60333a3747aedffbd04150
https://github.com/qemu/qemu/commit/aab8cfd4c3614a049b60333a3747aedffbd04150
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-15 (Wed, 15 Dec 2021)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/Kconfig
M hw/arm/boot.c
M hw/arm/digic_boards.c
M hw/arm/highbank.c
M hw/arm/npcm7xx_boards.c
M hw/arm/sbsa-ref.c
M hw/arm/stm32f405_soc.c
M hw/arm/vexpress.c
M hw/arm/virt-acpi-build.c
M hw/arm/virt.c
M hw/char/stm32f2xx_usart.c
M hw/intc/Kconfig
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_cpuif.c
A hw/intc/arm_gicv3_cpuif_common.c
M hw/intc/arm_gicv3_its.c
M hw/intc/meson.build
M hw/net/npcm7xx_emc.c
M hw/virtio/virtio-iommu-pci.c
M include/hw/i386/microvm.h
M include/hw/i386/x86.h
M linux-user/aarch64/cpu_loop.c
M linux-user/hexagon/cpu_loop.c
M target/arm/debug_helper.c
M target/arm/gdbstub.c
M target/arm/helper.c
M target/arm/helper.h
M target/arm/machine.c
M target/arm/syndrome.h
M target/arm/tlb_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/hexagon/cpu.h
M target/i386/tcg/translate.c
M target/rx/cpu.h
A tests/data/acpi/q35/DSDT.viot
A tests/data/acpi/q35/VIOT.viot
A tests/data/acpi/virt/VIOT
M tests/qtest/bios-tables-test.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/pcalign-a64.c
M tests/tcg/arm/Makefile.target
A tests/tcg/arm/pcalign-a32.c
Log Message:
-----------
Merge tag 'pull-target-arm-20211215' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* ITS: error reporting cleanup
* aspeed: improve documentation
* Fix STM32F2XX USART data register readout
* allow emulated GICv3 to be disabled in non-TCG builds
* fix exception priority for singlestep, misaligned PC, bp, etc
* Correct calculation of tlb range invalidate length
* npcm7xx_emc: fix missing queue_flush
* virt: Add VIOT ACPI table for virtio-iommu
* target/i386: Use assert() to sanity-check b1 in SSE decode
* Don't include qemu-common unnecessarily
# gpg: Signature made Wed 15 Dec 2021 02:39:37 AM PST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20211215' of
https://git.linaro.org/people/pmaydell/qemu-arm: (33 commits)
tests/acpi: add expected blob for VIOT test on virt machine
tests/acpi: add expected blobs for VIOT test on q35 machine
tests/acpi: add test case for VIOT
tests/acpi: allow updates of VIOT expected data files
hw/arm/virt: Use object_property_set instead of qdev_prop_set
hw/arm/virt: Reject instantiation of multiple IOMMUs
hw/arm/virt: Remove device tree restriction for virtio-iommu
hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu
hw/net: npcm7xx_emc fix missing queue_flush
target/arm: Correct calculation of tlb range invalidate length
hw/arm: Don't include qemu-common.h unnecessarily
target/rx/cpu.h: Don't include qemu-common.h
target/hexagon/cpu.h: don't include qemu-common.h
include/hw/i386: Don't include qemu-common.h in .h files
target/i386: Use assert() to sanity-check b1 in SSE decode
tests/tcg: Add arm and aarch64 pc alignment tests
target/arm: Suppress bp for exceptions with more priority
target/arm: Assert thumb pc is aligned
target/arm: Take an exception if PC is misaligned
target/arm: Split compute_fsr_fsc out of arm_deliver_fault
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/0da610688356...aab8cfd4c361
- [Qemu-commits] [qemu/qemu] 229c57: hw/intc: clean-up error reporting for failed ITS cmd,
Richard Henderson <=