[Qemu-commits] [qemu/qemu] 621f70: spapr/xive: Add source status helpers

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[Qemu-commits] [qemu/qemu] 621f70: spapr/xive: Add source status helpers

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] 621f70: spapr/xive: Add source status helpers
Date:	Thu, 21 Oct 2021 08:29:10 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 621f70d21027a914eda1446134193a24e7a662d5
      
https://github.com/qemu/qemu/commit/621f70d21027a914eda1446134193a24e7a662d5
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/intc/spapr_xive.c
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/xive.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  spapr/xive: Add source status helpers

and use them to set and test the ASSERTED bit of LSI sources.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211004212141.432954-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 6f4912a4160f157217730b0affdcb6c92c24ca76
      
https://github.com/qemu/qemu/commit/6f4912a4160f157217730b0affdcb6c92c24ca76
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use tcg_constant_i32() in gen_setb()

Avoid using TCG temporaries for the -1 and 8 constant values.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211003141711.3673181-2-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 491b3cca3653bf36db67f91be0e3db64682bef91
      
https://github.com/qemu/qemu/commit/491b3cca3653bf36db67f91be0e3db64682bef91
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use tcg_constant_i64() in gen_brh()

The mask of the Byte-Reverse Halfword opcode is a read-only
constant. We can avoid using a TCG temporary by moving the
mask to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211003141711.3673181-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: a8dcb8da8a95edde3d6d8bb6a0502d50ed632557
      
https://github.com/qemu/qemu/commit/a8dcb8da8a95edde3d6d8bb6a0502d50ed632557
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/ppc.c

  Log Message:
  -----------
  target/ppc: Fix the test raising the decrementer exception

Commit 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer") introduced
new int64t variables and broke the test triggering the decrementer
exception. Revert partially the change to evaluate both clause of the
if statement.

Reported-by: Coverity CID 1464061
Fixes: 4d9b8ef9b5ab ("target/ppc: Fix 64-bit decrementer")
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211005053324.441132-1-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 3c706d02522fb031e79823fd14b121878dccbcc6
      
https://github.com/qemu/qemu/commit/3c706d02522fb031e79823fd14b121878dccbcc6
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/spapr_softmmu.c

  Log Message:
  -----------
  hw/ppc/spapr_softmmu: Reduce include list

Commit 962104f0448 ("hw/ppc: moved hcalls that depend on softmmu")
introduced a lot of unnecessary #include directives. Remove them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20211006170801.178023-1-philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 644c68696e8335f80d4a9295db0445505e24d8e2
      
https://github.com/qemu/qemu/commit/644c68696e8335f80d4a9295db0445505e24d8e2
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/intc/spapr_xive_kvm.c

  Log Message:
  -----------
  spapr/xive: Use xive_esb_rw() to trigger interrupts

xive_esb_rw() is the common routine used for memory accesses on ESB
page. Use it for triggers also.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211006210546.641102-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 5ae3d2e8ba37def4b3ca38f220200bf5721317e0
      
https://github.com/qemu/qemu/commit/5ae3d2e8ba37def4b3ca38f220200bf5721317e0
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/ppc.c

  Log Message:
  -----------
  hw/ppc: Fix iothread locking in the 405 code

When using u-boot as firmware with the taihu board, QEMU aborts with
this assertion:

 ERROR:../accel/tcg/tcg-accel-ops.c:79:tcg_handle_interrupt: assertion failed:
  (qemu_mutex_iothread_locked())

Running QEMU with "-d in_asm" shows that the crash happens when writing
to SPR 0x3f2, so we are missing to lock the iothread in the code path
here.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211006071140.565952-1-thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 252fcf36bba483493365e91c2f98569de29a43fd
      
https://github.com/qemu/qemu/commit/252fcf36bba483493365e91c2f98569de29a43fd
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    A tests/acceptance/ppc_405.py

  Log Message:
  -----------
  tests/acceptance: Add tests for the ppc405 boards

Using the U-Boot firmware, we can check that at least the serial console
of the ppc405 boards is still usable.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211011125930.750217-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[dwg: Added an extra tag at Philippe's suggestion]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 66c6b40aba13807506f20c7522f4930c9ffc76ce
      
https://github.com/qemu/qemu/commit/66c6b40aba13807506f20c7522f4930c9ffc76ce
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M linux-user/ppc/signal.c
    M tests/tcg/ppc64/Makefile.target
    M tests/tcg/ppc64le/Makefile.target
    A tests/tcg/ppc64le/signal_save_restore_xer.c

  Log Message:
  -----------
  linux-user/ppc: Fix XER access in save/restore_user_regs

We should use cpu_read_xer/cpu_write_xer to save/restore the complete
register since some of its bits are in other fields of CPUPPCState. A
test is added to prevent future regressions.

Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-2-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 7974dc5900f7c128232782b0b39ccd40001bdb08
      
https://github.com/qemu/qemu/commit/7974dc5900f7c128232782b0b39ccd40001bdb08
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/gdbstub.c

  Log Message:
  -----------
  target/ppc: Fix XER access in gdbstub

The value of XER is split in multiple fields of CPUPPCState, like
env->xer and env->so. To get/set the whole register from gdb, we should
use cpu_read_xer/cpu_write_xer.

Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-3-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 10de0521889d36633450e35b22f6a45ef856226d
      
https://github.com/qemu/qemu/commit/10de0521889d36633450e35b22f6a45ef856226d
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M linux-user/elfload.c
    M target/ppc/cpu.c
    M target/ppc/cpu.h

  Log Message:
  -----------
  linux-user: Fix XER access in ppc version of elf_core_copy_regs

env->xer doesn't hold some bits of XER, like OV and CA. To write the
complete register in the core dump we should read XER value with
cpu_read_xer.

Reported-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-4-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 3938cacdb2367c203fd796af3f8c70cdb70c5007
      
https://github.com/qemu/qemu/commit/3938cacdb2367c203fd796af3f8c70cdb70c5007
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/monitor.c

  Log Message:
  -----------
  target/ppc: Fix XER access in monitor

We can't read env->xer directly, as it does not contain some bits of
XER. Instead, we should have a callback that uses cpu_read_xer to read
the complete register.

Fixes: da91a00f191f ("target-ppc: Split out SO, OV, CA fields from XER")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211014223234.127012-5-matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 239fec2497907f2adf7e6b9fdda4138e81bac619
      
https://github.com/qemu/qemu/commit/239fec2497907f2adf7e6b9fdda4138e81bac619
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Restrict memory to 2 gigabytes

The CHRP spec this board confirms to only allows 2 GiB of system
memory below 4 GiB as the high 2 GiB is allocated to IO and system
resources. To avoid problems with memory overlapping these areas
restrict RAM to 2 GiB similar to mac_newworld.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<54f58229a69c9c1cca21bcecad700b3d7052edd5.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 99173b679a346d6a92dbb685adecf5c419288c0c
      
https://github.com/qemu/qemu/commit/99173b679a346d6a92dbb685adecf5c419288c0c
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Warn when using VOF but no kernel is specified

Issue a warning when using VOF (which is the default) but no -kernel
option given to let users know that it will likely fail as the guest
has nothing to run. It is not a hard error because it may still be
useful to start the machine without further options for testing or
inspecting it from monitor without actually booting it.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<a4ec9a900df772b91e9f69ca7a0799d8ae293e5a.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 94cd1ffbe1a8b7f08df76e14d9226804cc21b56c
      
https://github.com/qemu/qemu/commit/94cd1ffbe1a8b7f08df76e14d9226804cc21b56c
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Implement get-time-of-day RTAS function with VOF

This is needed for Linux to access RTC time.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<6233eb07c680d6c74427e11b9641958f98d53378.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: bd20cde50bb1a3b47fcba02432edc6141d9fb1d0
      
https://github.com/qemu/qemu/commit/bd20cde50bb1a3b47fcba02432edc6141d9fb1d0
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/pci-host/mv64361.c
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Access MV64361 registers via their memory region

Instead of relying on the mapped address of the MV64361 registers
access them via their memory region. This is not a problem at reset
time when these registers are mapped at the default address but the
guest could change this later and then the RTAS calls accessing PCI
config registers could fail. None of the guests actually do this so
this only avoids a theoretical problem not seen in practice.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<b6f768023603dc2c4d130720bcecdbea459b7668.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d
      
https://github.com/qemu/qemu/commit/d200ea14b7ec5b9f0eaf1eee6e8fc47c359ee40d
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Add constants for PCI config addresses

Define a constant for PCI config addresses to make it clearer what
these numbers are.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<9bd8e84d02d91693b71082a1fadeb86e6bce3025.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 284c0486e7872243458b956b9a91bc757b59a44c
      
https://github.com/qemu/qemu/commit/284c0486e7872243458b956b9a91bc757b59a44c
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/pegasos2.c

  Log Message:
  -----------
  ppc/pegasos2: Implement power-off RTAS function with VOF

This only helps Linux guests as only that seems to use it.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: 
<1c1e030f2bbc86e950b3310fb5922facdc21ef86.1634241019.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 5ff1dfdf66f99c5208187cc2716a3a974f22b7c7
      
https://github.com/qemu/qemu/commit/5ff1dfdf66f99c5208187cc2716a3a974f22b7c7
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M MAINTAINERS
    A tests/acceptance/ppc_bamboo.py

  Log Message:
  -----------
  tests/acceptance: Add a test for the bamboo ppc board

The kernel and initrd from the "Aboriginal Linux" project can be
used to run some tests on the bamboo ppc machine.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211015090008.1299609-1-thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 6fa5726be6a52b246335cb86a3c118cdfd40c677
      
https://github.com/qemu/qemu/commit/6fa5726be6a52b246335cb86a3c118cdfd40c677
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Filter mtmsr[d] input before setting MSR

PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or
MSR[LE]", but the current code only filters the GPR-provided value if
L=1. This behavior caused some problems in FreeBSD, and a build option
was added to work around the issue [1], but it seems that the bug was
not reported in launchpad/gitlab. This patch address the issue in qemu,
so the option on FreeBSD should no longer be required.

[1] 
https://cgit.freebsd.org/src/commit/?id=4efb1ca7d2a44cfb33d7f9e18bd92f8d68dcfee0

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211015181940.197982-1-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: f7460df27162d1643f74677d53fad4328142c6a9
      
https://github.com/qemu/qemu/commit/f7460df27162d1643f74677d53fad4328142c6a9
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/helper_regs.c
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: add MMCR0 PMCC bits to hflags

We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1. This requires several PMU related
registers to be exposed to userspace (problem state). PowerISA v3.1
dictates that the PMCC bits of the MMCR0 register controls the level of
access of the PMU registers to problem state.

This patch start things off by exposing both PMCC bits to hflags,
allowing us to access them via DisasContext in the read/write callbacks
that we're going to add next.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-2-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 565cb1096733dae6d388244e03d60d680f6eca84
      
https://github.com/qemu/qemu/commit/565cb1096733dae6d388244e03d60d680f6eca84
  Author: Gustavo Romero <gromero@linux.ibm.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    A target/ppc/power8-pmu-regs.c.inc
    M target/ppc/spr_tcg.h
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: add user read/write functions for MMCR0

Userspace need access to PMU SPRs to be able to operate the PMU. One of
such SPRs is MMCR0.

MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU
register. This class of registers has common read/write rules that are
governed by MMCR0 PMCC bits. MMCR0 is also not fully exposed to problem
state: only MMCR0_FC, MMCR0_PMAO and MMCR0_PMAE bits are
readable/writable in this case.

This patch exposes MMCR0 to userspace by doing the following:

- two new callbacks, spr_read_MMCR0_ureg() and spr_write_MMCR0_ureg(),
are added to be used as problem state read/write callbacks of UMMCR0.
Both callbacks filters the amount of bits userspace is able to
read/write by using a MMCR0_UREG_MASK;

- problem state access control is done by the spr_groupA_read_allowed()
and spr_groupA_write_allowed() helpers. These helpers will read the
current PMCC bits from DisasContext and check whether the read/write
MMCR0 operation is valid or noti;

- to avoid putting exclusive PMU logic into the already loaded
translate.c file, let's create a new 'power8-pmu-regs.c.inc' file that
will hold all the spr_read/spr_write functions of PMU registers.

The 'power8' name of this new file intends to hint about the proven
support of the PMU logic to be added. The code has been tested with the
IBM POWER chip family, POWER8 being the oldest version tested. This
doesn't mean that the PMU logic will break with any other PPC64 chip
that implements Book3s, but rather that we can't assert that it works
properly with any Book3s compliant chip.

CC: Gustavo Romero <gustavo.romero@linaro.org>
Signed-off-by: Gustavo Romero <gromero@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-3-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 7b3ecf16c81c16eb3cf171b0bd63c08f1a5dd942
      
https://github.com/qemu/qemu/commit/7b3ecf16c81c16eb3cf171b0bd63c08f1a5dd942
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/power8-pmu-regs.c.inc
    M target/ppc/spr_tcg.h

  Log Message:
  -----------
  target/ppc: add user read/write functions for MMCR2

Similar to the previous patch, let's add problem state read/write access to
the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered
to be read/written by userspace.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-4-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: cedf706956e7440653b18ac2c2a9452b8d710577
      
https://github.com/qemu/qemu/commit/cedf706956e7440653b18ac2c2a9452b8d710577
  Author: Daniel Henrique Barboza <danielhb413@gmail.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M target/ppc/cpu_init.c
    M target/ppc/power8-pmu-regs.c.inc
    M target/ppc/spr_tcg.h

  Log Message:
  -----------
  target/ppc: adding user read/write functions for PMCs

Problem state needs to be able to read and write the PMU counters,
otherwise it won't be aware of any sampling result that the PMU produces
after a Perf run.

This patch does that in a similar fashion as already done in the
previous patches. PMCs 5 and 6 have a special condition, aside from the
constraints that are common with PMCs 1-4, where they are not part of the
PMU if MMCR0_PMCC is 0b11.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-5-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 6f9e8515c106650fbba7222c8f66234c8546c025
      
https://github.com/qemu/qemu/commit/6f9e8515c106650fbba7222c8f66234c8546c025
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M hw/ppc/ppc4xx_pci.c

  Log Message:
  -----------
  hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels

Recent Linux kernels are accessing the PCI device in slot 0 that
represents the PCI host bridge. This causes ppc4xx_pci_map_irq()
to return -1 which causes an assert() later:

 hw/pci/pci.c:262: pci_bus_change_irq_level: Assertion `irq_num >= 0' failed.

Thus we should allocate an IRQ line for the device in slot 0, too.
To avoid changes to the outside of ppc4xx_pci.c, we map it to
the internal IRQ number 4 which will then happily be ignored since
ppc440_bamboo.c does not wire it up.

With these changes it is now possible again to use recent Linux
kernels for the bamboo board.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211019091817.469003-1-thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: e016b58f6ed2e07bde45da7d6792b6c93879a3cf
      
https://github.com/qemu/qemu/commit/e016b58f6ed2e07bde45da7d6792b6c93879a3cf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-21 (Thu, 21 Oct 2021)

  Changed paths:
    M MAINTAINERS
    M hw/intc/spapr_xive.c
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/xive.c
    M hw/pci-host/mv64361.c
    M hw/ppc/pegasos2.c
    M hw/ppc/ppc.c
    M hw/ppc/ppc4xx_pci.c
    M hw/ppc/spapr_softmmu.c
    M include/hw/ppc/xive.h
    M linux-user/elfload.c
    M linux-user/ppc/signal.c
    M target/ppc/cpu.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/gdbstub.c
    M target/ppc/helper_regs.c
    M target/ppc/monitor.c
    A target/ppc/power8-pmu-regs.c.inc
    M target/ppc/spr_tcg.h
    M target/ppc/translate.c
    A tests/acceptance/ppc_405.py
    A tests/acceptance/ppc_bamboo.py
    M tests/tcg/ppc64/Makefile.target
    M tests/tcg/ppc64le/Makefile.target
    A tests/tcg/ppc64le/signal_save_restore_xer.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-6.2-20211021' into 
staging

ppc patch queue 2021-10-21

Here's the next batch of ppc target related patches for qemu-6.2.
Highlights are:
 * Some fixes and minimal tests for old embedded ppc platforms
 * The beginnings of PMU emulation in TCG from Daniel Barboza
 * Some improvements to the pegasos2 platform
 * A number of TCG bugfixes from the folks at the El Dorado Institute
 * A few other assorted bugfixes and cleanups

# gpg: Signature made Wed 20 Oct 2021 09:19:04 PM PDT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" 
[unknown]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" 
[full]

* remotes/dgibson/tags/ppc-for-6.2-20211021: (25 commits)
  hw/ppc/ppc4xx_pci: Fix ppc4xx_pci_map_irq() for recent Linux kernels
  target/ppc: adding user read/write functions for PMCs
  target/ppc: add user read/write functions for MMCR2
  target/ppc: add user read/write functions for MMCR0
  target/ppc: add MMCR0 PMCC bits to hflags
  target/ppc: Filter mtmsr[d] input before setting MSR
  tests/acceptance: Add a test for the bamboo ppc board
  ppc/pegasos2: Implement power-off RTAS function with VOF
  ppc/pegasos2: Add constants for PCI config addresses
  ppc/pegasos2: Access MV64361 registers via their memory region
  ppc/pegasos2: Implement get-time-of-day RTAS function with VOF
  ppc/pegasos2: Warn when using VOF but no kernel is specified
  ppc/pegasos2: Restrict memory to 2 gigabytes
  target/ppc: Fix XER access in monitor
  linux-user: Fix XER access in ppc version of elf_core_copy_regs
  target/ppc: Fix XER access in gdbstub
  linux-user/ppc: Fix XER access in save/restore_user_regs
  tests/acceptance: Add tests for the ppc405 boards
  hw/ppc: Fix iothread locking in the 405 code
  spapr/xive: Use xive_esb_rw() to trigger interrupts
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/afc9fcde5529...e016b58f6ed2
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