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[Qemu-commits] [qemu/qemu] 719f87: target/mips: Check nanoMIPS DSP MULT[

From: Richard Henderson
Subject: [Qemu-commits] [qemu/qemu] 719f87: target/mips: Check nanoMIPS DSP MULT[U] accumulato...
Date: Mon, 18 Oct 2021 09:19:06 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 719f874b83792951faa3fe67378eca4034bec3dc
      
https://github.com/qemu/qemu/commit/719f874b83792951faa3fe67378eca4034bec3dc
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-17 (Sun, 17 Oct 2021)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6

Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04,
MULT and MULTU opcodes:

  The value of ac selects an accumulator numbered from 0 to 3.
  When ac=0, this refers to the original HI/LO register pair of the
  MIPS32 architecture.

  In Release 6 of the MIPS Architecture, accumulators are eliminated
  from MIPS32.

Ensure pre-Release 6 is restricted to HI/LO registers pair.

Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part 
4")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: e07f3e265b90d078d69c1f305563f04f1371b7aa
      
https://github.com/qemu/qemu/commit/e07f3e265b90d078d69c1f305563f04f1371b7aa
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/mips/boston.c

  Log Message:
  -----------
  hw/mips/boston: Massage memory map information

Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Use local 'regaddr' in gen_firmware(), fix coding style]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211002184539.169-2-jiaxun.yang@flygoat.com>


  Commit: 10e3f30ff730624094a2fe6a81aaa72064853036
      
https://github.com/qemu/qemu/commit/10e3f30ff730624094a2fe6a81aaa72064853036
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/mips/boston.c

  Log Message:
  -----------
  hw/mips/boston: Allow loading elf kernel and dtb

ELF kernel allows us debugging much easier with DWARF symbols.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Fix coding style]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211002184539.169-3-jiaxun.yang@flygoat.com>


  Commit: 723038999ef42fec4f845841d2d35a52f9ab1dbe
      
https://github.com/qemu/qemu/commit/723038999ef42fec4f845841d2d35a52f9ab1dbe
  Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/mips/boston.c

  Log Message:
  -----------
  hw/mips/boston: Add FDT generator

Generate FDT on our own if no dtb argument supplied.
Avoid introducing unused device in FDT with user supplied dtb.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
[PMD: Fix coding style]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211002184539.169-4-jiaxun.yang@flygoat.com>


  Commit: 7da51cb391bc1100b941d04a0e9fec2cdc5b9632
      
https://github.com/qemu/qemu/commit/7da51cb391bc1100b941d04a0e9fec2cdc5b9632
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Remove unused register from MSA 2R/2RF instruction format

Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211003175743.3738710-2-f4bug@amsat.org>


  Commit: 2b537a3d856e2500acc321c9333f03b36a829f4e
      
https://github.com/qemu/qemu/commit/2b537a3d856e2500acc321c9333f03b36a829f4e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in gen_msa_elm_df()

Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-3-f4bug@amsat.org>


  Commit: e81a48b9e7fb3db72b7820b0342779227bf0510f
      
https://github.com/qemu/qemu/commit/e81a48b9e7fb3db72b7820b0342779227bf0510f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in gen_msa_2rf()

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-4-f4bug@amsat.org>


  Commit: 74341af7d6c7093bba0893a7efd53d30aa50a200
      
https://github.com/qemu/qemu/commit/74341af7d6c7093bba0893a7efd53d30aa50a200
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in gen_msa_2r()

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-5-f4bug@amsat.org>


  Commit: 1b5c0a11471cd0c3c2f206fd49e31972a2dc3bad
      
https://github.com/qemu/qemu/commit/1b5c0a11471cd0c3c2f206fd49e31972a2dc3bad
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_i32() in gen_msa_3rf()

Avoid using a TCG temporary by moving Data Format to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-6-f4bug@amsat.org>


  Commit: 469a316dc42cd669ab502a385fdd3539fd45e36e
      
https://github.com/qemu/qemu/commit/469a316dc42cd669ab502a385fdd3539fd45e36e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/msa_translate.c

  Log Message:
  -----------
  target/mips: Use explicit extract32() calls in gen_msa_i5()

We already use sextract32(), use extract32() for completeness
instead of open-coding it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-7-f4bug@amsat.org>


  Commit: d2db0f729da6946873b1352bfb7c12c2c9f91fb0
      
https://github.com/qemu/qemu/commit/d2db0f729da6946873b1352bfb7c12c2c9f91fb0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()

The offset is constant and read-only: move it to the constant pool.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-9-f4bug@amsat.org>


  Commit: 0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f
      
https://github.com/qemu/qemu/commit/0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Fix DEXTRV_S.H DSP opcode

While for the DEXTR_S.H opcode:

  "The shift argument is provided in the instruction."

For the DEXTRV_S.H opcode we have:

  "The five least-significant bits of register rs provide the
   shift argument, interpreted as a five-bit unsigned integer;
   the remaining bits in rs are ignored."

While 't1' contains the 'rs' register content (the shift value
for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
We can directly use the v1_t TCG register which already contains
this shift value.

Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>


  Commit: cfddceba7f9f56a5564015962154dccd242f5c8b
      
https://github.com/qemu/qemu/commit/cfddceba7f9f56a5564015962154dccd242f5c8b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()

Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4
("target-mips: Add ASE DSP accumulator instructions"), the
'v2_t' TCG temporary has never been used. Remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>


  Commit: 7c8eae45c0c12c92055486184f779d57a7677948
      
https://github.com/qemu/qemu/commit/7c8eae45c0c12c92055486184f779d57a7677948
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/ide/via.c

  Log Message:
  -----------
  via-ide: Set user_creatable to false

This model only works as a function of the via superio chip not as a
standalone PCI device.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211015092159.3E863748F57@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 3a2f166fe05ce4b00ca781d7abd08e6accd6e472
      
https://github.com/qemu/qemu/commit/3a2f166fe05ce4b00ca781d7abd08e6accd6e472
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/isa/vt82c686.c

  Log Message:
  -----------
  vt82c686: Move common code to via_isa_realize

The vt82c686b_realize and vt8231_realize methods are almost identical,
factor out the common parts to a via_isa_realize function to avoid
code duplication.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<7cb7a16ff4daf8f48d576246255bea1fd355207c.1634259980.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: a4d65b701ffce52b69b5b6c3f253519129af182e
      
https://github.com/qemu/qemu/commit/a4d65b701ffce52b69b5b6c3f253519129af182e
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/isa/vt82c686.c
    M include/hw/isa/vt82c686.h

  Log Message:
  -----------
  vt82c686: Add a method to VIA_ISA to raise ISA interrupts

Other functions in the VT82xx chips need to raise ISA interrupts. Keep
a reference to them in the device state and add via_isa_set_irq() to
allow setting their state.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: 
<778c04dc2c8affac060b8edf9e8d7dab3c3e04eb.1634259980.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 2792cf20ca7eed0e354a0ed731422411faca4908
      
https://github.com/qemu/qemu/commit/2792cf20ca7eed0e354a0ed731422411faca4908
  Author: BALATON Zoltan <balaton@eik.bme.hu>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/ide/via.c

  Log Message:
  -----------
  via-ide: Avoid using isa_get_irq()

Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using isa_get_irq() that has a comment saying
it should not be used.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: 
<26cb1848c9fc0360df7a57c2c9ba5e03c4a692b5.1634259980.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 9c050b661d3a43dfe2fd44106e559b39706d1296
      
https://github.com/qemu/qemu/commit/9c050b661d3a43dfe2fd44106e559b39706d1296
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-10-18 (Mon, 18 Oct 2021)

  Changed paths:
    M hw/ide/via.c
    M hw/isa/vt82c686.c
    M hw/mips/boston.c
    M include/hw/isa/vt82c686.h
    M target/mips/tcg/msa_translate.c
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/philmd/tags/mips-20211018' into staging

MIPS patches queue

Hardware emulation:
- Generate FDT blob for Boston machine (Jiaxun)
- VIA chipset cleanups (Zoltan)

TCG:
- Use tcg_constant() in Compact branch and MSA opcodes
- Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6
- Fix DEXTRV_S.H DSP opcode
- Remove unused TCG temporary for some DSP opcodes

# gpg: Signature made Sun 17 Oct 2021 03:50:57 PM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]

* remotes/philmd/tags/mips-20211018:
  via-ide: Avoid using isa_get_irq()
  vt82c686: Add a method to VIA_ISA to raise ISA interrupts
  vt82c686: Move common code to via_isa_realize
  via-ide: Set user_creatable to false
  target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()
  target/mips: Fix DEXTRV_S.H DSP opcode
  target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()
  target/mips: Use explicit extract32() calls in gen_msa_i5()
  target/mips: Use tcg_constant_i32() in gen_msa_3rf()
  target/mips: Use tcg_constant_i32() in gen_msa_2r()
  target/mips: Use tcg_constant_i32() in gen_msa_2rf()
  target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
  target/mips: Remove unused register from MSA 2R/2RF instruction format
  hw/mips/boston: Add FDT generator
  hw/mips/boston: Allow loading elf kernel and dtb
  hw/mips/boston: Massage memory map information
  target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/c148a0572130...9c050b661d3a
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