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[Qemu-commits] [qemu/qemu] 45a904: aspeed/smc: Add watchdog Control/Stat
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 45a904: aspeed/smc: Add watchdog Control/Status Registers |
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Date: |
Tue, 12 Oct 2021 04:42:57 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 45a904af3861b5457050e55271e1386a7040f04f
https://github.com/qemu/qemu/commit/45a904af3861b5457050e55271e1386a7040f04f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Add watchdog Control/Status Registers
The Aspeed SoCs have a dual boot function for firmware fail-over
recovery. The system auto-reboots from the second flash if the main
flash does not boot successfully within a certain amount of time. This
function is called alternate boot (ABR) in the FMC controllers.
On AST2400/AST2500, ABR is enabled by hardware strapping in SCU70 to
enable the 2nd watchdog timer, on AST2600, through register SCU510.
If the boot on the the main flash succeeds, the firmware should
disable the 2nd watchdog timer. If not, the BMC is reset and the CE0
and CE1 mappings are swapped to restart the BMC from the 2nd flash.
On the AST2600, the ABR registers controlling the 2nd watchdog timer
were moved from the watchdog register to the FMC controller and the
FMC model should be able to control WDT2 through its own register set.
This requires more work. For now, add dummy read/write handlers to let
the FW disable the 2nd watchdog without error.
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Reported-by: Peter Delevoryas <pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 32c54bd0ed622bbd1614ca9d1f5f108823f5cc11
https://github.com/qemu/qemu/commit/32c54bd0ed622bbd1614ca9d1f5f108823f5cc11
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Introduce aspeed_smc_error() helper
It unifies the errors reported by the Aspeed SMC model and also
removes some use of ctrl->name which will help us for the next
patches.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d0180a3ae48f71d4cb5b9cea89b49451e2dc9a47
https://github.com/qemu/qemu/commit/d0180a3ae48f71d4cb5b9cea89b49451e2dc9a47
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Stop using the model name for the memory regions
There is no real reason to use this name. It's simply nice to have in
the monitor output but it's a burden for the following patch which
removes the AspeedSMCController structure describing the controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 30b6852ce4c3398c54fc6f6c7ff5ccbf8c15cf4f
https://github.com/qemu/qemu/commit/30b6852ce4c3398c54fc6f6c7ff5ccbf8c15cf4f
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Drop AspeedSMCController structure
The characteristics of the Aspeed controllers are described in a
AspeedSMCController structure which is redundant with the
AspeedSMCClass. Move all attributes under the class and adapt the code
to use class attributes instead.
This is a large change but it is functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a7d78beff46f8e5c4343edca4b76675e6e55172e
https://github.com/qemu/qemu/commit/a7d78beff46f8e5c4343edca4b76675e6e55172e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/arm/aspeed.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash
There is no need to keep a reference of the flash qdev in the AspeedSMCFlash
state: the SPI bus takes ownership and will release its resources. Remove
AspeedSMCFlash::flash.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6bb55e796740a0b685831faa784efb0c38dd151c
https://github.com/qemu/qemu/commit/6bb55e796740a0b685831faa784efb0c38dd151c
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/arm/aspeed.c
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash
AspeedSMCFlash::size is only used to compute the initial size of the
boot_rom region. Not very useful, so directly call memory_region_size()
instead.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 10f915e4caefeacedf092eb90bfcce56e23e102e
https://github.com/qemu/qemu/commit/10f915e4caefeacedf092eb90bfcce56e23e102e
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'
'cs' is a more appropriate name to index SPI flash devices.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: f75b5331178b6771f2a96e92ce140dd2786c8282
https://github.com/qemu/qemu/commit/f75b5331178b6771f2a96e92ce140dd2786c8282
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: QOMify AspeedSMCFlash
AspeedSMCFlash is a small structure representing the AHB memory window
through which the contents of a flash device can be accessed with MMIOs.
Introduce an AspeedSMCFlash SysBusDevice model and attach the associated
memory region to the newly instantiated objects.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 71255c48e7b902483b94862f4882ddd050fe8ad8
https://github.com/qemu/qemu/commit/71255c48e7b902483b94862f4882ddd050fe8ad8
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Add default reset values
This simplifies the reset handler and has the benefit to remove some
"bad" use of the segments array as an identifier of the controller model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a779e37c681f17f83e1d31a68c030731ebc8c998
https://github.com/qemu/qemu/commit/a779e37c681f17f83e1d31a68c030731ebc8c998
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Introduce a new addr_width() class handler
The AST2400 SPI controller has a transitional HW interface and it
stores the address width currently in use in a different register than
all the other SMC controllers. It needs special handling when working
in 4B mode.
Make it clear through a class handler. This also removes another use
of the segments array.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 33456a8870f761ae4aba223a65082985d870bfc7
https://github.com/qemu/qemu/commit/33456a8870f761ae4aba223a65082985d870bfc7
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
aspeed/smc: Remove unused attribute 'irqline'
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 602610383f1be927830b903275ee02fcd368d6e8
https://github.com/qemu/qemu/commit/602610383f1be927830b903275ee02fcd368d6e8
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
aspeed/i2c: QOMify AspeedI2CBus
Introduce an AspeedI2CBus SysBusDevice model and attach the associated
memory region and IRQ to the newly instantiated objects.
Before this change, the I2C bus IRQs were all attached to the
SysBusDevice model of the I2C controller. Adapt the AST2600 SoC
realize routine to take into account this change.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 9fffe140a9424e80af5f30a149c9f0d67424434f
https://github.com/qemu/qemu/commit/9fffe140a9424e80af5f30a149c9f0d67424434f
Author: Peter Delevoryas <pdel@fb.com>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/gpio/aspeed_gpio.c
Log Message:
-----------
hw: aspeed_gpio: Fix pin I/O type declarations
Some of the pin declarations in the Aspeed GPIO module were incorrect,
probably because of confusion over which bits in the input and output
uint32_t's correspond to which groups in the label array. Since the
uint32_t literals are in big endian, it's sort of the opposite of what
would be intuitive. The least significant bit in ast2500_set_props[6]
corresponds to GPIOY0, not GPIOAB7.
GPIOxx indicates input and output capabilities, GPIxx indicates only
input, GPOxx indicates only output.
AST2500:
- Previously had GPIW0..GPIW7 and GPIX0..GPIX7, that's correct.
- Previously had GPIOY0..GPIOY3, should have been GPIOY0..GPIOY7.
- Previously had GPIOAB0..GPIOAB3 and GPIAB4..GPIAB7, should only have
been GPIOAB0..GPIOAB3.
AST2600:
- GPIOT0..GPIOT7 should have been GPIT0..GPIT7.
- GPIOU0..GPIOU7 should have been GPIU0..GPIU7.
- GPIW0..GPIW7 should have been GPIOW0..GPIOW7.
- GPIOY0..GPIOY7 and GPIOZ0...GPIOZ7 were disabled.
Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400
and AST2500")
Fixes: 36d737ee82b2972167e ("hw/gpio: Add in AST2600 specific implementation")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20210928032456.3192603-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 87bd33e8b0d2e08a6030ffced9433e5927360de5
https://github.com/qemu/qemu/commit/87bd33e8b0d2e08a6030ffced9433e5927360de5
Author: Peter Delevoryas <pdel@fb.com>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/gpio/aspeed_gpio.c
M include/hw/gpio/aspeed_gpio.h
Log Message:
-----------
hw: aspeed_gpio: Fix GPIO array indexing
The gpio array is declared as a dense array:
qemu_irq gpios[ASPEED_GPIO_NR_PINS];
(AST2500 has 228, AST2400 has 216, AST2600 has 208)
However, this array is used like a matrix of GPIO sets
(e.g. gpio[NR_SETS][NR_PINS_PER_SET] = gpio[8][32])
size_t offset = set * GPIOS_PER_SET + gpio;
qemu_set_irq(s->gpios[offset], !!(new & mask));
This can result in an out-of-bounds access to "s->gpios" because the
gpio sets do _not_ have the same length. Some of the groups (e.g.
GPIOAB) only have 4 pins. 228 != 8 * 32 == 256.
To fix this, I converted the gpio array from dense to sparse, to that
match both the hardware layout and this existing indexing code.
Fixes: 4b7f956862dc2db4c5c ("hw/gpio: Add basic Aspeed GPIO model for AST2400
and AST2500")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20211008033501.934729-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5857974d5d1133455e3c33e7c740786722418588
https://github.com/qemu/qemu/commit/5857974d5d1133455e3c33e7c740786722418588
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
A hw/adc/aspeed_adc.c
M hw/adc/meson.build
M hw/adc/trace-events
A include/hw/adc/aspeed_adc.h
Log Message:
-----------
hw/adc: Add basic Aspeed ADC model
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar to the STM ADC already in
the tree.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
[clg : support for multiple engines (AST2600) ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[pdel : refactored engine register struct fields to regs[] array field]
[pdel : added guest-error checking for upper-8 channel regs in AST2600]
[pdel : allow 16-bit reads of the channel data registers]
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20211005052604.1674891-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 199fd6230cf9e774991b60e1ee8a0ab35b6c5f9a
https://github.com/qemu/qemu/commit/199fd6230cf9e774991b60e1ee8a0ab35b6c5f9a
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm: Integrate ADC model into Aspeed SoC
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20211005052604.1674891-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a8eb9a43337b3243204c0a5d270165ca2ac03910
https://github.com/qemu/qemu/commit/a8eb9a43337b3243204c0a5d270165ca2ac03910
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/watchdog/trace-events
M hw/watchdog/wdt_aspeed.c
Log Message:
-----------
aspeed/wdt: Add trace events
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e2804a1ec97ceede14b69a2a6e9a8b5dfa0b15c2
https://github.com/qemu/qemu/commit/e2804a1ec97ceede14b69a2a6e9a8b5dfa0b15c2
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Dump address offset in trace events
The register index is currently printed and this is confusing.
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 81d8537cb297d57b0897797f1329e4d755a0eaf4
https://github.com/qemu/qemu/commit/81d8537cb297d57b0897797f1329e4d755a0eaf4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-10-12 (Tue, 12 Oct 2021)
Changed paths:
A hw/adc/aspeed_adc.c
M hw/adc/meson.build
M hw/adc/trace-events
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/gpio/aspeed_gpio.c
M hw/i2c/aspeed_i2c.c
M hw/ssi/aspeed_smc.c
M hw/watchdog/trace-events
M hw/watchdog/wdt_aspeed.c
A include/hw/adc/aspeed_adc.h
M include/hw/arm/aspeed_soc.h
M include/hw/gpio/aspeed_gpio.h
M include/hw/i2c/aspeed_i2c.h
M include/hw/ssi/aspeed_smc.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211012' into
staging
Aspeed patches :
* I2C QOMify (Cedric)
* SMC model cleanup and QOMify (Cedric)
* ADC model (Peter and Andrew)
* GPIO fixes (Peter)
# gpg: Signature made Tue 12 Oct 2021 12:36:22 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/clg/tags/pull-aspeed-20211012:
aspeed/smc: Dump address offset in trace events
aspeed/wdt: Add trace events
hw/arm: Integrate ADC model into Aspeed SoC
hw/adc: Add basic Aspeed ADC model
hw: aspeed_gpio: Fix GPIO array indexing
hw: aspeed_gpio: Fix pin I/O type declarations
aspeed/i2c: QOMify AspeedI2CBus
aspeed/smc: Remove unused attribute 'irqline'
aspeed/smc: Introduce a new addr_width() class handler
aspeed/smc: Add default reset values
aspeed/smc: QOMify AspeedSMCFlash
aspeed/smc: Rename AspeedSMCFlash 'id' to 'cs'
aspeed/smc: Remove the 'size' attribute from AspeedSMCFlash
aspeed/smc: Remove the 'flash' attribute from AspeedSMCFlash
aspeed/smc: Drop AspeedSMCController structure
aspeed/smc: Stop using the model name for the memory regions
aspeed/smc: Introduce aspeed_smc_error() helper
aspeed/smc: Add watchdog Control/Status Registers
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/c09124dcb840...81d8537cb297
- [Qemu-commits] [qemu/qemu] 45a904: aspeed/smc: Add watchdog Control/Status Registers,
Richard Henderson <=