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[Qemu-commits] [qemu/qemu] 01e75d: allwinner-h3: Switch to SMC as PSCI c
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 01e75d: allwinner-h3: Switch to SMC as PSCI conduit |
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Date: |
Fri, 01 Oct 2021 02:27:56 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 01e75d87834a5188f98defa2d1f88b69dca7e9a0
https://github.com/qemu/qemu/commit/01e75d87834a5188f98defa2d1f88b69dca7e9a0
Author: Alexander Graf <agraf@csgraf.de>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/arm/allwinner-h3.c
Log Message:
-----------
allwinner-h3: Switch to SMC as PSCI conduit
The Allwinner H3 SoC uses Cortex-A7 cores which support virtualization.
However, today we are configuring QEMU to use HVC as PSCI conduit.
That means HVC calls get trapped into QEMU instead of the guest's own
emulated CPU and thus break the guest's ability to execute virtualization.
Fix this by moving to SMC as conduit, freeing up HYP completely to the VM.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-id: 20210920203931.66527-1-agraf@csgraf.de
Fixes: 740dafc0ba0 ("hw/arm: add Allwinner H3 System-on-Chip")
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9fcd15b9193e819b6cc2fd0a45e3506148812bb4
https://github.com/qemu/qemu/commit/9fcd15b9193e819b6cc2fd0a45e3506148812bb4
Author: Alexander Graf <agraf@csgraf.de>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M target/arm/psci.c
Log Message:
-----------
arm: tcg: Adhere to SMCCC 1.3 section 5.2
The SMCCC 1.3 spec section 5.2 says
The Unknown SMC Function Identifier is a sign-extended value of (-1)
that is returned in the R0, W0 or X0 registers. An implementation must
return this error code when it receives:
* An SMC or HVC call with an unknown Function Identifier
* An SMC or HVC call for a removed Function Identifier
* An SMC64/HVC64 call from AArch32 state
To comply with these statements, let's always return -1 when we encounter
an unknown HVC or SMC call.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 68fbcc344ef6fb2dff0eb4cac0319ea7af010a7f
https://github.com/qemu/qemu/commit/68fbcc344ef6fb2dff0eb4cac0319ea7af010a7f
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/nvram/Kconfig
M hw/nvram/meson.build
A hw/nvram/xlnx-efuse-crc.c
A hw/nvram/xlnx-efuse.c
A include/hw/nvram/xlnx-efuse.h
Log Message:
-----------
hw/nvram: Introduce Xilinx eFuse QOM
This introduces the QOM for Xilinx eFuse, an one-time
field-programmable storage bit array.
The actual mmio interface to the array varies by device
families and will be provided in different change-sets.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-2-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9e4aa1fafef624ee4ae6006497bed0cc112135d3
https://github.com/qemu/qemu/commit/9e4aa1fafef624ee4ae6006497bed0cc112135d3
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/nvram/Kconfig
M hw/nvram/meson.build
A hw/nvram/xlnx-versal-efuse-cache.c
A hw/nvram/xlnx-versal-efuse-ctrl.c
A include/hw/nvram/xlnx-versal-efuse.h
Log Message:
-----------
hw/nvram: Introduce Xilinx Versal eFuse device
This implements the Xilinx Versal eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx Versal product family.
This device has two separate mmio interfaces, a controller
and a flatten readback.
The controller provides interfaces for field-programming,
configuration, control, and status.
The flatten readback is a cache to provide a byte-accessible
read-only interface to efficiently read efuse array.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-3-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 67fa02f89fbf7510b70080bbbea8ac0aa752e8ba
https://github.com/qemu/qemu/commit/67fa02f89fbf7510b70080bbbea8ac0aa752e8ba
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/nvram/Kconfig
M hw/nvram/meson.build
A hw/nvram/xlnx-zynqmp-efuse.c
A include/hw/nvram/xlnx-zynqmp-efuse.h
Log Message:
-----------
hw/nvram: Introduce Xilinx ZynqMP eFuse device
This implements the Xilinx ZynqMP eFuse, an one-time
field-programmable non-volatile storage device. There is
only one such device in the Xilinx ZynqMP product family.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-4-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 461a6a6f199944e466ddb808516e63cf064c0105
https://github.com/qemu/qemu/commit/461a6a6f199944e466ddb808516e63cf064c0105
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/nvram/Kconfig
M hw/nvram/meson.build
A hw/nvram/xlnx-bbram.c
A include/hw/nvram/xlnx-bbram.h
Log Message:
-----------
hw/nvram: Introduce Xilinx battery-backed ram
This device is present in Versal and ZynqMP product
families to store a 256-bit encryption key.
Co-authored-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Co-authored-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-5-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 393185bc9de599d82725c2a17d5db91d037745be
https://github.com/qemu/qemu/commit/393185bc9de599d82725c2a17d5db91d037745be
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
Connect the support for Versal Battery-Backed RAM (BBRAM)
The command argument:
-drive if=pflash,index=0,...
Can be used to optionally connect the bbram to a backend
storage, such that field-programmed values in one
invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and
its size must be 36 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-6-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5f4910ff12f88f9750608cbfe07895204405bed1
https://github.com/qemu/qemu/commit/5f4910ff12f88f9750608cbfe07895204405bed1
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M include/hw/arm/xlnx-versal.h
Log Message:
-----------
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
Connect the support for Versal eFUSE one-time field-programmable
bit array.
The command argument:
-drive if=pflash,index=1,...
Can be used to optionally connect the bit array to a
backend storage, such that field-programmed values
in one invocation can be made available to next
invocation.
The backend storage must be a seekable binary file, and
its size must be 3072 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-7-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7e47e15c8b47ac866e8f07998276b01e612a360a
https://github.com/qemu/qemu/commit/7e47e15c8b47ac866e8f07998276b01e612a360a
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/Kconfig
M hw/arm/xlnx-zcu102.c
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM)
The command argument:
-drive if=pflash,index=2,...
Can be used to optionally connect the bbram to a backend
storage, such that field-programmed values in one
invocation can be made available to next invocation.
The backend storage must be a seekable binary file, and
its size must be 36 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-8-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: db1264df32d5482cb49ea5acbd6dcf2f466325c2
https://github.com/qemu/qemu/commit/db1264df32d5482cb49ea5acbd6dcf2f466325c2
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/Kconfig
M hw/arm/xlnx-zcu102.c
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
Connect the support for ZynqMP eFUSE one-time field-programmable
bit array.
The command argument:
-drive if=pflash,index=3,...
Can be used to optionally connect the bit array to a
backend storage, such that field-programmed values
in one invocation can be made available to next
invocation.
The backend storage must be a seekable binary file, and
its size must be 768 bytes or larger. A file with all
binary 0's is a 'blank'.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-9-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 09e010aedeb0a20aefa1fa0c06cf421e80f25edd
https://github.com/qemu/qemu/commit/09e010aedeb0a20aefa1fa0c06cf421e80f25edd
Author: Tong Ho <tong.ho@xilinx.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M docs/system/arm/xlnx-versal-virt.rst
Log Message:
-----------
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
document.
Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0e2a76110465ec95fd9f2c4820f186ca8106ab49
https://github.com/qemu/qemu/commit/0e2a76110465ec95fd9f2c4820f186ca8106ab49
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64_be-linux-user.mak
Log Message:
-----------
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
The aarch64-linux QEMU usermode binaries can never run 32-bit
code, so they do not need to include the GDB XML for it.
(arm_cpu_register_gdb_regs_for_features() will not use these
XML files if the CPU has ARM_FEATURE_AARCH64, so we will not
advertise to gdb that we have them.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210921162901.17508-2-peter.maydell@linaro.org
Commit: d59b7cdccc6558f126c3081f7582131029c35660
https://github.com/qemu/qemu/commit/d59b7cdccc6558f126c3081f7582131029c35660
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix coding style issues in gdbstub code in helper.c
We're going to move this code to a different file; fix the coding
style first so checkpatch doesn't complain. This includes deleting
the spurious 'break' statements after returns in the
vfp_gdb_get_reg() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210921162901.17508-3-peter.maydell@linaro.org
Commit: 89f4f20e276e6e5dc08fca5e75e2bfbd92280072
https://github.com/qemu/qemu/commit/89f4f20e276e6e5dc08fca5e75e2bfbd92280072
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move gdbstub related code out of helper.c
Currently helper.c includes some code which is part of the arm
target's gdbstub support. This code has a better home: in gdbstub.c
and gdbstub64.c. Move it there.
Because aarch64_fpu_gdb_get_reg() and aarch64_fpu_gdb_set_reg() move
into gdbstub64.c, this means that they're now compiled only for
TARGET_AARCH64 rather than always. That is the only case when they
would ever be used, but it does mean that the ifdef in
arm_cpu_register_gdb_regs_for_features() needs to be adjusted to
match.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210921162901.17508-4-peter.maydell@linaro.org
Commit: b355f08a3724d3f29e1c177dde3a01b649108f98
https://github.com/qemu/qemu/commit/b355f08a3724d3f29e1c177dde3a01b649108f98
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M configs/targets/aarch64-softmmu.mak
M configs/targets/arm-linux-user.mak
M configs/targets/arm-softmmu.mak
M configs/targets/armeb-linux-user.mak
M gdb-xml/arm-neon.xml
A gdb-xml/arm-vfp-sysregs.xml
M gdb-xml/arm-vfp.xml
M gdb-xml/arm-vfp3.xml
M target/arm/gdbstub.c
Log Message:
-----------
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
Currently we send VFP XML which includes D0..D15 or D0..D31, plus
FPSID, FPSCR and FPEXC. The upstream GDB tolerates this, but its
definition of this XML feature does not include FPSID or FPEXC. In
particular, for M-profile cores there are no FPSID or FPEXC
registers, so advertising those is wrong.
Move FPSID and FPEXC into their own bit of XML which we only send for
A and R profile cores. This brings our definition of the XML
org.gnu.gdb.arm.vfp feature into line with GDB's own (at least for
non-Neon cores...) and means we don't claim to have FPSID and FPEXC
on M-profile.
(It seems unlikely to me that any gdbstub users really care about
being able to look at FPEXC and FPSID; but we've supplied them to gdb
for a decade and it's not hard to keep doing so.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210921162901.17508-5-peter.maydell@linaro.org
Commit: 739e95f5741b8efd74331bb74b9446bcb5ede71e
https://github.com/qemu/qemu/commit/739e95f5741b8efd74331bb74b9446bcb5ede71e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/scsi/esp-pci.c
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/scsi-bus.c
M hw/scsi/spapr_vscsi.c
M hw/scsi/virtio-scsi.c
M hw/scsi/vmw_pvscsi.c
M hw/usb/dev-storage-bot.c
M hw/usb/dev-storage-classic.c
M hw/usb/dev-uas.c
M include/hw/scsi/scsi.h
Log Message:
-----------
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
The function scsi_bus_new() creates a new SCSI bus; callers can
either pass in a name argument to specify the name of the new bus, or
they can pass in NULL to allow the bus to be given an automatically
generated unique name. Almost all callers want to use the
autogenerated name; the only exception is the virtio-scsi device.
Taking a name argument that should almost always be NULL is an
easy-to-misuse API design -- it encourages callers to think perhaps
they should pass in some standard name like "scsi" or "scsi-bus". We
don't do this anywhere for SCSI, but we do (incorrectly) do it for
other bus types such as i2c.
The function name also implies that it will return a newly allocated
object, when it in fact does in-place allocation. We more commonly
name such functions foo_init(), with foo_new() being the
allocate-and-return variant.
Replace all the scsi_bus_new() callsites with either:
* scsi_bus_init() for the usual case where the caller wants
an autogenerated bus name
* scsi_bus_init_named() for the rare case where the caller
needs to specify the bus name
and document that for the _named() version it's then the caller's
responsibility to think about uniqueness of bus names.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210923121153.23754-2-peter.maydell@linaro.org
Commit: 43417c0c27fd0851707a1f3bf50244d24aeeaf82
https://github.com/qemu/qemu/commit/43417c0c27fd0851707a1f3bf50244d24aeeaf82
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/ipack/ipack.c
M hw/ipack/tpci200.c
M include/hw/ipack/ipack.h
Log Message:
-----------
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
Rename ipack_bus_new_inplace() to ipack_bus_init(), to bring it in to
line with a "_init for in-place init, _new for allocate-and-return"
convention. Drop the 'name' argument, because the only caller does
not pass in a name. If a future caller does need to specify the bus
name, we should create an ipack_bus_init_named() function at that
point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20210923121153.23754-3-peter.maydell@linaro.org
Commit: 8d4cdf01f89fd834b952df2dd08f55e897a72ea8
https://github.com/qemu/qemu/commit/8d4cdf01f89fd834b952df2dd08f55e897a72ea8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/pci-host/raven.c
M hw/pci-host/versatile.c
M hw/pci/pci.c
M include/hw/pci/pci.h
Log Message:
-----------
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
Rename the pci_root_bus_new_inplace() function to
pci_root_bus_init(); this brings the bus type in to line with a
"_init for in-place init, _new for allocate-and-return" convention.
To do this we need to rename the implementation-internal function
that was using the pci_root_bus_init() name to
pci_root_bus_internal_init().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20210923121153.23754-4-peter.maydell@linaro.org
Commit: d637e1dc6de0e171dca6fbb5384668c642aa5ab6
https://github.com/qemu/qemu/commit/d637e1dc6de0e171dca6fbb5384668c642aa5ab6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/audio/intel-hda.c
M hw/block/fdc.c
M hw/block/swim.c
M hw/char/virtio-serial-bus.c
M hw/core/bus.c
M hw/core/sysbus.c
M hw/gpio/bcm2835_gpio.c
M hw/ide/qdev.c
M hw/ipack/ipack.c
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/macio.c
M hw/misc/macio/pmu.c
M hw/nubus/nubus-bridge.c
M hw/nvme/ctrl.c
M hw/nvme/subsys.c
M hw/pci/pci.c
M hw/pci/pci_bridge.c
M hw/s390x/event-facility.c
M hw/s390x/virtio-ccw.c
M hw/scsi/scsi-bus.c
M hw/sd/allwinner-sdhost.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sdhci.c
M hw/sd/ssi-sd.c
M hw/usb/bus.c
M hw/usb/dev-smartcard-reader.c
M hw/virtio/virtio-mmio.c
M hw/virtio/virtio-pci.c
M include/hw/qdev-core.h
Log Message:
-----------
qbus: Rename qbus_create_inplace() to qbus_init()
Rename qbus_create_inplace() to qbus_init(); this is more in line
with our usual naming convention for functions that in-place
initialize objects.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
Commit: 9388d1701efa87095d31ed5f68793dfc82cdd47e
https://github.com/qemu/qemu/commit/9388d1701efa87095d31ed5f68793dfc82cdd47e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/core/bus.c
M hw/hyperv/vmbus.c
M hw/i2c/core.c
M hw/isa/isa-bus.c
M hw/misc/auxbus.c
M hw/pci/pci.c
M hw/ppc/spapr_vio.c
M hw/s390x/ap-bridge.c
M hw/s390x/css-bridge.c
M hw/s390x/s390-pci-bus.c
M hw/ssi/ssi.c
M hw/xen/xen-bus.c
M hw/xen/xen-legacy-backend.c
M include/hw/qdev-core.h
Log Message:
-----------
qbus: Rename qbus_create() to qbus_new()
Rename the "allocate and return" qbus creation function to
qbus_new(), to bring it into line with our _init vs _new convention.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Message-id: 20210923121153.23754-6-peter.maydell@linaro.org
Commit: 82c74ac42e1b9e564a3c011dca6215d130b7e6a0
https://github.com/qemu/qemu/commit/82c74ac42e1b9e564a3c011dca6215d130b7e6a0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/ide/ahci.c
M hw/ide/cmd646.c
M hw/ide/isa.c
M hw/ide/macio.c
M hw/ide/microdrive.c
M hw/ide/mmio.c
M hw/ide/piix.c
M hw/ide/qdev.c
M hw/ide/sii3112.c
M hw/ide/via.c
M include/hw/ide/internal.h
Log Message:
-----------
ide: Rename ide_bus_new() to ide_bus_init()
The function ide_bus_new() does an in-place initialization. Rename
it to ide_bus_init() to follow our _init vs _new convention.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Acked-by: John Snow <jsnow@redhat.com> (Feel free to merge.)
Message-id: 20210923121153.23754-7-peter.maydell@linaro.org
Commit: 1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b
https://github.com/qemu/qemu/commit/1f4b2ec701b9d73d3fa7bb90c8b4376bc7d3c42b
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M hw/arm/sabrelite.c
Log Message:
-----------
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
The Linux spi-imx driver does not work on QEMU. The reason is that the
state of m25p80 loops in STATE_READING_DATA state after receiving
RDSR command, the new command is ignored. Before sending a new command,
CS line should be pulled high to make the state of m25p80 back to IDLE.
Currently the SPI flash CS line is connected to the SPI controller, but
on the real board, it's connected to GPIO3_19. This matches the ecspi1
device node in the board dts.
ecspi1 node in imx6qdl-sabrelite.dtsi:
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
flash: m25p80@0 {
compatible = "sst,sst25vf016b", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
Should connect the SSI_GPIO_CS to GPIO3_19 when adding a spi-nor to
spi1 on sabrelite machine.
Verified this patch on Linux v5.14.
Logs:
# echo "01234567899876543210" > test
# mtd_debug erase /dev/mtd0 0x0 0x1000
Erased 4096 bytes from address 0x00000000 in flash
# mtd_debug write /dev/mtdblock0 0x0 20 test
Copied 20 bytes from test to address 0x00000000 in flash
# mtd_debug read /dev/mtdblock0 0x0 20 test_out
Copied 20 bytes from address 0x00000000 in flash to test_out
# cat test_out
01234567899876543210#
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210927142825.491-1-xchengl.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bb4aa8f59e18412cff0d69f14aee7abba153161a
https://github.com/qemu/qemu/commit/bb4aa8f59e18412cff0d69f14aee7abba153161a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-30 (Thu, 30 Sep 2021)
Changed paths:
M configs/targets/aarch64-linux-user.mak
M configs/targets/aarch64-softmmu.mak
M configs/targets/aarch64_be-linux-user.mak
M configs/targets/arm-linux-user.mak
M configs/targets/arm-softmmu.mak
M configs/targets/armeb-linux-user.mak
M docs/system/arm/xlnx-versal-virt.rst
M gdb-xml/arm-neon.xml
A gdb-xml/arm-vfp-sysregs.xml
M gdb-xml/arm-vfp.xml
M gdb-xml/arm-vfp3.xml
M hw/Kconfig
M hw/arm/Kconfig
M hw/arm/allwinner-h3.c
M hw/arm/sabrelite.c
M hw/arm/xlnx-versal-virt.c
M hw/arm/xlnx-versal.c
M hw/arm/xlnx-zcu102.c
M hw/arm/xlnx-zynqmp.c
M hw/audio/intel-hda.c
M hw/block/fdc.c
M hw/block/swim.c
M hw/char/virtio-serial-bus.c
M hw/core/bus.c
M hw/core/sysbus.c
M hw/gpio/bcm2835_gpio.c
M hw/hyperv/vmbus.c
M hw/i2c/core.c
M hw/ide/ahci.c
M hw/ide/cmd646.c
M hw/ide/isa.c
M hw/ide/macio.c
M hw/ide/microdrive.c
M hw/ide/mmio.c
M hw/ide/piix.c
M hw/ide/qdev.c
M hw/ide/sii3112.c
M hw/ide/via.c
M hw/ipack/ipack.c
M hw/ipack/tpci200.c
M hw/isa/isa-bus.c
M hw/misc/auxbus.c
M hw/misc/mac_via.c
M hw/misc/macio/cuda.c
M hw/misc/macio/macio.c
M hw/misc/macio/pmu.c
M hw/nubus/nubus-bridge.c
M hw/nvme/ctrl.c
M hw/nvme/subsys.c
M hw/nvram/Kconfig
M hw/nvram/meson.build
A hw/nvram/xlnx-bbram.c
A hw/nvram/xlnx-efuse-crc.c
A hw/nvram/xlnx-efuse.c
A hw/nvram/xlnx-versal-efuse-cache.c
A hw/nvram/xlnx-versal-efuse-ctrl.c
A hw/nvram/xlnx-zynqmp-efuse.c
M hw/pci-host/raven.c
M hw/pci-host/versatile.c
M hw/pci/pci.c
M hw/pci/pci_bridge.c
M hw/ppc/spapr_vio.c
M hw/s390x/ap-bridge.c
M hw/s390x/css-bridge.c
M hw/s390x/event-facility.c
M hw/s390x/s390-pci-bus.c
M hw/s390x/virtio-ccw.c
M hw/scsi/esp-pci.c
M hw/scsi/esp.c
M hw/scsi/lsi53c895a.c
M hw/scsi/megasas.c
M hw/scsi/mptsas.c
M hw/scsi/scsi-bus.c
M hw/scsi/spapr_vscsi.c
M hw/scsi/virtio-scsi.c
M hw/scsi/vmw_pvscsi.c
M hw/sd/allwinner-sdhost.c
M hw/sd/bcm2835_sdhost.c
M hw/sd/pl181.c
M hw/sd/pxa2xx_mmci.c
M hw/sd/sdhci.c
M hw/sd/ssi-sd.c
M hw/ssi/ssi.c
M hw/usb/bus.c
M hw/usb/dev-smartcard-reader.c
M hw/usb/dev-storage-bot.c
M hw/usb/dev-storage-classic.c
M hw/usb/dev-uas.c
M hw/virtio/virtio-mmio.c
M hw/virtio/virtio-pci.c
M hw/xen/xen-bus.c
M hw/xen/xen-legacy-backend.c
M include/hw/arm/xlnx-versal.h
M include/hw/arm/xlnx-zynqmp.h
M include/hw/ide/internal.h
M include/hw/ipack/ipack.h
A include/hw/nvram/xlnx-bbram.h
A include/hw/nvram/xlnx-efuse.h
A include/hw/nvram/xlnx-versal-efuse.h
A include/hw/nvram/xlnx-zynqmp-efuse.h
M include/hw/pci/pci.h
M include/hw/qdev-core.h
M include/hw/scsi/scsi.h
M target/arm/gdbstub.c
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/psci.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930'
into staging
target-arm queue:
* allwinner-h3: Switch to SMC as PSCI conduit
* arm: tcg: Adhere to SMCCC 1.3 section 5.2
* xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices
* gdbstub related code cleanups
* Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
* Use _init vs _new convention in bus creation function names
* sabrelite: Connect SPI flash CS line to GPIO3_19
# gpg: Signature made Thu 30 Sep 2021 16:11:20 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits)
hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19
ide: Rename ide_bus_new() to ide_bus_init()
qbus: Rename qbus_create() to qbus_new()
qbus: Rename qbus_create_inplace() to qbus_init()
pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init()
ipack: Rename ipack_bus_new_inplace() to ipack_bus_init()
scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named()
target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML
target/arm: Move gdbstub related code out of helper.c
target/arm: Fix coding style issues in gdbstub code in helper.c
configs: Don't include 32-bit-only GDB XML in aarch64 linux configs
docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
hw/arm: xlnx-zcu102: Add Xilinx eFUSE device
hw/arm: xlnx-zcu102: Add Xilinx BBRAM device
hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device
hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device
hw/nvram: Introduce Xilinx battery-backed ram
hw/nvram: Introduce Xilinx ZynqMP eFuse device
hw/nvram: Introduce Xilinx Versal eFuse device
hw/nvram: Introduce Xilinx eFuse QOM
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/0021c4765a6b...bb4aa8f59e18
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