[Qemu-commits] [qemu/qemu] 23e607: target/riscv: Update the ePMP CSR address

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 23e60710d54ddf667a9b5cb9e563775d8e151bec
      
https://github.com/qemu/qemu/commit/23e60710d54ddf667a9b5cb9e563775d8e151bec
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Update the ePMP CSR address

Update the ePMP CSRs to match the 0.9.3 ePMP spec
https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
28c908de60b9b04fa20e63d113885c98586053f3.1630543194.git.alistair.francis@wdc.com


  Commit: 796b2d4bb3d08dd9581b81ee09f5c1ba06936f61
      
https://github.com/qemu/qemu/commit/796b2d4bb3d08dd9581b81ee09f5c1ba06936f61
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix satp write

These variables should be target_ulong. If truncated to int,
the bool conditions they indicate will be wrong.

As satp is very important for Linux, this bug almost fails every boot.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124539.222868-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 5ecb8a58213b96548731d2d362be1e92aae3413a
      
https://github.com/qemu/qemu/commit/5ecb8a58213b96548731d2d362be1e92aae3413a
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Expose interrupt pending bits as GPIO lines

Expose the 12 interrupt pending bits in MIP as GPIO lines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
069d6162f0bc2f4a4f5a44e73f6442b11c703c53.1630301632.git.alistair.francis@wdc.com


  Commit: b676a72f923172c05b66529f077fd5d6094fdafc
      
https://github.com/qemu/qemu/commit/b676a72f923172c05b66529f077fd5d6094fdafc
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/intc/sifive_clint.c
    M include/hw/intc/sifive_clint.h

  Log Message:
  -----------
  hw/intc: sifive_clint: Use RISC-V CPU GPIO lines

Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer and soft MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-id: 
946e1ef5e268b24084c7ddad84c146de62a56736.1630301632.git.alistair.francis@wdc.com


  Commit: 47748825310fb47f0054bcfd011dd8fa5b2728b4
      
https://github.com/qemu/qemu/commit/47748825310fb47f0054bcfd011dd8fa5b2728b4
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/intc/ibex_plic.c
    M hw/riscv/opentitan.c
    M include/hw/intc/ibex_plic.h

  Log Message:
  -----------
  hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines

Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com


  Commit: 1e430ed67e4dfd741c34bfc334eb09b7bda7984d
      
https://github.com/qemu/qemu/commit/1e430ed67e4dfd741c34bfc334eb09b7bda7984d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/intc/sifive_plic.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/intc/sifive_plic.h

  Log Message:
  -----------
  hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines

Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the external MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
0364190bfa935058a845c0fa1ecf650328840ad5.1630301632.git.alistair.francis@wdc.com


  Commit: 82f5b716aa5f6e7448f126e4dabc0c32e4bfd4f4
      
https://github.com/qemu/qemu/commit/82f5b716aa5f6e7448f126e4dabc0c32e4bfd4f4
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M hw/timer/ibex_timer.c
    M include/hw/timer/ibex_timer.h

  Log Message:
  -----------
  hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines

Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V
CPU GPIO lines to set the timer MIP bits.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com


  Commit: 48e52b032b80cb3c09f05457678f2c83fb5a0efb
      
https://github.com/qemu/qemu/commit/48e52b032b80cb3c09f05457678f2c83fb5a0efb
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/timer/Kconfig
    M hw/timer/meson.build
    A hw/timer/sifive_pwm.c
    M hw/timer/trace-events
    A include/hw/timer/sifive_pwm.h

  Log Message:
  -----------
  hw/timer: Add SiFive PWM support

This is the initial commit of the SiFive PWM timer. This is used by
guest software as a timer and is included in the SiFive FU540 SoC.

Signed-off-by: Justin Restivo <jrestivo@draper.com>
Signed-off-by: Alexandra Clifford <aclifford@draper.com>
Signed-off-by: Amanda Strnad <astrnad@draper.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
9f70a210acbfaf0e1ea6ad311ab892ac69134d8b.1631159656.git.alistair.francis@wdc.com


  Commit: f27c582219836cab2a571dd30a680ada963f87e7
      
https://github.com/qemu/qemu/commit/f27c582219836cab2a571dd30a680ada963f87e7
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M docs/system/riscv/sifive_u.rst
    M hw/riscv/Kconfig
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  sifive_u: Connect the SiFive PWM device

Connect the SiFive PWM device and expose it via the device tree.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com


  Commit: fe34a9a937704025c5a9884e426dbc6858bbd6b8
      
https://github.com/qemu/qemu/commit/fe34a9a937704025c5a9884e426dbc6858bbd6b8
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/intc/Kconfig
    M hw/intc/meson.build
    A hw/intc/riscv_aclint.c
    R hw/intc/sifive_clint.c
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    A include/hw/intc/riscv_aclint.h
    R include/hw/intc/sifive_clint.h

  Log Message:
  -----------
  hw/intc: Rename sifive_clint sources to riscv_aclint sources

We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
implementation so let's first rename the sources.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-2-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: db81b215710f47be1c9d38a1b160c4e3c353c6b3
      
https://github.com/qemu/qemu/commit/db81b215710f47be1c9d38a1b160c4e3c353c6b3
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/intc/riscv_aclint.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/intc/riscv_aclint.h

  Log Message:
  -----------
  hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT

The RISC-V ACLINT is more modular and backward compatible with
original SiFive CLINT so instead of duplicating the original
SiFive CLINT implementation we upgrade the current SiFive CLINT
implementation to RISC-V ACLINT implementation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-3-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: e5e1b657a1add0c5d8674091e918d21c1527d500
      
https://github.com/qemu/qemu/commit/e5e1b657a1add0c5d8674091e918d21c1527d500
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Re-factor FDT generation

We re-factor and break the FDT generation into smaller functions
so that it is easier to modify FDT generation for different
configurations of virt machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-4-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 36e5450c0eb00d8b231d06f1ad8e543f72b142e8
      
https://github.com/qemu/qemu/commit/36e5450c0eb00d8b231d06f1ad8e543f72b142e8
  Author: Anup Patel <anup.patel@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M docs/system/riscv/virt.rst
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  hw/riscv: virt: Add optional ACLINT support to virt machine

We extend virt machine to emulate ACLINT devices only when "aclint=on"
parameter is passed along with machine name in QEMU command-line.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210831110603.338681-5-anup.patel@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7f7019cefe39ef919b0de7db07948ad695b7d959
      
https://github.com/qemu/qemu/commit/7f7019cefe39ef919b0de7db07948ad695b7d959
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/dma/sifive_pdma.c

  Log Message:
  -----------
  hw/dma: sifive_pdma: reset Next* registers when Control.claim is set

Setting Control.claim clears all of the chanel's Next registers.
This is effective only when Control.claim is set from 0 to 1.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-2-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2e30a698d678d2f42f0bf9d65144f42a4dcbb18f
      
https://github.com/qemu/qemu/commit/2e30a698d678d2f42f0bf9d65144f42a4dcbb18f
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/dma/sifive_pdma.c

  Log Message:
  -----------
  hw/dma: sifive_pdma: claim bit must be set before DMA transactions

Real PDMA must have Control.claim bit to be set before
Control.run bit is set to start any DMA transactions.
Otherwise nothing will be transferred.

The following result is PDMA tested in U-Boot on Unmatched board:

=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
                                              (Channel 0 is not claimed)
=> mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x2                      <= NextBytes = 2
=> mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321              <= Fill test data to dst
=> mw.l 0x84001000 0x12345678              <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000000 55000000 00000002 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> mw.l 0x3000000 0x3                      <= Set channel 0 run and claim bits
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000001 66000000 00000000 00000000    .......f........
03000010: 00000000 00000000 00000000 00000000    ................
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 49cd347f4cbaf91ef1f2b2aefad074c2e70eeef1
      
https://github.com/qemu/qemu/commit/49cd347f4cbaf91ef1f2b2aefad074c2e70eeef1
  Author: Green Wan <green.wan@sifive.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/dma/sifive_pdma.c

  Log Message:
  -----------
  hw/dma: sifive_pdma: allow non-multiple transaction size transactions

Real PDMA is able to deal with non-multiple transaction size transactions.

The following result is PDMA tested in U-Boot on Unmatched board:

=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
=> mw.l 0x3000000 0x1                      <= Claim channel 0
=> mw.l 0x3000004 0x11000000               <= wsize = rsize = 1 (2^1 = 2 bytes)
=> mw.q 0x3000008 0x3                      <= NextBytes = 3
=> mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321              <= Fill test data to dst
=> mw.l 0x84001000 0x12345678              <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000001 11000000 00000003 00000000    ................
03000010: 84000000 00000000 84001000 00000000    ................
=> mw.l 0x3000000 0x3                      <= Set channel 0 run and claim bits
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 40000001 11000000 00000003 00000000    ...@............
03000010: 84000000 00000000 84001000 00000000    ................
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87345678                               xV4.
84001000: 12345678                               xV4.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20210912130553.179501-4-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a951bb01654ef77ee259f4aa6294ee055af40b10
      
https://github.com/qemu/qemu/commit/a951bb01654ef77ee259f4aa6294ee055af40b10
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/dma/sifive_pdma.c

  Log Message:
  -----------
  hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer

Real PDMA doesn't set Control.error if there are 0 bytes to be
transferred. The DMA transfer is still success.

The following result is PDMA tested in U-Boot on Unmatched board:

=> mw.l 0x3000000 0x0                      <= Disclaim channel 0
=> mw.l 0x3000000 0x1                      <= Claim channel 0
=> mw.l 0x3000004 0x55000000               <= wsize = rsize = 5 (2^5 = 32 bytes)
=> mw.q 0x3000008 0x0                      <= NextBytes = 0
=> mw.q 0x3000010 0x84000000               <= NextDestination = 0x84000000
=> mw.q 0x3000018 0x84001000               <= NextSource = 0x84001000
=> mw.l 0x84000000 0x87654321              <= Fill test data to dst
=> mw.l 0x84001000 0x12345678              <= Fill test data to src
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 00000001 55000000 00000000 00000000    .......U........
03000010: 84000000 00000000 84001000 00000000    ................
=> mw.l 0x3000000 0x3                      <= Set channel 0 run and claim bits
=> md.l 0x3000000 8                        <= Dump PDMA status
03000000: 40000001 55000000 00000000 00000000    ...@...U........
03000010: 84000000 00000000 84001000 00000000    ................
=> md.l 0x84000000 1; md.l 0x84001000 1    <= Dump src/dst memory contents
84000000: 87654321                               !Ce.
84001000: 12345678                               xV4.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Tested-by: Max Hsu <max.hsu@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210912130553.179501-5-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 863dad816ecf6eca04495052d20164ac1d498b65
      
https://github.com/qemu/qemu/commit/863dad816ecf6eca04495052d20164ac1d498b65
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M docs/system/riscv/sifive_u.rst

  Log Message:
  -----------
  docs/system/riscv: sifive_u: Update U-Boot instructions

In U-Boot v2021.07 release, there were 2 major changes for the
SiFive Unleashed board support:

- Board config name was changed from sifive_fu540_defconfig to
  sifive_unleashed_defconfig
- The generic binman tool was used to generate the FIT image
  (combination of U-Boot proper, DTB and OpenSBI firmware)

which make the existing U-Boot instructions out of date.

Update the doc with latest instructions.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911153431.10362-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4eac030af7033eaa796d89c85af4998f8a7be646
      
https://github.com/qemu/qemu/commit/4eac030af7033eaa796d89c85af4998f8a7be646
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Backup/restore mstatus.SD bit when virtual register swapped

When virtual registers are swapped, mstatus.SD bit should also be
backed up/restored. Otherwise, mstatus.SD bit will be incorrectly kept
across the world switches.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Vincent Chen <vincent.chen@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210914013717.881430-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9f58ca235121414d3a1e24f6b7aa238afb34d3dd
      
https://github.com/qemu/qemu/commit/9f58ca235121414d3a1e24f6b7aa238afb34d3dd
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: csr: Rename HCOUNTEREN_CY and friends

The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: c14620db9b66de88bb4fef1d0cfc283bb3d53f85
      
https://github.com/qemu/qemu/commit/c14620db9b66de88bb4fef1d0cfc283bb3d53f85
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-09-17 (Fri, 17 Sep 2021)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: opentitan: Correct the USB Dev address

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
d6cb4dfe75a2f536f217d7075b750ece3acb1535.1631767043.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 735c20bd4925f271684e91d8d57b7314a13a3c82
      
https://github.com/qemu/qemu/commit/735c20bd4925f271684e91d8d57b7314a13a3c82
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-20 (Mon, 20 Sep 2021)

  Changed paths:
    M docs/system/riscv/sifive_u.rst
    M docs/system/riscv/virt.rst
    M hw/dma/sifive_pdma.c
    M hw/intc/Kconfig
    M hw/intc/ibex_plic.c
    M hw/intc/meson.build
    A hw/intc/riscv_aclint.c
    R hw/intc/sifive_clint.c
    M hw/intc/sifive_plic.c
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M hw/timer/Kconfig
    M hw/timer/ibex_timer.c
    M hw/timer/meson.build
    A hw/timer/sifive_pwm.c
    M hw/timer/trace-events
    M include/hw/intc/ibex_plic.h
    A include/hw/intc/riscv_aclint.h
    R include/hw/intc/sifive_clint.h
    M include/hw/intc/sifive_plic.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/virt.h
    M include/hw/timer/ibex_timer.h
    A include/hw/timer/sifive_pwm.h
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210917' into staging

Second RISC-V PR for QEMU 6.2

 - ePMP CSR address updates
 - Convert internal interrupts to use QEMU GPIO lines
 - SiFive PWM support
 - Support for RISC-V ACLINT
 - SiFive PDMA fixes
 - Update to u-boot instructions for sifive_u
 - mstatus.SD bug fix for hypervisor extensions
 - OpenTitan fix for USB dev address

# gpg: Signature made Thu 16 Sep 2021 22:48:20 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210917: (21 commits)
  hw/riscv: opentitan: Correct the USB Dev address
  target/riscv: csr: Rename HCOUNTEREN_CY and friends
  target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
  docs/system/riscv: sifive_u: Update U-Boot instructions
  hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer
  hw/dma: sifive_pdma: allow non-multiple transaction size transactions
  hw/dma: sifive_pdma: claim bit must be set before DMA transactions
  hw/dma: sifive_pdma: reset Next* registers when Control.claim is set
  hw/riscv: virt: Add optional ACLINT support to virt machine
  hw/riscv: virt: Re-factor FDT generation
  hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
  hw/intc: Rename sifive_clint sources to riscv_aclint sources
  sifive_u: Connect the SiFive PWM device
  hw/timer: Add SiFive PWM support
  hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines
  hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines
  hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines
  hw/intc: sifive_clint: Use RISC-V CPU GPIO lines
  target/riscv: Expose interrupt pending bits as GPIO lines
  target/riscv: Fix satp write
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/294c3a851813...735c20bd4925