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[Qemu-commits] [qemu/qemu] 4e1168: accel/tcg: Add DisasContextBase argum

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 4e1168: accel/tcg: Add DisasContextBase argument to transl...
Date: Wed, 15 Sep 2021 05:28:17 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 4e116893c6079b51efdc9e226be3f1a530f47f5e
      
https://github.com/qemu/qemu/commit/4e116893c6079b51efdc9e226be3f1a530f47f5e
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M include/exec/translator.h
    M target/alpha/translate.c
    M target/arm/arm_ldst.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/hexagon/translate.c
    M target/hppa/translate.c
    M target/i386/tcg/translate.c
    M target/m68k/translate.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/translate.c
    M target/openrisc/translate.c
    M target/ppc/translate.c
    M target/riscv/translate.c
    M target/s390x/tcg/translate.c
    M target/sh4/translate.c
    M target/sparc/translate.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  accel/tcg: Add DisasContextBase argument to translator_ld*

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
[rth: Split out of a larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f025692c992c1ed6cc54ac2802cff14e9052c0d3
      
https://github.com/qemu/qemu/commit/f025692c992c1ed6cc54ac2802cff14e9052c0d3
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M include/exec/translate-all.h
    M include/exec/translator.h

  Log Message:
  -----------
  accel/tcg: Clear PAGE_WRITE before translation

translate_insn() implementations fetch instruction bytes piecemeal,
which can cause qemu-user to generate inconsistent translations if
another thread modifies them concurrently [1].

Fix by making pages containing translated instruction non-writable
right before loading instruction bytes from them.

[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fc88a52318c58e90b0ad0220c660d7bd4695bda0
      
https://github.com/qemu/qemu/commit/fc88a52318c58e90b0ad0220c660d7bd4695bda0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Split P_VEXW from P_REXW

We need to be able to represent VEX.W on a 32-bit host, where REX.W
will always be zero.  Fixes the encoding for VPSLLVQ and VPSRLVQ.

Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cf3fccba00c7e239f9ea8189a7c97f94c3df9b37
      
https://github.com/qemu/qemu/commit/cf3fccba00c7e239f9ea8189a7c97f94c3df9b37
  Author: Luc Michel <lmichel@kalray.eu>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M accel/tcg/tcg-accel-ops-rr.c

  Log Message:
  -----------
  accel/tcg: remove redundant TCG_KICK_PERIOD define

The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
Remove it from tcg-accel-ops-rr.c.

Signed-off-by: Luc Michel <lmichel@kalray.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 57d4941602b89fba1c4170692f110b168bc1695e
      
https://github.com/qemu/qemu/commit/57d4941602b89fba1c4170692f110b168bc1695e
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M include/tcg/tcg-op.h
    M target/hppa/translate.c

  Log Message:
  -----------
  tcg: Remove tcg_global_reg_new defines

Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
these tcg_global_reg_new_ macros are not used anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2fa169ba611162c055bd83831c64e8a16d355b94
      
https://github.com/qemu/qemu/commit/2fa169ba611162c055bd83831c64e8a16d355b94
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN

If __APPLE__, ensure that _CALL_DARWIN is set, then remove
our local TCG_TARGET_CALL_DARWIN.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d216898563a1d84f6147a13ecf396ae5bd252e68
      
https://github.com/qemu/qemu/commit/d216898563a1d84f6147a13ecf396ae5bd252e68
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF

Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
the ABI for ppc32.  Make a good guess based on other symbols.

Reported-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 421519d82cb19dda07ee1711df30c4e29bffe97e
      
https://github.com/qemu/qemu/commit/421519d82cb19dda07ee1711df30c4e29bffe97e
  Author: Jose R. Ziviani <jziviani@suse.de>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Fix tcg_out_vec_op function signature

Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
for arm is missing. It causes a build error on armv6 and armv7:

tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
   const TCGArg *args, const int *const_args)
  ~~~~~~~~~~~~~~^~~~
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
{aka 'const unsigned int[16]'}
   const TCGArg args[TCG_MAX_OP_ARGS],
  ~~~~~~~~~~~~~~^~~~

Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d2470cf0e9c0f99bf73beef63595298153ef91a7
      
https://github.com/qemu/qemu/commit/d2470cf0e9c0f99bf73beef63595298153ef91a7
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/avr/cpu.c

  Log Message:
  -----------
  target/avr: Remove pointless use of CONFIG_USER_ONLY definition

Commit f1c671f96cb ("target/avr: Introduce basic CPU class object")
added to target/avr/cpu.h:

  #ifdef CONFIG_USER_ONLY
  #error "AVR 8-bit does not support user mode"
  #endif

Remove the CONFIG_USER_ONLY definition introduced by mistake in
commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a
pointer in CPUClass").

Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Message-Id: <20210911165434.531552-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7ce088659846b7f27eb26afd31249eebf529f2b3
      
https://github.com/qemu/qemu/commit/7ce088659846b7f27eb26afd31249eebf529f2b3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/i386/cpu.h

  Log Message:
  -----------
  target/i386: Restrict sysemu-only fpu_helper helpers

Restrict some sysemu-only fpu_helper helpers (see commit
83a3d9c7402: "i386: separate fpu_helper sysemu-only parts").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 30ca39244bccc93d90a9a763e7e3d115ba089c13
      
https://github.com/qemu/qemu/commit/30ca39244bccc93d90a9a763e7e3d115ba089c13
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/i386/tcg/seg_helper.c

  Log Message:
  -----------
  target/i386: Simplify TARGET_X86_64 #ifdef'ry

Merge two TARGET_X86_64 consecutive blocks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b40db05daa35d2d0186a47463338ddc8730d0c5c
      
https://github.com/qemu/qemu/commit/b40db05daa35d2d0186a47463338ddc8730d0c5c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/xtensa/cpu.h

  Log Message:
  -----------
  target/xtensa: Restrict do_transaction_failed() to sysemu

The do_transaction_failed() is restricted to system emulation since
commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 120964219d7cb6c72ae629a7a71ff9c45a9c8a9b
      
https://github.com/qemu/qemu/commit/120964219d7cb6c72ae629a7a71ff9c45a9c8a9b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M include/hw/core/tcg-cpu-ops.h
    M target/i386/tcg/tcg-cpu.c

  Log Message:
  -----------
  accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt

do_interrupt() is sysemu specific. However due to some X86
specific hack, it is also used in user-mode emulation, which
is why it couldn't be restricted to CONFIG_SOFTMMU (see the
comment around added in commit 78271684719: "cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Keep the hack but rename the handler as fake_user_interrupt()
and restrict do_interrupt() to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9354e6947adcd0b74b9c7de875ab8635a4e7e947
      
https://github.com/qemu/qemu/commit/9354e6947adcd0b74b9c7de875ab8635a4e7e947
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/alpha/cpu.c
    M target/alpha/cpu.h
    M target/alpha/helper.c

  Log Message:
  -----------
  target/alpha: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-7-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 083afd18a97d402d55848e00b7f7a650dc92fed0
      
https://github.com/qemu/qemu/commit/083afd18a97d402d55848e00b7f7a650dc92fed0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-8-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 413f858d39f7565b265e40ca6cd8918e73d0e9ce
      
https://github.com/qemu/qemu/commit/413f858d39f7565b265e40ca6cd8918e73d0e9ce
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/cris/cpu.c
    M target/cris/cpu.h
    M target/cris/helper.c

  Log Message:
  -----------
  target/cris: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 68fa1780e07cb0a649d7cbd5c753cedcfe2e46c4
      
https://github.com/qemu/qemu/commit/68fa1780e07cb0a649d7cbd5c753cedcfe2e46c4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/int_helper.c

  Log Message:
  -----------
  target/hppa: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 604664726f400ca3857a28d7169542596dd83dd0
      
https://github.com/qemu/qemu/commit/604664726f400ca3857a28d7169542596dd83dd0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/i386/tcg/helper-tcg.h
    M target/i386/tcg/seg_helper.c
    M target/i386/tcg/tcg-cpu.c

  Log Message:
  -----------
  target/i386: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0792e6c88d4af085f7b6adf5d573f018939becef
      
https://github.com/qemu/qemu/commit/0792e6c88d4af085f7b6adf5d573f018939becef
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/i386/tcg/seg_helper.c
    M target/i386/tcg/sysemu/seg_helper.c

  Log Message:
  -----------
  target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder

Following the logic of commit 30493a030ff ("i386: split seg_helper
into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
under sysemu/seg_helper.c.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Message-Id: <20210911165434.531552-12-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d5db810c551f7baac3ecad7a492dcbd9dc0e5c9c
      
https://github.com/qemu/qemu/commit/d5db810c551f7baac3ecad7a492dcbd9dc0e5c9c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/op_helper.c

  Log Message:
  -----------
  target/m68k: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eb3ef3136eb2a56026d7f1516082e14a0c98f152
      
https://github.com/qemu/qemu/commit/eb3ef3136eb2a56026d7f1516082e14a0c98f152
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/microblaze/helper.c

  Log Message:
  -----------
  target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-14-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6eb66e086a5b03ed197ad8db8b637ab304bbc4d9
      
https://github.com/qemu/qemu/commit/6eb66e086a5b03ed197ad8db8b637ab304bbc4d9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/mips/cpu.c
    M target/mips/tcg/exception.c
    M target/mips/tcg/sysemu/tlb_helper.c
    M target/mips/tcg/tcg-internal.h
    M target/mips/tcg/user/tlb_helper.c

  Log Message:
  -----------
  target/mips: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-15-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dabfe1332eb3dd20affef4c696f716e0930bba7e
      
https://github.com/qemu/qemu/commit/dabfe1332eb3dd20affef4c696f716e0930bba7e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/nios2/cpu.c

  Log Message:
  -----------
  target/nios2: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-16-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 250ae6dfc726fa99fd068e4c135c8017cbd88af0
      
https://github.com/qemu/qemu/commit/250ae6dfc726fa99fd068e4c135c8017cbd88af0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/meson.build

  Log Message:
  -----------
  target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-17-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f725245c527c96e4333e9bf3ed38635ee8c9fcbc
      
https://github.com/qemu/qemu/commit/f725245c527c96e4333e9bf3ed38635ee8c9fcbc
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  target/ppc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210911165434.531552-18-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 17b3c353e6aa4627d2418714cf2431853da45e31
      
https://github.com/qemu/qemu/commit/17b3c353e6aa4627d2418714cf2431853da45e31
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210911165434.531552-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 73166ca348a9590c7e089e617851a91ffb8bcb23
      
https://github.com/qemu/qemu/commit/73166ca348a9590c7e089e617851a91ffb8bcb23
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/sh4/cpu.c
    M target/sh4/cpu.h
    M target/sh4/helper.c

  Log Message:
  -----------
  target/sh4: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-20-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 798ac8b5e9f7a43fd8a0b1469bf7df27a9a04dd4
      
https://github.com/qemu/qemu/commit/798ac8b5e9f7a43fd8a0b1469bf7df27a9a04dd4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/sparc/cpu.c

  Log Message:
  -----------
  target/sparc: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-21-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 65c575b61e000ef862f899643ed0a818794881b9
      
https://github.com/qemu/qemu/commit/65c575b61e000ef862f899643ed0a818794881b9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/rx/cpu.c
    M target/rx/cpu.h
    M target/rx/helper.c

  Log Message:
  -----------
  target/rx: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-22-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f364a7f9685732ba236ed268252dcf24926ff26a
      
https://github.com/qemu/qemu/commit/f364a7f9685732ba236ed268252dcf24926ff26a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/exc_helper.c

  Log Message:
  -----------
  target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu

Restrict cpu_exec_interrupt() and its callees to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-23-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 77c0fc4e55cd7edf2f109fd5dca2395a1c91e9e7
      
https://github.com/qemu/qemu/commit/77c0fc4e55cd7edf2f109fd5dca2395a1c91e9e7
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M include/hw/core/tcg-cpu-ops.h

  Log Message:
  -----------
  accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu

All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code.
Move its declaration to restrict it to system emulation.
Extend the code guarded.
Restrict the static inlined need_replay_interrupt() method to
avoid a "defined but not used" warning.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-24-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 76d0042bb2a7601e7a343fd2ff02902658f8a97a
      
https://github.com/qemu/qemu/commit/76d0042bb2a7601e7a343fd2ff02902658f8a97a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M bsd-user/i386/target_arch_cpu.c
    M bsd-user/x86_64/target_arch_cpu.c
    M linux-user/main.c
    M target/i386/cpu.h

  Log Message:
  -----------
  user: Remove cpu_get_pic_interrupt() stubs

cpu_get_pic_interrupt() is now unreachable from user-mode,
delete the unnecessary stubs.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-25-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: db17d2cdb1a10e6fa8aa02de167546c17c893c3c
      
https://github.com/qemu/qemu/commit/db17d2cdb1a10e6fa8aa02de167546c17c893c3c
  Author: Ilya Leoshkevich <iii@linux.ibm.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M accel/tcg/user-exec.c

  Log Message:
  -----------
  accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts

x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
under s390x qemu-linux user, cpu_signal_handler() does not recognize
this as a write and does not restore PAGE_WRITE cleared by
tb_page_add(), incorrectly forwarding the signal to the guest code.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210803221606.150103-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e0e1ad61f6ed8ac90b0cd5bed2de464035d9a2e4
      
https://github.com/qemu/qemu/commit/e0e1ad61f6ed8ac90b0cd5bed2de464035d9a2e4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.h

  Log Message:
  -----------
  tcg/arm: Remove fallback definition of __ARM_ARCH

GCC since 4.8 provides the definition and we now require 7.5.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 326b9669b0ae118e8275af536ee9503cd93f8525
      
https://github.com/qemu/qemu/commit/326b9669b0ae118e8275af536ee9503cd93f8525
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}

Some of the functions specified _reg, some _imm, and some
left it blank.  Make it clearer to which we are referring.

Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when
we do not actually require BX semantics.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4ae82ca7eb3913a575646dacdc0d151723e54d1d
      
https://github.com/qemu/qemu/commit/4ae82ca7eb3913a575646dacdc0d151723e54d1d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.h

  Log Message:
  -----------
  tcg/arm: Simplify use_armv5t_instructions

According to the Arm ARM DDI 0406C, section A1.3, the valid variants
are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb.
Therefore simplify the test from preprocessor ifdefs to base
architecture revision.  Retain the "t" in the name to minimize churn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b87c1add03232889d5a464ef29f1d8f1ad2ebe9b
      
https://github.com/qemu/qemu/commit/b87c1add03232889d5a464ef29f1d8f1ad2ebe9b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call

ARMv4T has BX as its only interworking instruction.  In order
to support testing of different architecture revisions with a
qemu binary that may have been built for, say ARMv6T2, fill in
the blank required to make calls to helpers in thumb mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 31d160adc9d2a13db582096bb844038732c1fbea
      
https://github.com/qemu/qemu/commit/31d160adc9d2a13db582096bb844038732c1fbea
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Split out tcg_out_ldstm

Expand these hard-coded instructions symbolically.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 90606715dc1b5de5c432afd0deac8b5c6d36eeda
      
https://github.com/qemu/qemu/commit/90606715dc1b5de5c432afd0deac8b5c6d36eeda
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Simplify usage of encode_imm

We have already computed the rotated value of the imm8
portion of the complete imm12 encoding.  No sense leaving
the combination of rot + rotation to the caller.

Create an encode_imm12_nofail helper that performs an assert.

This removes the final use of the local "rotl" function,
which duplicated our generic "rol32" function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5f726ebce1637c7acd626fa1ec710ca5fb5469dd
      
https://github.com/qemu/qemu/commit/5f726ebce1637c7acd626fa1ec710ca5fb5469dd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Drop inline markers

Let the compiler decide about inlining.
Remove tcg_out_nop as unused.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1446600f7f6e8ecdcaa5d33133b2fa169cd49738
      
https://github.com/qemu/qemu/commit/1446600f7f6e8ecdcaa5d33133b2fa169cd49738
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Give enum arm_cond_code_e a typedef and use it

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 142fb62fd0640062c505d46727bafeb38c295bfc
      
https://github.com/qemu/qemu/commit/142fb62fd0640062c505d46727bafeb38c295bfc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: More use of the ARMInsn enum

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e028eada62dbfcba134ac5afdefc3aa343ae202f
      
https://github.com/qemu/qemu/commit/e028eada62dbfcba134ac5afdefc3aa343ae202f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: More use of the TCGReg enum

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0b6206b9c6825619cd721085fe082d7a0abc9af4
      
https://github.com/qemu/qemu/commit/0b6206b9c6825619cd721085fe082d7a0abc9af4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-15 (Wed, 15 Sep 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/tcg-accel-ops-rr.c
    M accel/tcg/translate-all.c
    M accel/tcg/translator.c
    M accel/tcg/user-exec.c
    M bsd-user/i386/target_arch_cpu.c
    M bsd-user/x86_64/target_arch_cpu.c
    M include/exec/translate-all.h
    M include/exec/translator.h
    M include/hw/core/tcg-cpu-ops.h
    M include/tcg/tcg-op.h
    M linux-user/main.c
    M target/alpha/cpu.c
    M target/alpha/cpu.h
    M target/alpha/helper.c
    M target/alpha/translate.c
    M target/arm/arm_ldst.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu_tcg.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/avr/cpu.c
    M target/cris/cpu.c
    M target/cris/cpu.h
    M target/cris/helper.c
    M target/hexagon/translate.c
    M target/hppa/cpu.c
    M target/hppa/cpu.h
    M target/hppa/int_helper.c
    M target/hppa/translate.c
    M target/i386/cpu.h
    M target/i386/tcg/helper-tcg.h
    M target/i386/tcg/seg_helper.c
    M target/i386/tcg/sysemu/seg_helper.c
    M target/i386/tcg/tcg-cpu.c
    M target/i386/tcg/translate.c
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/op_helper.c
    M target/m68k/translate.c
    M target/microblaze/cpu.c
    M target/microblaze/cpu.h
    M target/microblaze/helper.c
    M target/mips/cpu.c
    M target/mips/tcg/exception.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/nanomips_translate.c.inc
    M target/mips/tcg/sysemu/tlb_helper.c
    M target/mips/tcg/tcg-internal.h
    M target/mips/tcg/translate.c
    M target/mips/tcg/user/tlb_helper.c
    M target/nios2/cpu.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/meson.build
    M target/openrisc/translate.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c
    M target/ppc/translate.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/translate.c
    M target/rx/cpu.c
    M target/rx/cpu.h
    M target/rx/helper.c
    M target/s390x/tcg/translate.c
    M target/sh4/cpu.c
    M target/sh4/cpu.h
    M target/sh4/helper.c
    M target/sh4/translate.c
    M target/sparc/cpu.c
    M target/sparc/translate.c
    M target/xtensa/cpu.c
    M target/xtensa/cpu.h
    M target/xtensa/exc_helper.c
    M target/xtensa/translate.c
    M tcg/arm/tcg-target.c.inc
    M tcg/arm/tcg-target.h
    M tcg/i386/tcg-target.c.inc
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210914-4' 
into staging

Fix translation race condition for user-only.
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
Fix tcg/arm tcg_out_vec_op signature.
Fix tcg/ppc (32bit) build with clang.
Remove dupluate TCG_KICK_PERIOD definition.
Remove unused tcg_global_reg_new.
Restrict cpu_exec_interrupt and its callees to sysemu.
Cleanups for tcg/arm.

# gpg: Signature made Tue 14 Sep 2021 20:28:35 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210914-4: (43 commits)
  tcg/arm: More use of the TCGReg enum
  tcg/arm: More use of the ARMInsn enum
  tcg/arm: Give enum arm_cond_code_e a typedef and use it
  tcg/arm: Drop inline markers
  tcg/arm: Simplify usage of encode_imm
  tcg/arm: Split out tcg_out_ldstm
  tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
  tcg/arm: Simplify use_armv5t_instructions
  tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
  tcg/arm: Remove fallback definition of __ARM_ARCH
  accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
  user: Remove cpu_get_pic_interrupt() stubs
  accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
  target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
  target/rx: Restrict cpu_exec_interrupt() handler to sysemu
  target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
  target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
  target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
  target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
  target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/831aaf24967a...0b6206b9c682
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