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[Qemu-commits] [qemu/qemu] 2d8e01: accel/tcg: Add DisasContextBase argum
From: |
Peter Maydell |
Subject: |
[Qemu-commits] [qemu/qemu] 2d8e01: accel/tcg: Add DisasContextBase argument to transl... |
Date: |
Tue, 14 Sep 2021 09:10:59 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 2d8e01274358addfe6e8e10bb125f9a649ab59b0
https://github.com/qemu/qemu/commit/2d8e01274358addfe6e8e10bb125f9a649ab59b0
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M include/exec/translator.h
M target/alpha/translate.c
M target/arm/arm_ldst.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/hexagon/translate.c
M target/hppa/translate.c
M target/i386/tcg/translate.c
M target/m68k/translate.c
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/mips16e_translate.c.inc
M target/mips/tcg/nanomips_translate.c.inc
M target/mips/tcg/translate.c
M target/openrisc/translate.c
M target/ppc/translate.c
M target/riscv/translate.c
M target/s390x/tcg/translate.c
M target/sh4/translate.c
M target/sparc/translate.c
M target/xtensa/translate.c
Log Message:
-----------
accel/tcg: Add DisasContextBase argument to translator_ld*
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
[rth: Split out of a larger patch.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ccd635315db606b95eda1fea6b21a564cb83933d
https://github.com/qemu/qemu/commit/ccd635315db606b95eda1fea6b21a564cb83933d
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M include/exec/translate-all.h
M include/exec/translator.h
Log Message:
-----------
accel/tcg: Clear PAGE_WRITE before translation
translate_insn() implementations fetch instruction bytes piecemeal,
which can cause qemu-user to generate inconsistent translations if
another thread modifies them concurrently [1].
Fix by making pages containing translated instruction non-writable
right before loading instruction bytes from them.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00644.html
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20210805204835.158918-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: eb2e292e3e7a97e0c0a090f4b31b221b3865ab2c
https://github.com/qemu/qemu/commit/eb2e292e3e7a97e0c0a090f4b31b221b3865ab2c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Split P_VEXW from P_REXW
We need to be able to represent VEX.W on a 32-bit host, where REX.W
will always be zero. Fixes the encoding for VPSLLVQ and VPSRLVQ.
Fixes: a2ce146a068 ("tcg/i386: Support vector variable shift opcodes")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/385
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d8b964d15fd54f1e09aeaf4512120aa322b7c4cf
https://github.com/qemu/qemu/commit/d8b964d15fd54f1e09aeaf4512120aa322b7c4cf
Author: Luc Michel <lmichel@kalray.eu>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/tcg-accel-ops-rr.c
Log Message:
-----------
accel/tcg: remove redundant TCG_KICK_PERIOD define
The TCG_KICK_PERIOD macro is already defined in tcg-accel-ops-rr.h.
Remove it from tcg-accel-ops-rr.c.
Signed-off-by: Luc Michel <lmichel@kalray.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210811141229.12470-1-lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0e05752997503e2cb06e86420e48d94a6a7a535c
https://github.com/qemu/qemu/commit/0e05752997503e2cb06e86420e48d94a6a7a535c
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M include/tcg/tcg-op.h
M target/hppa/translate.c
Log Message:
-----------
tcg: Remove tcg_global_reg_new defines
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"),
these tcg_global_reg_new_ macros are not used anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8323604092c905e7fd7389e19989e0adc97e13d8
https://github.com/qemu/qemu/commit/8323604092c905e7fd7389e19989e0adc97e13d8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
If __APPLE__, ensure that _CALL_DARWIN is set, then remove
our local TCG_TARGET_CALL_DARWIN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 101e77c31d3e46fc64472d7bd4922711361b6c11
https://github.com/qemu/qemu/commit/101e77c31d3e46fc64472d7bd4922711361b6c11
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
Clang only sets _CALL_ELF for ppc64, and nothing at all to specify
the ABI for ppc32. Make a good guess based on other symbols.
Reported-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 53da366b5ddf504d5531a1b2b95784647c283f34
https://github.com/qemu/qemu/commit/53da366b5ddf504d5531a1b2b95784647c283f34
Author: Jose R. Ziviani <jziviani@suse.de>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Fix tcg_out_vec_op function signature
Commit 5e8892db93 fixed several function signatures but tcg_out_vec_op
for arm is missing. It causes a build error on armv6 and armv7:
tcg-target.c.inc:2718:42: error: argument 5 of type 'const TCGArg *'
{aka 'const unsigned int *'} declared as a pointer [-Werror=array-parameter=]
const TCGArg *args, const int *const_args)
~~~~~~~~~~~~~~^~~~
../tcg/tcg.c:120:41: note: previously declared as an array 'const TCGArg[16]'
{aka 'const unsigned int[16]'}
const TCGArg args[TCG_MAX_OP_ARGS],
~~~~~~~~~~~~~~^~~~
Signed-off-by: Jose R. Ziviani <jziviani@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210908185338.7927-1-jziviani@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9e8faa93f83a76f10850fb225dbc3505dafd6f3e
https://github.com/qemu/qemu/commit/9e8faa93f83a76f10850fb225dbc3505dafd6f3e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/avr/cpu.c
Log Message:
-----------
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
Commit f1c671f96cb ("target/avr: Introduce basic CPU class object")
added to target/avr/cpu.h:
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
#endif
Remove the CONFIG_USER_ONLY definition introduced by mistake in
commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a
pointer in CPUClass").
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Message-Id: <20210911165434.531552-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ce67d5114a3ba0f1641c1d0c3ee4d44377cb896c
https://github.com/qemu/qemu/commit/ce67d5114a3ba0f1641c1d0c3ee4d44377cb896c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: Restrict sysemu-only fpu_helper helpers
Restrict some sysemu-only fpu_helper helpers (see commit
83a3d9c7402: "i386: separate fpu_helper sysemu-only parts").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1c461570468ca4699c0ab1b52d01af78d4805a8e
https://github.com/qemu/qemu/commit/1c461570468ca4699c0ab1b52d01af78d4805a8e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/i386/tcg/seg_helper.c
Log Message:
-----------
target/i386: Simplify TARGET_X86_64 #ifdef'ry
Merge two TARGET_X86_64 consecutive blocks.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 219123e3007ad74a317e20b738ad5d63b6d97cf5
https://github.com/qemu/qemu/commit/219123e3007ad74a317e20b738ad5d63b6d97cf5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/xtensa/cpu.h
Log Message:
-----------
target/xtensa: Restrict do_transaction_failed() to sysemu
The do_transaction_failed() is restricted to system emulation since
commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 80d94d0076c4c14b9ad5e49648fb95a1bd8e7497
https://github.com/qemu/qemu/commit/80d94d0076c4c14b9ad5e49648fb95a1bd8e7497
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/tcg-cpu-ops.h
M target/i386/tcg/tcg-cpu.c
Log Message:
-----------
accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
do_interrupt() is sysemu specific. However due to some X86
specific hack, it is also used in user-mode emulation, which
is why it couldn't be restricted to CONFIG_SOFTMMU (see the
comment around added in commit 78271684719: "cpu: tcg_ops:
move to tcg-cpu-ops.h, keep a pointer in CPUClass").
Keep the hack but rename the handler as fake_user_interrupt()
and restrict do_interrupt() to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b3ac6d731cd81619364d1e5ecbb384bca2969772
https://github.com/qemu/qemu/commit/b3ac6d731cd81619364d1e5ecbb384bca2969772
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/alpha/helper.c
Log Message:
-----------
target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-7-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fb3242a5097e49e84f2cecaf9b47d19cece49f85
https://github.com/qemu/qemu/commit/fb3242a5097e49e84f2cecaf9b47d19cece49f85
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-8-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: eaeeed49233dfbfbed7cc64ab71395909e191324
https://github.com/qemu/qemu/commit/eaeeed49233dfbfbed7cc64ab71395909e191324
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/cris/cpu.c
M target/cris/cpu.h
M target/cris/helper.c
Log Message:
-----------
target/cris: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a431af6f4cb1a8e87fe2a24984a29595443bb400
https://github.com/qemu/qemu/commit/a431af6f4cb1a8e87fe2a24984a29595443bb400
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/int_helper.c
Log Message:
-----------
target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fa548d5fcfa3b40746e7f385c60b34e7a766f8c0
https://github.com/qemu/qemu/commit/fa548d5fcfa3b40746e7f385c60b34e7a766f8c0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/i386/tcg/helper-tcg.h
M target/i386/tcg/seg_helper.c
M target/i386/tcg/tcg-cpu.c
Log Message:
-----------
target/i386: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 17415c4bbcb6ca18a66da7be74d5422733b0f4d2
https://github.com/qemu/qemu/commit/17415c4bbcb6ca18a66da7be74d5422733b0f4d2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/seg_helper.c
Log Message:
-----------
target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
Following the logic of commit 30493a030ff ("i386: split seg_helper
into user-only and sysemu parts"), move x86_cpu_exec_interrupt()
under sysemu/seg_helper.c.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Message-Id: <20210911165434.531552-12-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 078b78149249284683ee5653a7bbc1d7ca3a212a
https://github.com/qemu/qemu/commit/078b78149249284683ee5653a7bbc1d7ca3a212a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/m68k/op_helper.c
Log Message:
-----------
target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ab400afd0977013a18584825ac388f9faf680280
https://github.com/qemu/qemu/commit/ab400afd0977013a18584825ac388f9faf680280
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/helper.c
Log Message:
-----------
target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-14-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 10bc79aa39fe89a2fb088188c6f30d9bf39d324f
https://github.com/qemu/qemu/commit/10bc79aa39fe89a2fb088188c6f30d9bf39d324f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/tcg/exception.c
M target/mips/tcg/sysemu/tlb_helper.c
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/user/tlb_helper.c
Log Message:
-----------
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-15-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e9466467e19f12749d7352352225212732853669
https://github.com/qemu/qemu/commit/e9466467e19f12749d7352352225212732853669
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/nios2/cpu.c
Log Message:
-----------
target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-16-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6914281d45573b03f07bf45788a4f79c5ede10e2
https://github.com/qemu/qemu/commit/6914281d45573b03f07bf45788a4f79c5ede10e2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/interrupt.c
M target/openrisc/meson.build
Log Message:
-----------
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-17-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 35551dec49f65db44ddce5d2f073ebf962d5d9c7
https://github.com/qemu/qemu/commit/35551dec49f65db44ddce5d2f073ebf962d5d9c7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210911165434.531552-18-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3ca265c113e92d22951067b32836ac4a3759c06d
https://github.com/qemu/qemu/commit/3ca265c113e92d22951067b32836ac4a3759c06d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210911165434.531552-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 40c1af0d07c00b05a374a758f568468bcc8bec85
https://github.com/qemu/qemu/commit/40c1af0d07c00b05a374a758f568468bcc8bec85
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/helper.c
Log Message:
-----------
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-20-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 91adcc217327bc8dfcc69fac73cbfcc03499a4de
https://github.com/qemu/qemu/commit/91adcc217327bc8dfcc69fac73cbfcc03499a4de
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-21-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3a7bb7acb88f52a8cda816770e7824743c2fcce9
https://github.com/qemu/qemu/commit/3a7bb7acb88f52a8cda816770e7824743c2fcce9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/rx/cpu.c
M target/rx/cpu.h
M target/rx/helper.c
Log Message:
-----------
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-22-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 026e4c456c8b79df4aed6df8c52196933ea05899
https://github.com/qemu/qemu/commit/026e4c456c8b79df4aed6df8c52196933ea05899
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/exc_helper.c
Log Message:
-----------
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
Restrict cpu_exec_interrupt() and its callees to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-23-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3d68358b65b67acc4d2fddef84c02b23b2d7ecbc
https://github.com/qemu/qemu/commit/3d68358b65b67acc4d2fddef84c02b23b2d7ecbc
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/tcg-cpu-ops.h
Log Message:
-----------
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
All targets call TCGCPUOps::cpu_exec_interrupt() from sysemu code.
Move its declaration to restrict it to system emulation.
Extend the code guarded.
Restrict the static inlined need_replay_interrupt() method to
avoid a "defined but not used" warning.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-24-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f3a133640b8d71ef8aaf38b79e616f93af9eb30f
https://github.com/qemu/qemu/commit/f3a133640b8d71ef8aaf38b79e616f93af9eb30f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M bsd-user/i386/target_arch_cpu.c
M bsd-user/x86_64/target_arch_cpu.c
M linux-user/main.c
M target/i386/cpu.h
Log Message:
-----------
user: Remove cpu_get_pic_interrupt() stubs
cpu_get_pic_interrupt() is now unreachable from user-mode,
delete the unnecessary stubs.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210911165434.531552-25-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0237ee05a61a8f69fa4c5099df75d2b664badee0
https://github.com/qemu/qemu/commit/0237ee05a61a8f69fa4c5099df75d2b664badee0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M bsd-user/qemu.h
M linux-user/qemu.h
Log Message:
-----------
user: Mark cpu_loop() with noreturn attribute
cpu_loop() never exits, so mark it with QEMU_NORETURN.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-By: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210905000429.1097336-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: af85fdb81d966519bad14e7e90720e0ddcc607a6
https://github.com/qemu/qemu/commit/af85fdb81d966519bad14e7e90720e0ddcc607a6
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/user-exec.c
Log Message:
-----------
accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
x86_64 dotnet/runtime uses cmpxchg for code patching. When running it
under s390x qemu-linux user, cpu_signal_handler() does not recognize
this as a write and does not restore PAGE_WRITE cleared by
tb_page_add(), incorrectly forwarding the signal to the guest code.
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210803221606.150103-1-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6a0b2143fb29ca8e245cfc1f4d3f2118198c01f7
https://github.com/qemu/qemu/commit/6a0b2143fb29ca8e245cfc1f4d3f2118198c01f7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Remove fallback definition of __ARM_ARCH
GCC since 4.8 provides the definition and we now require 7.5.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8cf276a473438ee9c9eebcc841a4f1f2191af7cc
https://github.com/qemu/qemu/commit/8cf276a473438ee9c9eebcc841a4f1f2191af7cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
Some of the functions specified _reg, some _imm, and some
left it blank. Make it clearer to which we are referring.
Split tcg_out_b_reg from tcg_out_bx_reg, to indicate when
we do not actually require BX semantics.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: de7c005dbce1250f7b114447de288b44b7e76c6e
https://github.com/qemu/qemu/commit/de7c005dbce1250f7b114447de288b44b7e76c6e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Simplify use_armv5t_instructions
According to the Arm ARM DDI 0406C, section A1.3, the valid variants
are ARMv5T, ARMv5TE, ARMv5TEJ -- there is no ARMv5 without Thumb.
Therefore simplify the test from preprocessor ifdefs to base
architecture revision. Retain the "t" in the name to minimize churn.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3f5a93c3d0e3277c2b5abe965e9eecffe9d663a6
https://github.com/qemu/qemu/commit/3f5a93c3d0e3277c2b5abe965e9eecffe9d663a6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
ARMv4T has BX as its only interworking instruction. In order
to support testing of different architecture revisions with a
qemu binary that may have been built for, say ARMv6T2, fill in
the blank required to make calls to helpers in thumb mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 68c6cd1f87ac9866bf06667c0e0707c4a7fa5f04
https://github.com/qemu/qemu/commit/68c6cd1f87ac9866bf06667c0e0707c4a7fa5f04
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Split out tcg_out_ldstm
Expand these hard-coded instructions symbolically.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8067a775acf543f564a79883ce25fa1fcf9c5552
https://github.com/qemu/qemu/commit/8067a775acf543f564a79883ce25fa1fcf9c5552
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Simplify usage of encode_imm
We have already computed the rotated value of the imm8
portion of the complete imm12 encoding. No sense leaving
the combination of rot + rotation to the caller.
Create an encode_imm12_nofail helper that performs an assert.
This removes the final use of the local "rotl" function,
which duplicated our generic "rol32" function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4ac08f183b733f719a5b3de9522a5f7fbefae87d
https://github.com/qemu/qemu/commit/4ac08f183b733f719a5b3de9522a5f7fbefae87d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Drop inline markers
Let the compiler decide about inlining.
Remove tcg_out_nop as unused.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b1a835946fc570af4fce7a85a3b5b96d6928254b
https://github.com/qemu/qemu/commit/b1a835946fc570af4fce7a85a3b5b96d6928254b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Give enum arm_cond_code_e a typedef and use it
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e901b0a57c281a6a4e0a965cee9e1cdf42a17eb0
https://github.com/qemu/qemu/commit/e901b0a57c281a6a4e0a965cee9e1cdf42a17eb0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: More use of the ARMInsn enum
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a5b759b6dca7daf87fa5007a7f5784bf22f3830f
https://github.com/qemu/qemu/commit/a5b759b6dca7daf87fa5007a7f5784bf22f3830f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: More use of the TCGReg enum
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b9036d7020e0d392bd3a1389c086f504c92e1e12
https://github.com/qemu/qemu/commit/b9036d7020e0d392bd3a1389c086f504c92e1e12
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-14 (Tue, 14 Sep 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops-rr.c
M accel/tcg/translate-all.c
M accel/tcg/translator.c
M accel/tcg/user-exec.c
M bsd-user/i386/target_arch_cpu.c
M bsd-user/qemu.h
M bsd-user/x86_64/target_arch_cpu.c
M include/exec/translate-all.h
M include/exec/translator.h
M include/hw/core/tcg-cpu-ops.h
M include/tcg/tcg-op.h
M linux-user/main.c
M linux-user/qemu.h
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/alpha/helper.c
M target/alpha/translate.c
M target/arm/arm_ldst.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu_tcg.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/cris/cpu.h
M target/cris/helper.c
M target/hexagon/translate.c
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/int_helper.c
M target/hppa/translate.c
M target/i386/cpu.h
M target/i386/tcg/helper-tcg.h
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/seg_helper.c
M target/i386/tcg/tcg-cpu.c
M target/i386/tcg/translate.c
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/m68k/op_helper.c
M target/m68k/translate.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/helper.c
M target/mips/cpu.c
M target/mips/tcg/exception.c
M target/mips/tcg/micromips_translate.c.inc
M target/mips/tcg/mips16e_translate.c.inc
M target/mips/tcg/nanomips_translate.c.inc
M target/mips/tcg/sysemu/tlb_helper.c
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/translate.c
M target/mips/tcg/user/tlb_helper.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/interrupt.c
M target/openrisc/meson.build
M target/openrisc/translate.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/translate.c
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
M target/rx/cpu.c
M target/rx/cpu.h
M target/rx/helper.c
M target/s390x/tcg/translate.c
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/translate.c
M target/sparc/cpu.c
M target/sparc/translate.c
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/exc_helper.c
M target/xtensa/translate.c
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210914' into
staging
Fix translation race condition for user-only.
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
Fix tcg/arm tcg_out_vec_op signature.
Fix tcg/ppc (32bit) build with clang.
Remove dupluate TCG_KICK_PERIOD definition.
Remove unused tcg_global_reg_new.
Restrict cpu_exec_interrupt and its callees to sysemu.
Cleanups for tcg/arm.
# gpg: Signature made Tue 14 Sep 2021 16:48:04 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210914: (44 commits)
tcg/arm: More use of the TCGReg enum
tcg/arm: More use of the ARMInsn enum
tcg/arm: Give enum arm_cond_code_e a typedef and use it
tcg/arm: Drop inline markers
tcg/arm: Simplify usage of encode_imm
tcg/arm: Split out tcg_out_ldstm
tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
tcg/arm: Simplify use_armv5t_instructions
tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
tcg/arm: Remove fallback definition of __ARM_ARCH
accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
user: Mark cpu_loop() with noreturn attribute
user: Remove cpu_get_pic_interrupt() stubs
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5f3a6834ab52...b9036d7020e0
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