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[Qemu-commits] [qemu/qemu] 7eca39: hw/intc: GICv3 ITS command queue fram
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 7eca39: hw/intc: GICv3 ITS command queue framework |
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Date: |
Mon, 13 Sep 2021 11:50:56 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 7eca39e071fc026f06eb3bbe9257d686f1d7e2e1
https://github.com/qemu/qemu/commit/7eca39e071fc026f06eb3bbe9257d686f1d7e2e1
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3_its.c
M hw/intc/gicv3_internal.h
Log Message:
-----------
hw/intc: GICv3 ITS command queue framework
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-4-shashi.mallela@linaro.org
[PMM: fixed format string nit]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2c898c7d4e94bcd1c3d575c26f46f7c81fea7925
https://github.com/qemu/qemu/commit/2c898c7d4e94bcd1c3d575c26f46f7c81fea7925
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3_its.c
M hw/intc/gicv3_internal.h
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc: GICv3 ITS Command processing
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 820be7c736b684dfb1d70a552b9065169253cdba
https://github.com/qemu/qemu/commit/820be7c736b684dfb1d70a552b9065169253cdba
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc: GICv3 ITS Feature enablement
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ed4fff7a962fd08cf9ff9b3b119e133f21ed4b38
https://github.com/qemu/qemu/commit/ed4fff7a962fd08cf9ff9b3b119e133f21ed4b38
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
M include/hw/intc/arm_gicv3_common.h
Log Message:
-----------
hw/intc: GICv3 redistributor ITS processing
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a5a414ee1235983e9531c94fd358aeef37c722d4
https://github.com/qemu/qemu/commit/a5a414ee1235983e9531c94fd358aeef37c722d4
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
A tests/data/acpi/virt/IORT
A tests/data/acpi/virt/IORT.memhp
A tests/data/acpi/virt/IORT.numamem
A tests/data/acpi/virt/IORT.pxb
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/data/acpi/virt: Add IORT files for ITS
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-8-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2cdc9d31e33036eb42c074fddef09e48b2d86042
https://github.com/qemu/qemu/commit/2cdc9d31e33036eb42c074fddef09e48b2d86042
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/arm/virt.c
M include/hw/arm/virt.h
M target/arm/kvm_arm.h
Log Message:
-----------
hw/arm/virt: add ITS support in virt GIC
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-9-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 669afcdd0ea44843f4a772c121fe0d099e6d75e2
https://github.com/qemu/qemu/commit/669afcdd0ea44843f4a772c121fe0d099e6d75e2
Author: Shashi Mallela <shashi.mallela@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M tests/data/acpi/virt/IORT
M tests/data/acpi/virt/IORT.memhp
M tests/data/acpi/virt/IORT.numamem
M tests/data/acpi/virt/IORT.pxb
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/data/acpi/virt: Update IORT files for ITS
Updated expected IORT files applicable with latest GICv3
ITS changes.
Full diff of new file disassembly:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021
*
* ACPI Data Table [IORT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "IORT" [IO Remapping Table]
[004h 0004 4] Table Length : 0000007C
[008h 0008 1] Revision : 00
[009h 0009 1] Checksum : 07
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] Node Count : 00000002
[028h 0040 4] Node Offset : 00000030
[02Ch 0044 4] Reserved : 00000000
[030h 0048 1] Type : 00
[031h 0049 2] Length : 0018
[033h 0051 1] Revision : 00
[034h 0052 4] Reserved : 00000000
[038h 0056 4] Mapping Count : 00000000
[03Ch 0060 4] Mapping Offset : 00000000
[040h 0064 4] ItsCount : 00000001
[044h 0068 4] Identifiers : 00000000
[048h 0072 1] Type : 02
[049h 0073 2] Length : 0034
[04Bh 0075 1] Revision : 00
[04Ch 0076 4] Reserved : 00000000
[050h 0080 4] Mapping Count : 00000001
[054h 0084 4] Mapping Offset : 00000020
[058h 0088 8] Memory Properties : [IORT Memory Access Properties]
[058h 0088 4] Cache Coherency : 00000001
[05Ch 0092 1] Hints (decoded below) : 00
Transient : 0
Write Allocate : 0
Read Allocate : 0
Override : 0
[05Dh 0093 2] Reserved : 0000
[05Fh 0095 1] Memory Flags (decoded below) : 03
Coherency : 1
Device Attribute : 1
[060h 0096 4] ATS Attribute : 00000000
[064h 0100 4] PCI Segment Number : 00000000
[068h 0104 1] Memory Size Limit : 00
[069h 0105 3] Reserved : 000000
[068h 0104 4] Input base : 00000000
[06Ch 0108 4] ID Count : 0000FFFF
[070h 0112 4] Output Base : 00000000
[074h 0116 4] Output Reference : 00000030
[078h 0120 4] Flags (decoded below) : 00000000
Single Mapping : 0
Raw Table Data: Length 124 (0x7C)
0000: 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20 // IORT|.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00 // ........0.......
0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00 // .........4......
0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03 // .... ...........
0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00 // ................
0070: 00 00 00 00 30 00 00 00 00 00 00 00 // ....0.......
Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-10-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a56c4ddc61fa03f1d3da80ae840b638033f3d578
https://github.com/qemu/qemu/commit/a56c4ddc61fa03f1d3da80ae840b638033f3d578
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/syndrome.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Take an exception if PSTATE.IL is set
In v8A, the PSTATE.IL bit is set for various kinds of illegal
exception return or mode-change attempts. We already set PSTATE.IL
(or its AArch32 equivalent CPSR.IL) in all those cases, but we
weren't implementing the part of the behaviour where attempting to
execute an instruction with PSTATE.IL takes an immediate exception
with an appropriate syndrome value.
Add a new TB flags bit tracking PSTATE.IL/CPSR.IL, and generate code
to take an exception instead of whatever the instruction would have
been.
PSTATE.IL and CPSR.IL change only on exception entry, attempted
exception exit, and various AArch32 mode changes via cpsr_write().
These places generally already rebuild the hflags, so the only place
we need an extra rebuild_hflags call is in the illegal-return
codepath of the AArch64 exception_return helper.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210821195958.41312-2-richard.henderson@linaro.org
Message-Id: <20210817162118.24319-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[rth: Added missing returns; set IL bit in syndrome]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4197927eeb404ffcd290d63e0f2d197bf18c391f
https://github.com/qemu/qemu/commit/4197927eeb404ffcd290d63e0f2d197bf18c391f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
It is confusing to have different exits from translation
for various conditions in separate functions.
Merge disas_a64_insn into its only caller. Standardize
on the "s" name for the DisasContext, as the code from
disas_a64_insn had more instances.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210821195958.41312-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 15fb0c86227ddeba01e71966ee9eaa9062b20647
https://github.com/qemu/qemu/commit/15fb0c86227ddeba01e71966ee9eaa9062b20647
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M include/hw/qdev-core.h
M softmmu/qdev-monitor.c
Log Message:
-----------
qdev: Support marking individual buses as 'full'
By default, QEMU will allow devices to be plugged into a bus up to
the bus class's device count limit. If the user creates a device on
the command line or via the monitor and doesn't explicitly specify
the bus to plug it in, QEMU will plug it into the first non-full bus
that it finds.
This is fine in most cases, but some machines have multiple buses of
a given type, some of which are dedicated to on-board devices and
some of which have an externally exposed connector for user-pluggable
devices. One example is I2C buses.
Provide a new function qbus_mark_full() so that a machine model can
mark this kind of "internal only" bus as 'full' after it has created
all the devices that should be plugged into that bus. The "find a
non-full bus" algorithm will then skip the internal-only bus when
looking for a place to plug in user-created devices.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-2-peter.maydell@linaro.org
Commit: ba5a567f401d176a03780f152c25568b0e7b1560
https://github.com/qemu/qemu/commit/ba5a567f401d176a03780f152c25568b0e7b1560
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
The mps2-tz boards use a data-driven structure to create the devices
that sit behind peripheral protection controllers. Currently the
functions which create these devices are passed an 'opaque' pointer
which is always the address within the machine struct of the device
to create, and some "all devices need this" information like irqs and
addresses.
If a specific device needs more information than this, it is
currently not possible to pass that through from the PPCInfo
data structure. Add support for passing an extra data parameter,
so that we can more flexibly handle the needs of specific
device types. To provide some type-safety we make this extra
parameter a pointer to a union (which initially has no members).
In particular, we would like to be able to indicate which of the
i2c controllers are for on-board devices only and which are
connected to the external 'shield' expansion port; a subsequent
patch will use this mechanism for that purpose.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-3-peter.maydell@linaro.org
Commit: 8d61ea6137ad420a99fa8f72a3c086a6206d90ad
https://github.com/qemu/qemu/commit/8d61ea6137ad420a99fa8f72a3c086a6206d90ad
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
The various MPS2 boards have multiple I2C buses: typically a bus
dedicated to the audio configuration, one for the LCD touchscreen
controller, one for a DDR4 EEPROM, and two which are connected to the
external Shield expansion connector. Mark the buses which are used
only for board-internal devices as 'full' so that if the user creates
i2c devices on the commandline without specifying a bus name then
they will be connected to the I2C controller used for the Shield
connector, where guest software will expect them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-4-peter.maydell@linaro.org
Commit: eec607843ca81eccab238fce86222be9c78b3675
https://github.com/qemu/qemu/commit/eec607843ca81eccab238fce86222be9c78b3675
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
The various MPS2 boards implemented in mps2.c have multiple I2C
buses: a bus dedicated to the audio configuration, one for the LCD
touchscreen controller, and two which are connected to the external
Shield expansion connector. Mark the buses which are used only for
board-internal devices as 'full' so that if the user creates i2c
devices on the commandline without specifying a bus name then they
will be connected to the I2C controller used for the Shield
connector, where guest software will expect them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-5-peter.maydell@linaro.org
Commit: ec86c3cce0bb5c2f9d98f320cbf7d46caaa08102
https://github.com/qemu/qemu/commit/ec86c3cce0bb5c2f9d98f320cbf7d46caaa08102
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-13 (Mon, 13 Sep 2021)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/npcm7xx_boards.c
M hw/arm/virt.c
M hw/char/cadence_uart.c
M hw/intc/arm_gicv3.c
M hw/intc/arm_gicv3_common.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/arm_gicv3_dist.c
A hw/intc/arm_gicv3_its.c
M hw/intc/arm_gicv3_its_common.c
M hw/intc/arm_gicv3_its_kvm.c
M hw/intc/arm_gicv3_redist.c
M hw/intc/gicv3_internal.h
M hw/intc/meson.build
M hw/misc/zynq_slcr.c
M include/hw/arm/virt.h
M include/hw/intc/arm_gicv3_common.h
M include/hw/intc/arm_gicv3_its_common.h
M include/hw/qdev-core.h
M softmmu/qdev-monitor.c
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/kvm.c
M target/arm/kvm_arm.h
M target/arm/syndrome.h
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
A tests/data/acpi/virt/IORT
A tests/data/acpi/virt/IORT.memhp
A tests/data/acpi/virt/IORT.numamem
A tests/data/acpi/virt/IORT.pxb
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20210913-2' into staging
target-arm queue:
* mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
line user-created devices are not plugged into them
* Take an exception if PSTATE.IL is set
* Support an emulated ITS in the virt board
* Add support for kudo-bmc board
* Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
* cadence_uart: Fix clock handling issues that prevented
u-boot from running
# gpg: Signature made Mon 13 Sep 2021 19:49:37 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210913-2: (23 commits)
hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
qdev: Support marking individual buses as 'full'
target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
target/arm: Take an exception if PSTATE.IL is set
tests/data/acpi/virt: Update IORT files for ITS
hw/arm/virt: add ITS support in virt GIC
tests/data/acpi/virt: Add IORT files for ITS
hw/intc: GICv3 redistributor ITS processing
hw/intc: GICv3 ITS Feature enablement
hw/intc: GICv3 ITS Command processing
hw/intc: GICv3 ITS command queue framework
hw/intc: GICv3 ITS register definitions added
hw/intc: GICv3 ITS initial framework
hw/arm: Add support for kudo-bmc board.
hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
hw/char: cadence_uart: Log a guest error when device is unclocked or in reset
hw/char: cadence_uart: Ignore access when unclocked or in reset for
uart_{read, write}()
hw/char: cadence_uart: Convert to memop_with_attrs() ops
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/001e6fd6c771...ec86c3cce0bb
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