[Qemu-commits] [qemu/qemu] a89b91: hw/misc: zynq_slcr: Correctly compute output clock...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a89b91addf2b28613a89b842f501c903a819de68
      
https://github.com/qemu/qemu/commit/a89b91addf2b28613a89b842f501c903a819de68
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase

As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as
per the logic in uart_receive().

>From zynq_slcr_reset_exit() comment, it intends to compute output
clocks according to ps_clk and registers. zynq_slcr_compute_clocks()
is called to accomplish the task, inside which device_is_in_reset()
is called to actually make the attempt in vain.

Rework reset_hold() and reset_exit() so that in the reset exit phase,
the logic can really compute output clocks in reset_exit().

With this change, upstream U-Boot boots properly again with:

$ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null -serial 
stdio \
    -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0

Fixes: 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210901124521.30599-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 62a3f63182a7cda98bdc168ed841507befca014f
      
https://github.com/qemu/qemu/commit/62a3f63182a7cda98bdc168ed841507befca014f
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char: cadence_uart: Disable transmit when input clock is disabled

At present when input clock is disabled, any character transmitted
to tx fifo can still show on the serial line, which is wrong.

Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210901124521.30599-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 983f4adf364628bf1e75f99d85a47a803d2e2dce
      
https://github.com/qemu/qemu/commit/983f4adf364628bf1e75f99d85a47a803d2e2dce
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char: cadence_uart: Move clock/reset check to uart_can_receive()

Currently the clock/reset check is done in uart_receive(), but we
can move the check to uart_can_receive() which is earlier.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7956a8f5dd702adf351575b2aee9dbd99001b61f
      
https://github.com/qemu/qemu/commit/7956a8f5dd702adf351575b2aee9dbd99001b61f
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char: cadence_uart: Convert to memop_with_attrs() ops

This converts uart_read() and uart_write() to memop_with_attrs() ops.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-5-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9834ecaaea8dfe1def47431f096a2b77de3583a1
      
https://github.com/qemu/qemu/commit/9834ecaaea8dfe1def47431f096a2b77de3583a1
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char: cadence_uart: Ignore access when unclocked or in reset for 
uart_{read, write}()

Read or write to uart registers when unclocked or in reset should be
ignored. Add the check there, and as a result of this, the check in
uart_write_tx_fifo() is now unnecessary.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 47c305f6f2761c5be9b5a69721cd586aaae0d43e
      
https://github.com/qemu/qemu/commit/47c305f6f2761c5be9b5a69721cd586aaae0d43e
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/char/cadence_uart.c

  Log Message:
  -----------
  hw/char: cadence_uart: Log a guest error when device is unclocked or in reset

We've got SW that expects FSBL (Bootlooader) to setup clocks and
resets. It's quite common that users run that SW on QEMU without
FSBL (FSBL typically requires the Xilinx tools installed). That's
fine, since users can stil use -device loader to enable clocks etc.

To help folks understand what's going, a log (guest-error) message
would be helpful here. In particular with the serial port since
things will go very quiet if they get things wrong.

Suggested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210901124521.30599-7-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d26f2f93c1853810fad7da7faa2fa1d590c1017b
      
https://github.com/qemu/qemu/commit/d26f2f93c1853810fad7da7faa2fa1d590c1017b
  Author: Marc Zyngier <maz@kernel.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M target/arm/kvm.c

  Log Message:
  -----------
  hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM

Although we probe for the IPA limits imposed by KVM (and the hardware)
when computing the memory map, we still use the old style '0' when
creating a scratch VM in kvm_arm_create_scratch_host_vcpu().

On systems that are severely IPA challenged (such as the Apple M1),
this results in a failure as KVM cannot use the default 40bit that
'0' represents.

Instead, probe for the extension and use the reported IPA limit
if available.

Cc: Andrew Jones <drjones@redhat.com>
Cc: Eric Auger <eric.auger@redhat.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20210822144441.1290891-2-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3b8a4733d1dfb3dd7cbf32fa031b092e28eedd0f
      
https://github.com/qemu/qemu/commit/3b8a4733d1dfb3dd7cbf32fa031b092e28eedd0f
  Author: Chris Rauer <crauer@google.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/arm/npcm7xx_boards.c

  Log Message:
  -----------
  hw/arm: Add support for kudo-bmc board.

kudo-bmc is a board supported by OpenBMC.
https://github.com/openbmc/openbmc/tree/master/meta-fii/meta-kudo

Since v1:
- hyphenated Cortex-A9

Tested: Booted kudo firmware.
Signed-off-by: Chris Rauer <crauer@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20210907223234.1165705-1-crauer@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 18f6290a6a95b2b16ab061bfd92274f6ba2a821b
      
https://github.com/qemu/qemu/commit/18f6290a6a95b2b16ab061bfd92274f6ba2a821b
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    A hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_its_common.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/gicv3_internal.h
    M hw/intc/meson.build
    M include/hw/intc/arm_gicv3_its_common.h

  Log Message:
  -----------
  hw/intc: GICv3 ITS initial framework

Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-2-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1b08e436d0deaece35f7fa21aba6e6afe26cb3ac
      
https://github.com/qemu/qemu/commit/1b08e436d0deaece35f7fa21aba6e6afe26cb3ac
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/intc/arm_gicv3_its_common.h

  Log Message:
  -----------
  hw/intc: GICv3 ITS register definitions added

Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for subsequent ITS processing) and
initialize the same in ITS device.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-3-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 07b42bd43e2760fe8fc029d3cc91ab86e09ca67d
      
https://github.com/qemu/qemu/commit/07b42bd43e2760fe8fc029d3cc91ab86e09ca67d
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h

  Log Message:
  -----------
  hw/intc: GICv3 ITS command queue framework

Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-4-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 36a033d3e66e2bcb942a816471488085906458dd
      
https://github.com/qemu/qemu/commit/36a033d3e66e2bcb942a816471488085906458dd
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/intc/arm_gicv3_its.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc: GICv3 ITS Command processing

Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands make use of other functionalities implemented to
get device table entry,collection table entry or interrupt translation
table entry required for their processing.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-5-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e4211582d750220cf3784ca1742308812d04583c
      
https://github.com/qemu/qemu/commit/e4211582d750220cf3784ca1742308812d04583c
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_dist.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc: GICv3 ITS Feature enablement

Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Message-id: 20210910143951.92242-6-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a2021f57d016be9cf08e30152096a5bb73346782
      
https://github.com/qemu/qemu/commit/a2021f57d016be9cf08e30152096a5bb73346782
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc: GICv3 redistributor ITS processing

Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part of ITS INT,CLEAR,DISCARD command and
GITS_TRANSLATER processing.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-7-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 39e5fd9b2dfd5f8f4bd989cd456ac8f9a1c38922
      
https://github.com/qemu/qemu/commit/39e5fd9b2dfd5f8f4bd989cd456ac8f9a1c38922
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    A tests/data/acpi/virt/IORT
    A tests/data/acpi/virt/IORT.memhp
    A tests/data/acpi/virt/IORT.numamem
    A tests/data/acpi/virt/IORT.pxb
    M tests/qtest/bios-tables-test-allowed-diff.h

  Log Message:
  -----------
  tests/data/acpi/virt: Add IORT files for ITS

Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-8-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a172caa8b04b5527a86408f7d0446c1bfdf4573e
      
https://github.com/qemu/qemu/commit/a172caa8b04b5527a86408f7d0446c1bfdf4573e
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  hw/arm/virt: add ITS support in virt GIC

Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-9-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 757466001d3e7e426f0077066b51535fd56c9020
      
https://github.com/qemu/qemu/commit/757466001d3e7e426f0077066b51535fd56c9020
  Author: Shashi Mallela <shashi.mallela@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M tests/data/acpi/virt/IORT
    M tests/data/acpi/virt/IORT.memhp
    M tests/data/acpi/virt/IORT.numamem
    M tests/data/acpi/virt/IORT.pxb
    M tests/qtest/bios-tables-test-allowed-diff.h

  Log Message:
  -----------
  tests/data/acpi/virt: Update IORT files for ITS

Updated expected IORT files applicable with latest GICv3
ITS changes.

Full diff of new file disassembly:

/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20180629 (64-bit version)
 * Copyright (c) 2000 - 2018 Intel Corporation
 *
 * Disassembly of tests/data/acpi/virt/IORT.pxb, Tue Jun 29 17:35:38 2021
 *
 * ACPI Data Table [IORT]
 *
 * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
 */

[000h 0000   4]                    Signature : "IORT"    [IO Remapping Table]
[004h 0004   4]                 Table Length : 0000007C
[008h 0008   1]                     Revision : 00
[009h 0009   1]                     Checksum : 07
[00Ah 0010   6]                       Oem ID : "BOCHS "
[010h 0016   8]                 Oem Table ID : "BXPC    "
[018h 0024   4]                 Oem Revision : 00000001
[01Ch 0028   4]              Asl Compiler ID : "BXPC"
[020h 0032   4]        Asl Compiler Revision : 00000001

[024h 0036   4]                   Node Count : 00000002
[028h 0040   4]                  Node Offset : 00000030
[02Ch 0044   4]                     Reserved : 00000000

[030h 0048   1]                         Type : 00
[031h 0049   2]                       Length : 0018
[033h 0051   1]                     Revision : 00
[034h 0052   4]                     Reserved : 00000000
[038h 0056   4]                Mapping Count : 00000000
[03Ch 0060   4]               Mapping Offset : 00000000

[040h 0064   4]                     ItsCount : 00000001
[044h 0068   4]                  Identifiers : 00000000

[048h 0072   1]                         Type : 02
[049h 0073   2]                       Length : 0034
[04Bh 0075   1]                     Revision : 00
[04Ch 0076   4]                     Reserved : 00000000
[050h 0080   4]                Mapping Count : 00000001
[054h 0084   4]               Mapping Offset : 00000020

[058h 0088   8]            Memory Properties : [IORT Memory Access Properties]
[058h 0088   4]              Cache Coherency : 00000001
[05Ch 0092   1]        Hints (decoded below) : 00
                                   Transient : 0
                              Write Allocate : 0
                               Read Allocate : 0
                                    Override : 0
[05Dh 0093   2]                     Reserved : 0000
[05Fh 0095   1] Memory Flags (decoded below) : 03
                                   Coherency : 1
                            Device Attribute : 1
[060h 0096   4]                ATS Attribute : 00000000
[064h 0100   4]           PCI Segment Number : 00000000
[068h 0104   1]            Memory Size Limit : 00
[069h 0105   3]                     Reserved : 000000

[068h 0104   4]                   Input base : 00000000
[06Ch 0108   4]                     ID Count : 0000FFFF
[070h 0112   4]                  Output Base : 00000000
[074h 0116   4]             Output Reference : 00000030
[078h 0120   4]        Flags (decoded below) : 00000000
                              Single Mapping : 0

Raw Table Data: Length 124 (0x7C)

    0000: 49 4F 52 54 7C 00 00 00 00 07 42 4F 43 48 53 20  // IORT|.....BOCHS
    0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43  // BXPC    ....BXPC
    0020: 01 00 00 00 02 00 00 00 30 00 00 00 00 00 00 00  // ........0.......
    0030: 00 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00  // ................
    0040: 01 00 00 00 00 00 00 00 02 34 00 00 00 00 00 00  // .........4......
    0050: 01 00 00 00 20 00 00 00 01 00 00 00 00 00 00 03  // .... ...........
    0060: 00 00 00 00 00 00 00 00 00 00 00 00 FF FF 00 00  // ................
    0070: 00 00 00 00 30 00 00 00 00 00 00 00              // ....0.......

Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210910143951.92242-10-shashi.mallela@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3193f3a038e3e1cf22193e5ad5a77b4223204e94
      
https://github.com/qemu/qemu/commit/3193f3a038e3e1cf22193e5ad5a77b4223204e94
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/syndrome.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Take an exception if PSTATE.IL is set

In v8A, the PSTATE.IL bit is set for various kinds of illegal
exception return or mode-change attempts.  We already set PSTATE.IL
(or its AArch32 equivalent CPSR.IL) in all those cases, but we
weren't implementing the part of the behaviour where attempting to
execute an instruction with PSTATE.IL takes an immediate exception
with an appropriate syndrome value.

Add a new TB flags bit tracking PSTATE.IL/CPSR.IL, and generate code
to take an exception instead of whatever the instruction would have
been.

PSTATE.IL and CPSR.IL change only on exception entry, attempted
exception exit, and various AArch32 mode changes via cpsr_write().
These places generally already rebuild the hflags, so the only place
we need an extra rebuild_hflags call is in the illegal-return
codepath of the AArch64 exception_return helper.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210821195958.41312-2-richard.henderson@linaro.org
Message-Id: <20210817162118.24319-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[rth: Added missing returns; set IL bit in syndrome]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 37cf4623a0f822c574569c54f9f636ad59f55906
      
https://github.com/qemu/qemu/commit/37cf4623a0f822c574569c54f9f636ad59f55906
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn

It is confusing to have different exits from translation
for various conditions in separate functions.

Merge disas_a64_insn into its only caller.  Standardize
on the "s" name for the DisasContext, as the code from
disas_a64_insn had more instances.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210821195958.41312-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 62ba9bc875ef609ca963ebc8ee676b733f240519
      
https://github.com/qemu/qemu/commit/62ba9bc875ef609ca963ebc8ee676b733f240519
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M include/hw/qdev-core.h
    M softmmu/qdev-monitor.c

  Log Message:
  -----------
  qdev: Support marking individual buses as 'full'

By default, QEMU will allow devices to be plugged into a bus up to
the bus class's device count limit.  If the user creates a device on
the command line or via the monitor and doesn't explicitly specify
the bus to plug it in, QEMU will plug it into the first non-full bus
that it finds.

This is fine in most cases, but some machines have multiple buses of
a given type, some of which are dedicated to on-board devices and
some of which have an externally exposed connector for user-pluggable
devices. One example is I2C buses.

Provide a new function qbus_mark_full() so that a machine model can
mark this kind of "internal only" bus as 'full' after it has created
all the devices that should be plugged into that bus. The "find a
non-full bus" algorithm will then skip the internal-only bus when
looking for a place to plug in user-created devices.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-2-peter.maydell@linaro.org


  Commit: 8eacbc36a1caa601895bfc50da6bc4a8cfe728fc
      
https://github.com/qemu/qemu/commit/8eacbc36a1caa601895bfc50da6bc4a8cfe728fc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn

The mps2-tz boards use a data-driven structure to create the devices
that sit behind peripheral protection controllers.  Currently the
functions which create these devices are passed an 'opaque' pointer
which is always the address within the machine struct of the device
to create, and some "all devices need this" information like irqs and
addresses.

If a specific device needs more information than this, it is
currently not possible to pass that through from the PPCInfo
data structure. Add support for passing an extra data parameter,
so that we can more flexibly handle the needs of specific
device types. To provide some type-safety we make this extra
parameter a pointer to a union (which initially has no members).

In particular, we would like to be able to indicate which of the
i2c controllers are for on-board devices only and which are
connected to the external 'shield' expansion port; a subsequent
patch will use this mechanism for that purpose.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-3-peter.maydell@linaro.org


  Commit: abfec9704f020b0707940a030625f35ff2dfc371
      
https://github.com/qemu/qemu/commit/abfec9704f020b0707940a030625f35ff2dfc371
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'

The various MPS2 boards have multiple I2C buses: typically a bus
dedicated to the audio configuration, one for the LCD touchscreen
controller, one for a DDR4 EEPROM, and two which are connected to the
external Shield expansion connector.  Mark the buses which are used
only for board-internal devices as 'full' so that if the user creates
i2c devices on the commandline without specifying a bus name then
they will be connected to the I2C controller used for the Shield
connector, where guest software will expect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-4-peter.maydell@linaro.org


  Commit: 9a2b2ecf4d25a3943918c95d2db4508b304161b5
      
https://github.com/qemu/qemu/commit/9a2b2ecf4d25a3943918c95d2db4508b304161b5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2.c: Mark internal-only I2C buses as 'full'

The various MPS2 boards implemented in mps2.c have multiple I2C
buses: a bus dedicated to the audio configuration, one for the LCD
touchscreen controller, and two which are connected to the external
Shield expansion connector.  Mark the buses which are used only for
board-internal devices as 'full' so that if the user creates i2c
devices on the commandline without specifying a bus name then they
will be connected to the I2C controller used for the Shield
connector, where guest software will expect them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210903151435.22379-5-peter.maydell@linaro.org


  Commit: 54babfa57d9f07b45b2572b90bbb5d25e9a153fa
      
https://github.com/qemu/qemu/commit/54babfa57d9f07b45b2572b90bbb5d25e9a153fa
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/npcm7xx_boards.c
    M hw/arm/virt.c
    M hw/char/cadence_uart.c
    M hw/intc/arm_gicv3.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_dist.c
    A hw/intc/arm_gicv3_its.c
    M hw/intc/arm_gicv3_its_common.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/arm_gicv3_redist.c
    M hw/intc/gicv3_internal.h
    M hw/intc/meson.build
    M hw/misc/zynq_slcr.c
    M include/hw/arm/virt.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/intc/arm_gicv3_its_common.h
    M include/hw/qdev-core.h
    M softmmu/qdev-monitor.c
    M target/arm/cpu.h
    M target/arm/helper-a64.c
    M target/arm/helper.c
    M target/arm/kvm.c
    M target/arm/kvm_arm.h
    M target/arm/syndrome.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    A tests/data/acpi/virt/IORT
    A tests/data/acpi/virt/IORT.memhp
    A tests/data/acpi/virt/IORT.numamem
    A tests/data/acpi/virt/IORT.pxb

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210913' 
into staging

target-arm queue:
 * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command
   line user-created devices are not plugged into them
 * Take an exception if PSTATE.IL is set
 * Support an emulated ITS in the virt board
 * Add support for kudo-bmc board
 * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
 * cadence_uart: Fix clock handling issues that prevented
   u-boot from running

# gpg: Signature made Mon 13 Sep 2021 17:11:15 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210913: (23 commits)
  hw/arm/mps2.c: Mark internal-only I2C buses as 'full'
  hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full'
  hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn
  qdev: Support marking individual buses as 'full'
  target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn
  target/arm: Take an exception if PSTATE.IL is set
  tests/data/acpi/virt: Update IORT files for ITS
  hw/arm/virt: add ITS support in virt GIC
  tests/data/acpi/virt: Add IORT files for ITS
  hw/intc: GICv3 redistributor ITS processing
  hw/intc: GICv3 ITS Feature enablement
  hw/intc: GICv3 ITS Command processing
  hw/intc: GICv3 ITS command queue framework
  hw/intc: GICv3 ITS register definitions added
  hw/intc: GICv3 ITS initial framework
  hw/arm: Add support for kudo-bmc board.
  hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM
  hw/char: cadence_uart: Log a guest error when device is unclocked or in reset
  hw/char: cadence_uart: Ignore access when unclocked or in reset for 
uart_{read, write}()
  hw/char: cadence_uart: Convert to memop_with_attrs() ops
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/7d79344d4fa4...54babfa57d9f