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[Qemu-commits] [qemu/qemu] 982fd3: target/i386: add missing bits to CR4_
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 982fd3: target/i386: add missing bits to CR4_RESERVED_MASK |
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Date: |
Tue, 07 Sep 2021 08:14:50 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 982fd3e4424af593fa8e8f4dc2538437792e2054
https://github.com/qemu/qemu/commit/982fd3e4424af593fa8e8f4dc2538437792e2054
Author: Daniel P. Berrangé <berrange@redhat.com>
Date: 2021-09-06 (Mon, 06 Sep 2021)
Changed paths:
M target/i386/cpu.h
Log Message:
-----------
target/i386: add missing bits to CR4_RESERVED_MASK
Booting Fedora kernels with -cpu max hangs very early in boot. Disabling
the la57 CPUID bit fixes the problem. git bisect traced the regression to
commit 213ff024a2f92020290296cb9dc29c2af3d4a221 (HEAD, refs/bisect/bad)
Author: Lara Lazier <laramglazier@gmail.com>
Date: Wed Jul 21 17:26:50 2021 +0200
target/i386: Added consistency checks for CR4
All MBZ bits in CR4 must be zero. (APM2 15.5)
Added reserved bitmask and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210721152651.14683-2-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In this commit CR4_RESERVED_MASK is missing CR4_LA57_MASK and
two others. Adding this lets Fedora kernels boot once again.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Message-Id: <20210831175033.175584-1-berrange@redhat.com>
[Removed VMXE/SMXE, matching the commit message. - Paolo]
Fixes: 213ff024a2 ("target/i386: Added consistency checks for CR4", 2021-07-22)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8e4e83d3a45d3e31256c913a67a7007c40e3b38b
https://github.com/qemu/qemu/commit/8e4e83d3a45d3e31256c913a67a7007c40e3b38b
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-06 (Mon, 06 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: VMRUN and VMLOAD canonicalizations
APM2 requires that VMRUN and VMLOAD canonicalize (sign extend to 63
from 48/57) all base addresses in the segment registers that have been
respectively loaded.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210804113058.45186-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4a9ec59db93133698dac4d721412e38b41cdaf06
https://github.com/qemu/qemu/commit/4a9ec59db93133698dac4d721412e38b41cdaf06
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-06 (Mon, 06 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/svm.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF feature
VGIF allows STGI and CLGI to execute in guest mode and control virtual
interrupts in guest mode.
When the VGIF feature is enabled then:
* executing STGI in the guest sets bit 9 of the VMCB offset 60h.
* executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210730070742.9674-1-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 9fa3e4e39a871c8ff901069325feb53fcbcd0d26
https://github.com/qemu/qemu/commit/9fa3e4e39a871c8ff901069325feb53fcbcd0d26
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/machine.c
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Moved int_ctl into CPUX86State structure
Moved int_ctl into the CPUX86State structure. It removes some
unnecessary stores and loads, and prepares for tracking the vIRQ
state even when it is masked due to vGIF.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bbdc4467477d4ea04dbadd86cdbda9f3b3811fe1
https://github.com/qemu/qemu/commit/bbdc4467477d4ea04dbadd86cdbda9f3b3811fe1
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added VGIF V_IRQ masking capability
VGIF provides masking capability for when virtual interrupts
are taken. (APM2)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5a0eef70a58d4acaa209efc40a6dbd55f44ae86e
https://github.com/qemu/qemu/commit/5a0eef70a58d4acaa209efc40a6dbd55f44ae86e
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added ignore TPR check in ctl_has_irq
The APM2 states that if V_IGN_TPR is nonzero, the current
virtual interrupt ignores the (virtual) TPR.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 731331cc29592a107112b635d93da66c20ea0c1c
https://github.com/qemu/qemu/commit/731331cc29592a107112b635d93da66c20ea0c1c
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added changed priority check for VIRQ
Writes to cr8 affect v_tpr. This could set or unset an interrupt
request as the priority might have changed.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f3f109bcda23f71dd5f89f4813ab6d209014742
https://github.com/qemu/qemu/commit/5f3f109bcda23f71dd5f89f4813ab6d209014742
Author: Lara Lazier <laramglazier@gmail.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.h
M target/i386/svm.h
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
target/i386: Added vVMLOAD and vVMSAVE feature
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode
without
causing a VMEXIT. (APM2 15.33.1)
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0c6a099e438cc85ef19c857e29f9675ba49ab503
https://github.com/qemu/qemu/commit/0c6a099e438cc85ef19c857e29f9675ba49ab503
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/vfio/common.c
M include/exec/memory.h
M softmmu/memory.c
M softmmu/physmem.c
Log Message:
-----------
memory: Add RAM_PROTECTED flag to skip IOMMU mappings
Add a new RAMBlock flag to denote "protected" memory, i.e. memory that
looks and acts like RAM but is inaccessible via normal mechanisms,
including DMA. Use the flag to skip protected memory regions when
mapping RAM for DMA in VFIO.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Unified the "share" and "protected" arguments with ram_flags in the
memory_region_init_ram_from_fd()(Paolo).
Message-Id: <20210719112136.57018-2-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 696da79c93bca804c96103a44cae7fe47aeb3ad7
https://github.com/qemu/qemu/commit/696da79c93bca804c96103a44cae7fe47aeb3ad7
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
Log Message:
-----------
hostmem: Add hostmem-epc as a backend for SGX EPC
EPC (Enclave Page Cahe) is a specialized type of memory used by Intel
SGX (Software Guard Extensions). The SDM desribes EPC as:
The Enclave Page Cache (EPC) is the secure storage used to store
enclave pages when they are a part of an executing enclave. For an
EPC page, hardware performs additional access control checks to
restrict access to the page. After the current page access checks
and translations are performed, the hardware checks that the EPC
page is accessible to the program currently executing. Generally an
EPC page is only accessed by the owner of the executing enclave or
an instruction which is setting up an EPC page.
Because of its unique requirements, Linux manages EPC separately from
normal memory. Similar to memfd, the device /dev/sgx_vepc can be
opened to obtain a file descriptor which can in turn be used to mmap()
EPC memory.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Unified the "share" and "protected" arguments with ram_flags in the
memory_region_init_ram_from_fd()(Paolo).
Message-Id: <20210719112136.57018-3-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a7212a5a689063c5c04d35c32cab479a4f2d2d70
https://github.com/qemu/qemu/commit/a7212a5a689063c5c04d35c32cab479a4f2d2d70
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M qapi/qom.json
Log Message:
-----------
qom: Add memory-backend-epc ObjectOptions support
Add the new 'memory-backend-epc' user creatable QOM object in
the ObjectOptions to support SGX since v6.1, or the sgx backend
object cannot bootup.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v1-->v2:
- Added the new MemoryBackendEpcProperties and related documents,
and updated the blurb(Eric Blake).
Message-Id: <20210719112136.57018-4-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e03caae5d3f9a0b6c238a3c446d6818db7469ad0
https://github.com/qemu/qemu/commit/e03caae5d3f9a0b6c238a3c446d6818db7469ad0
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/meson.build
A hw/i386/sgx-epc.c
A include/hw/i386/sgx-epc.h
Log Message:
-----------
i386: Add 'sgx-epc' device to expose EPC sections to guest
SGX EPC is enumerated through CPUID, i.e. EPC "devices" need to be
realized prior to realizing the vCPUs themselves, which occurs long
before generic devices are parsed and realized. Because of this,
do not allow 'sgx-epc' devices to be instantiated after vCPUS have
been created.
The 'sgx-epc' device is essentially a placholder at this time, it will
be fully implemented in a future patch along with a dedicated command
to create 'sgx-epc' devices.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-5-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: fbbb3d92f54a5c9082320465fcfc7032449dc304
https://github.com/qemu/qemu/commit/fbbb3d92f54a5c9082320465fcfc7032449dc304
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/meson.build
M hw/i386/sgx-epc.c
A hw/i386/sgx.c
M hw/i386/x86.c
M include/hw/i386/pc.h
M include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M qapi/machine.json
M qemu-options.hx
Log Message:
-----------
vl: Add sgx compound properties to expose SGX EPC sections to guest
Because SGX EPC is enumerated through CPUID, EPC "devices" need to be
realized prior to realizing the vCPUs themselves, i.e. long before
generic devices are parsed and realized. From a virtualization
perspective, the CPUID aspect also means that EPC sections cannot be
hotplugged without paravirtualizing the guest kernel (hardware does
not support hotplugging as EPC sections must be locked down during
pre-boot to provide EPC's security properties).
So even though EPC sections could be realized through the generic
-devices command, they need to be created much earlier for them to
actually be usable by the guest. Place all EPC sections in a
contiguous block, somewhat arbitrarily starting after RAM above 4g.
Ensuring EPC is in a contiguous region simplifies calculations, e.g.
device memory base, PCI hole, etc..., allows dynamic calculation of the
total EPC size, e.g. exposing EPC to guests does not require -maxmem,
and last but not least allows all of EPC to be enumerated in a single
ACPI entry, which is expected by some kernels, e.g. Windows 7 and 8.
The new compound properties command for sgx like below:
......
-object memory-backend-epc,id=mem1,size=28M,prealloc=on \
-object memory-backend-epc,id=mem2,size=10M \
-M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Moved sgx compound property setter/getter from MachineState
to X86MachineState(Paolo).
- Re-defined struct SgxEPC, removed 'id' property and added struct
SgxEPCList for sgx-epc.0.{memdev}(Paolo).
- Removed g_malloc0(), and changed the 'SGXEPCState *sgx_epc' to
'SGXEPCState sgx_epc' in struct PCMachineState(Paolo).
- Changed the SGX compound property cmdline from sgx-epc.{memdev}.0
to sgx-epc.0.{memdev}(Paolo).
v2-->v3:
- Removed the QemuOptsList for sgx-epc virtual device and used the '-M' to
replace '-sgx-epc' with compound properties(Paolo).
Message-Id: <20210719112136.57018-6-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 32276d3863cdd275e5f83832728a7eb04ca636e1
https://github.com/qemu/qemu/commit/32276d3863cdd275e5f83832728a7eb04ca636e1
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add primary SGX CPUID and MSR defines
Add CPUID defines for SGX and SGX Launch Control (LC), as well as
defines for their associated FEATURE_CONTROL MSR bits. Define the
Launch Enclave Public Key Hash MSRs (LE Hash MSRs), which exist
when SGX LC is present (in CPUID), and are writable when SGX LC is
enabled (in FEATURE_CONTROL).
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-7-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d26ac8ce42c5b6e64e374ecb1142869dc44618c5
https://github.com/qemu/qemu/commit/d26ac8ce42c5b6e64e374ecb1142869dc44618c5
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
CPUID leaf 12_0_EAX is an Intel-defined feature bits leaf enumerating
the CPU's SGX capabilities, e.g. supported SGX instruction sets.
Currently there are four enumerated capabilities:
- SGX1 instruction set, i.e. "base" SGX
- SGX2 instruction set for dynamic EPC management
- ENCLV instruction set for VMM oversubscription of EPC
- ENCLS-C instruction set for thread safe variants of ENCLS
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-8-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 03780b85a6b2ef418e3a37a1e9ffdd1292514695
https://github.com/qemu/qemu/commit/03780b85a6b2ef418e3a37a1e9ffdd1292514695
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX
CPUID leaf 12_0_EBX is an Intel-defined feature bits leaf enumerating
the platform's SGX extended capabilities. Currently there is a single
capabilitiy:
- EXINFO: record information about #PFs and #GPs in the enclave's SSA
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-9-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8261b858c7cbc4f5c439c7433bedc19472efad86
https://github.com/qemu/qemu/commit/8261b858c7cbc4f5c439c7433bedc19472efad86
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
CPUID leaf 12_1_EAX is an Intel-defined feature bits leaf enumerating
the platform's SGX capabilities that may be utilized by an enclave, e.g.
whether or not an enclave can gain access to the provision key.
Currently there are six capabilities:
- INIT: set when the enclave has has been initialized by EINIT. Cannot
be set by software, i.e. forced to zero in CPUID.
- DEBUG: permits a debugger to read/write into the enclave.
- MODE64BIT: the enclave runs in 64-bit mode
- PROVISIONKEY: grants has access to the provision key
- EINITTOKENKEY: grants access to the EINIT token key, i.e. the
enclave can generate EINIT tokens
- KSS: Key Separation and Sharing enabled for the enclave.
Note that the entirety of CPUID.0x12.0x1, i.e. all registers, enumerates
the allowed ATTRIBUTES (128 bits), but only bits 31:0 are directly
exposed to the user (via FEAT_12_1_EAX). Bits 63:32 are currently all
reserved and bits 127:64 correspond to the allowed XSAVE Feature Request
Mask, which is calculated based on other CPU features, e.g. XSAVE, MPX,
AVX, etc... and is not exposed to the user.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-10-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 561598b6619191d0a0d6c8522e054bbd93eb1244
https://github.com/qemu/qemu/commit/561598b6619191d0a0d6c8522e054bbd93eb1244
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/machine.c
Log Message:
-----------
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.
KVM advertises SGX LC via CPUID if and only if the MSRs are writable.
Unconditionally initialize those MSRs to digest of Intel's signing key
when CPU is realized and reset to reflect the fact. This avoids
potential bug in case kvm_arch_put_registers() is called before
kvm_arch_get_registers() is called, in which case guest's virtual
SGX_LEPUBKEYHASH MSRs will be set to 0, although KVM initializes those
to digest of Intel's signing key by default, since KVM allows those MSRs
to be updated by Qemu to support live migration.
Save/restore the SGX Launch Enclave Public Key Hash MSRs if SGX Launch
Control (LC) is exposed to the guest. Likewise, migrate the MSRs if they
are writable by the guest.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Kai Huang <kai.huang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-11-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a2299f2f224ef7909e5e95b02493141cd8b4f725
https://github.com/qemu/qemu/commit/a2299f2f224ef7909e5e95b02493141cd8b4f725
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Add feature control MSR dependency when SGX is enabled
SGX adds multiple flags to FEATURE_CONTROL to enable SGX and Flexible
Launch Control.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-12-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 82326edb840e2ff535bb32756bf3bfbadd019ed1
https://github.com/qemu/qemu/commit/82326edb840e2ff535bb32756bf3bfbadd019ed1
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/sgx.c
M include/hw/i386/sgx-epc.h
M target/i386/cpu.c
Log Message:
-----------
i386: Update SGX CPUID info according to hardware/KVM/user input
Expose SGX to the guest if and only if KVM is enabled and supports
virtualization of SGX. While the majority of ENCLS can be emulated to
some degree, because SGX uses a hardware-based root of trust, the
attestation aspects of SGX cannot be emulated in software, i.e.
ultimately emulation will fail as software cannot generate a valid
quote/report. The complexity of partially emulating SGX in Qemu far
outweighs the value added, e.g. an SGX specific simulator for userspace
applications can emulate SGX for development and testing purposes.
Note, access to the PROVISIONKEY is not yet advertised to the guest as
KVM blocks access to the PROVISIONKEY by default and requires userspace
to provide additional credentials (via ioctl()) to expose PROVISIONKEY.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Replaced g_malloc0() with directly ....
Message-Id: <20210719112136.57018-13-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: e981f8eab97ce9635104126bf8b9ebce5310c937
https://github.com/qemu/qemu/commit/e981f8eab97ce9635104126bf8b9ebce5310c937
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
Log Message:
-----------
i386: kvm: Add support for exposing PROVISIONKEY to guest
If the guest want to fully use SGX, the guest needs to be able to
access provisioning key. Add a new KVM_CAP_SGX_ATTRIBUTE to KVM to
support provisioning key to KVM guests.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-14-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: af2b109dca91e0df51b7f3b1e76a84a86d10caaa
https://github.com/qemu/qemu/commit/af2b109dca91e0df51b7f3b1e76a84a86d10caaa
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386: Propagate SGX CPUID sub-leafs to KVM
The SGX sub-leafs are enumerated at CPUID 0x12. Indices 0 and 1 are
always present when SGX is supported, and enumerate SGX features and
capabilities. Indices >=2 are directly correlated with the platform's
EPC sections. Because the number of EPC sections is dynamic and user
defined, the number of SGX sub-leafs is "NULL" terminated.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-15-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 3324756e4e4b5e2f46871fdc9eef0a3a2b6132fe
https://github.com/qemu/qemu/commit/3324756e4e4b5e2f46871fdc9eef0a3a2b6132fe
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
Adjust min CPUID level to 0x12 when SGX is enabled
SGX capabilities are enumerated through CPUID_0x12.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-16-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6901d7a2b0a3a9a2cfb5d952b91062631f799d28
https://github.com/qemu/qemu/commit/6901d7a2b0a3a9a2cfb5d952b91062631f799d28
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/fw_cfg.c
Log Message:
-----------
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Request SGX an SGX Launch Control to be enabled in FEATURE_CONTROL
when the features are exposed to the guest. Our design is the SGX
Launch Control bit will be unconditionally set in FEATURE_CONTROL,
which is unlike host bios.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-17-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 6cd7669e8027ffb793cc8cfff36e5ec5806e47f8
https://github.com/qemu/qemu/commit/6cd7669e8027ffb793cc8cfff36e5ec5806e47f8
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/sgx-epc.h
Log Message:
-----------
hw/i386/pc: Account for SGX EPC sections when calculating device memory
Add helpers to detect if SGX EPC exists above 4g, and if so, where SGX
EPC above 4g ends. Use the helpers to adjust the device memory range
if SGX EPC exists above 4g.
For multiple virtual EPC sections, we just put them together physically
contiguous for the simplicity because we don't support EPC NUMA affinity
now. Once the SGX EPC NUMA support in the kernel SGX driver, we will
support this in the future.
Note that SGX EPC is currently hardcoded to reside above 4g.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-18-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 71812d20cdf1fc533b61fc253d08c7122650cbe7
https://github.com/qemu/qemu/commit/71812d20cdf1fc533b61fc253d08c7122650cbe7
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/pc.c
Log Message:
-----------
i386/pc: Add e820 entry for SGX EPC section(s)
Note that SGX EPC is currently guaranteed to reside in a single
contiguous chunk of memory regardless of the number of EPC sections.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-19-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 5f1ee5b7a7d2a80537655a5fe0d17f25294cc478
https://github.com/qemu/qemu/commit/5f1ee5b7a7d2a80537655a5fe0d17f25294cc478
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
i386: acpi: Add SGX EPC entry to ACPI tables
The ACPI Device entry for SGX EPC is essentially a hack whose primary
purpose is to provide software with a way to autoprobe SGX support,
e.g. to allow software to implement SGX support as a driver. Details
on the individual EPC sections are not enumerated through ACPI tables,
i.e. software must enumerate the EPC sections via CPUID. Furthermore,
software expects to see only a single EPC Device in the ACPI tables
regardless of the number of EPC sections in the system.
However, several versions of Windows do rely on the ACPI tables to
enumerate the address and size of the EPC. So, regardless of the number
of EPC sections exposed to the guest, create exactly *one* EPC device
with a _CRS entry that spans the entirety of all EPC sections (which are
guaranteed to be contiguous in Qemu).
Note, NUMA support for EPC memory is intentionally not considered as
enumerating EPC NUMA information is not yet defined for bare metal.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-20-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: a5a4aa60b8e839cc88005dc5bdaa6fd589802cda
https://github.com/qemu/qemu/commit/a5a4aa60b8e839cc88005dc5bdaa6fd589802cda
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/pc_q35.c
Log Message:
-----------
q35: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-21-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 99d0eae19b4f2e5cdf774e8165d814caac572da5
https://github.com/qemu/qemu/commit/99d0eae19b4f2e5cdf774e8165d814caac572da5
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
i440fx: Add support for SGX EPC
Enable SGX EPC virtualization, which is currently only support by KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-22-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 21c2a083c0cbcb54d710c61eeaa39f2abc88bcf3
https://github.com/qemu/qemu/commit/21c2a083c0cbcb54d710c61eeaa39f2abc88bcf3
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M backends/hostmem-epc.c
M include/hw/i386/pc.h
Log Message:
-----------
hostmem-epc: Add the reset interface for EPC backend reset
Add the sgx_memory_backend_reset() interface to handle EPC backend
reset when VM is reset. This reset function will destroy previous
backend memory region and re-mmap the EPC section for guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-23-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 0a4de79f8359a4e21f1d24012793ab846e4c475a
https://github.com/qemu/qemu/commit/0a4de79f8359a4e21f1d24012793ab846e4c475a
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
Log Message:
-----------
sgx-epc: Add the reset interface for sgx-epc virt device
If the VM is reset, we need make sure sgx virt epc in clean status.
Once the VM is reset, and sgx epc virt device will be reseted by
reset callback registered by qemu_register_reset(). Since this epc
virt device depend on backend, this reset will call backend reset
interface to re-mmap epc to guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-24-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ebd0cc087ee592c6738f683468fe70fba23d21a5
https://github.com/qemu/qemu/commit/ebd0cc087ee592c6738f683468fe70fba23d21a5
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
Log Message:
-----------
sgx-epc: Avoid bios reset during sgx epc initialization
Since bios do the reset when qemu boot up, and sgx epc will be
reset by the registered reset callback function. Like this, the
sgx epc will do two times initialization. This patch will check
protected mode from cr0 register, and will bypass reset operation
from bios. The reset callback will only accept reset operation
from guest.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-25-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d349498b33da85f4257dc750e6dadabce39b61ca
https://github.com/qemu/qemu/commit/d349498b33da85f4257dc750e6dadabce39b61ca
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M backends/hostmem-epc.c
Log Message:
-----------
hostmem-epc: Make prealloc consistent with qemu cmdline during reset
If qemu cmdline set the prealloc property for sgx epc and VM do the
reset the prealloc property will be different with cmdline settings.
This patch can make sure same prealloc property setting with cmdline.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-26-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 470278ee3beb5e0a3290a036bca8e66c1f4f223e
https://github.com/qemu/qemu/commit/470278ee3beb5e0a3290a036bca8e66c1f4f223e
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M backends/meson.build
M configs/devices/i386-softmmu/default.mak
M hw/i386/Kconfig
M hw/i386/meson.build
A hw/i386/sgx-stub.c
Log Message:
-----------
Kconfig: Add CONFIG_SGX support
Add new CONFIG_SGX for sgx support in the Qemu, and the Kconfig
default enable sgx in the i386 platform.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-32-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: c31f5243cf61041f1600c03d0c4aff969146de1c
https://github.com/qemu/qemu/commit/c31f5243cf61041f1600c03d0c4aff969146de1c
Author: Yang Zhong <yang.zhong@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
M hw/i386/sgx-epc.c
M monitor/hmp-cmds.c
M qapi/machine.json
Log Message:
-----------
sgx-epc: Add the fill_device_info() callback support
Since there is no fill_device_info() callback support, and when we
execute "info memory-devices" command in the monitor, the segfault
will be found.
This patch will add this callback support and "info memory-devices"
will show sgx epc memory exposed to guest. The result as below:
qemu) info memory-devices
Memory device [sgx-epc]: ""
memaddr: 0x180000000
size: 29360128
memdev: /objects/mem1
Memory device [sgx-epc]: ""
memaddr: 0x181c00000
size: 10485760
memdev: /objects/mem2
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
v3-->v4:
- Removed the epc device 'id' from compound property(Paolo).
v1-->v2:
- "Since: 5.1" to "Since: 6.1"(Eric Blake).
Message-Id: <20210719112136.57018-33-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 127c76bd1aa893122a22677b991c0f31ebef7f09
https://github.com/qemu/qemu/commit/127c76bd1aa893122a22677b991c0f31ebef7f09
Author: Sean Christopherson <sean.j.christopherson@intel.com>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
A docs/intel-sgx.txt
Log Message:
-----------
doc: Add the SGX doc
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-34-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: f31636a5d46ec39dc39a2416260577e0fb22116b
https://github.com/qemu/qemu/commit/f31636a5d46ec39dc39a2416260577e0fb22116b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-07 (Tue, 07 Sep 2021)
Changed paths:
A backends/hostmem-epc.c
M backends/meson.build
M configs/devices/i386-softmmu/default.mak
A docs/intel-sgx.txt
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/fw_cfg.c
M hw/i386/meson.build
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
A hw/i386/sgx-epc.c
A hw/i386/sgx-stub.c
A hw/i386/sgx.c
M hw/i386/x86.c
M hw/vfio/common.c
M include/exec/memory.h
M include/hw/i386/pc.h
A include/hw/i386/sgx-epc.h
M include/hw/i386/x86.h
M monitor/hmp-cmds.c
M qapi/machine.json
M qapi/qom.json
M qemu-options.hx
M softmmu/memory.c
M softmmu/physmem.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
M target/i386/kvm/kvm_i386.h
M target/i386/machine.c
M target/i386/svm.h
M target/i386/tcg/seg_helper.c
M target/i386/tcg/sysemu/excp_helper.c
M target/i386/tcg/sysemu/misc_helper.c
M target/i386/tcg/sysemu/svm_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into
staging
* SGX support (Sean, Yang)
* vGIF and vVMLOAD/VMSAVE support (Lara)
* Fix LA57 support in TCG (Daniel)
# gpg: Signature made Tue 07 Sep 2021 07:55:00 BST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (36 commits)
doc: Add the SGX doc
sgx-epc: Add the fill_device_info() callback support
Kconfig: Add CONFIG_SGX support
hostmem-epc: Make prealloc consistent with qemu cmdline during reset
sgx-epc: Avoid bios reset during sgx epc initialization
sgx-epc: Add the reset interface for sgx-epc virt device
hostmem-epc: Add the reset interface for EPC backend reset
i440fx: Add support for SGX EPC
q35: Add support for SGX EPC
i386: acpi: Add SGX EPC entry to ACPI tables
i386/pc: Add e820 entry for SGX EPC section(s)
hw/i386/pc: Account for SGX EPC sections when calculating device memory
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
Adjust min CPUID level to 0x12 when SGX is enabled
i386: Propagate SGX CPUID sub-leafs to KVM
i386: kvm: Add support for exposing PROVISIONKEY to guest
i386: Update SGX CPUID info according to hardware/KVM/user input
i386: Add feature control MSR dependency when SGX is enabled
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/f9128631fbeb...f31636a5d46e
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