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[Qemu-commits] [qemu/qemu] cd066e: tests: Remove uses of deprecated rasp
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] cd066e: tests: Remove uses of deprecated raspi2/raspi3 mac... |
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Date: |
Thu, 02 Sep 2021 00:49:11 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: cd066eea604762de484352c0a46c2f97dcfa5510
https://github.com/qemu/qemu/commit/cd066eea604762de484352c0a46c2f97dcfa5510
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M docs/devel/qgraph.rst
M tests/acceptance/boot_linux_console.py
M tests/qtest/boot-serial-test.c
M tests/qtest/libqos/arm-raspi2-machine.c
M tests/qtest/libqos/qgraph.h
M tests/qtest/libqos/qgraph_internal.h
M tests/unit/test-qgraph.c
Log Message:
-----------
tests: Remove uses of deprecated raspi2/raspi3 machine names
Commit 155e1c82ed0 deprecated the raspi2/raspi3 machine names.
Use the recommended new names: raspi2b and raspi3b.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id: 20210827060815.2384760-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 57469ed384b1f83788f0f1995af673b735f4f790
https://github.com/qemu/qemu/commit/57469ed384b1f83788f0f1995af673b735f4f790
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M hw/arm/raspi.c
Log Message:
-----------
hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases
Remove the raspi2/raspi3 machine aliases,
deprecated since commit 155e1c82ed0.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210827060815.2384760-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c0bb7d611403ba0fff050a6a065e76ab54d7ab77
https://github.com/qemu/qemu/commit/c0bb7d611403ba0fff050a6a065e76ab54d7ab77
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3_dist.c
Log Message:
-----------
hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix
QEMU load/store API (docs/devel/loads-stores.rst) uses the 'q'
suffix for 64-bit accesses. Rename the current 'll' suffix to
have the GIC dist accessors better match the rest of the codebase.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210826180704.2131949-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5dcf0d3ae2a5056b1ccdfc6e63ab18e5700d3ac8
https://github.com/qemu/qemu/commit/5dcf0d3ae2a5056b1ccdfc6e63ab18e5700d3ac8
Author: Philippe Mathieu-Daudé <philmd@redhat.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/intc/arm_gicv3_dist.c
Log Message:
-----------
hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans
Quoting Peter Maydell:
These MEMTX_* aren't from the memory transaction API functions;
they're just being used by gicd_readl() and friends as a way to
indicate a success/failure so that the actual MemoryRegionOps
read/write fns like gicv3_dist_read() can log a guest error.
Arguably this is a bit of a misuse of the MEMTX_* constants and
perhaps we should have gicd_readl etc return a bool instead.
Follow his suggestion and replace the MEMTX_* constants by
boolean values, simplifying a bit the gicv3_dist_read() /
gicv3_dist_write() handlers.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210826180704.2131949-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 52e64f5b1f2c81472b57dbad255ab9b00302f10d
https://github.com/qemu/qemu/commit/52e64f5b1f2c81472b57dbad255ab9b00302f10d
Author: Yanan Wang <wangyanan55@huawei.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/virt.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/i386/pc.h
Log Message:
-----------
hw: Add compat machines for 6.2
Add 6.2 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Yanan Wang <wangyanan55@huawei.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1e35cd916695389074b12614d254087a9f51b852
https://github.com/qemu/qemu/commit/1e35cd916695389074b12614d254087a9f51b852
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
M target/arm/translate-neon.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE VADD (floating-point)
Implement the MVE VADD (floating-point) insn. Handling of this is
similar to the 2-operand integer insns, except that we must take care
to only update the floating point exception status if the least
significant bit of the predicate mask for each element is active.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 82af0153d3a92230211b326b90f953a7e1877e29
https://github.com/qemu/qemu/commit/82af0153d3a92230211b326b90f953a7e1877e29
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM
Implement more simple 2-operand floating point MVE insns.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 104afc68cf6fbd518e202647e996a14dd0c70130
https://github.com/qemu/qemu/commit/104afc68cf6fbd518e202647e996a14dd0c70130
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCADD
Implement the MVE VCADD insn. Note that here the size bit is the
opposite sense to the other 2-operand fp insns.
We don't check for the sz == 1 && Qd == Qm UNPREDICTABLE case,
because that would mean we can't use the DO_2OP_FP macro in
translate-mve.c.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3173c0dd933cbd80578bde6aa116f8f519174a2e
https://github.com/qemu/qemu/commit/3173c0dd933cbd80578bde6aa116f8f519174a2e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VFMA and VFMS
Implement the MVE VFMA and VFMS insns.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d3cd965c846bb350637090d2d11bc578b79f87cd
https://github.com/qemu/qemu/commit/d3cd965c846bb350637090d2d11bc578b79f87cd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCMUL and VCMLA
Implement the MVE VCMUL and VCMLA insns.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 90257a4f35efef15380f45339fecc348e762acc6
https://github.com/qemu/qemu/commit/90257a4f35efef15380f45339fecc348e762acc6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VMAXNMA and VMINNMA
Implement the MVE VMAXNMA and VMINNMA insns; these are 2-operand, but
the destination register must be the same as one of the source
registers.
We defer the decode of the size in bit 28 to the individual insn
patterns rather than doing it in the format, because otherwise we
would have a single insn pattern that overlapped with two groups (eg
VMAXNMA with the VMULH_S and VMULH_U groups). Having two insn
patterns per insn seems clearer than a complex multilevel nesting
of overlapping and non-overlapping groups.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: abfe39b263595a47f42219aa3a3fc63804a12a35
https://github.com/qemu/qemu/commit/abfe39b263595a47f42219aa3a3fc63804a12a35
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE scalar fp insns
Implement the MVE scalar floating point insns VADD, VSUB and VMUL.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4773e74e5f58dbf5637a27f37cd3b95b0ee33ac8
https://github.com/qemu/qemu/commit/4773e74e5f58dbf5637a27f37cd3b95b0ee33ac8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE fp-with-scalar VFMA, VFMAS
Implement the MVE fp-with-scalar VFMA and VFMAS insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2c8cb5888e998d7ba8e36c312644a11d832dbe9c
https://github.com/qemu/qemu/commit/2c8cb5888e998d7ba8e36c312644a11d832dbe9c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M fpu/softfloat-specialize.c.inc
Log Message:
-----------
softfloat: Remove assertion preventing silencing of NaN in default-NaN mode
In commit a777d6033447a we added an assertion to parts_silence_nan() that
prohibits calling float*_silence_nan() when in default-NaN mode.
This ties together a property of the output ("do we generate a default
NaN when the result is a NaN?") with an operation on an input ("silence
this input NaN").
It's true that most of the time when in default-NaN mode you won't
need to silence an input NaN, because you can just produce the
default NaN as the result instead. But some functions like
float*_maxnum() are defined to be able to work with quiet NaNs, so
silencing an input SNaN is still reasonable. In particular, the
upcoming implementation of MVE VMAXNMV would fall over this assertion
if we didn't delete it.
Delete the assertion.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 29f80e7d831f123268fcc15c5516b06eeec5eab5
https://github.com/qemu/qemu/commit/29f80e7d831f123268fcc15c5516b06eeec5eab5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE FP max/min across vector
Implement the MVE VMAXNMV, VMINNMV, VMAXNMAV, VMINNMAV insns. These
calculate the maximum or minimum of floating point elements across a
vector, starting with a value in a general purpose register and
returning the result there.
The pseudocode silences a possible SNaN in the accumulating result
on every iteration (by calling FPConvertNaN), but we do it only
on the input ra, because if none of the inputs to float*_maxnum
or float*_minnum are SNaNs then the result can't be an SNaN.
Note that we can't use the float*_maxnuma() etc functions we defined
earlier for VMAXNMA and VMINNMA, because we mustn't take the absolute
value of the starting general-purpose register value, which could be
negative.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c87fe6d28cb08cd02288e915488fb86816ae99fe
https://github.com/qemu/qemu/commit/c87fe6d28cb08cd02288e915488fb86816ae99fe
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE fp vector comparisons
Implement the MVE fp vector comparisons VCMP and VPT.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c2d8f6bb28ffc5c9e4e465604ccdf7a08b7e3568
https://github.com/qemu/qemu/commit/c2d8f6bb28ffc5c9e4e465604ccdf7a08b7e3568
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE fp scalar comparisons
Implement the MVE fp scalar comparisons VCMP and VPT.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2a4b939cf865fe5edd0f3dccf1b4ba6c3ca8b904
https://github.com/qemu/qemu/commit/2a4b939cf865fe5edd0f3dccf1b4ba6c3ca8b904
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCVT between floating and fixed point
Implement the MVE VCVT insns which convert between floating and fixed
point. As with the Neon equivalents, these use essentially the same
constant encoding as right-shift-by-immediate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2ec0dcf034b6954eb6d0b03ae83fba015e263c27
https://github.com/qemu/qemu/commit/2ec0dcf034b6954eb6d0b03ae83fba015e263c27
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/mve.decode
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCVT between fp and integer
Implement the MVE "VCVT (between floating-point and integer)" insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 53fc5f61394927101416dc618480967dc7cd2171
https://github.com/qemu/qemu/commit/53fc5f61394927101416dc618480967dc7cd2171
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCVT with specified rounding mode
Implement the MVE VCVT which converts from floating-point to integer
using a rounding mode specified by the instruction. We implement
this similarly to the Neon equivalents, by passing the required
rounding mode as an extra integer parameter to the helper functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 73d260db3c7597c1efe7541057469358d2e5d001
https://github.com/qemu/qemu/commit/73d260db3c7597c1efe7541057469358d2e5d001
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VCVT between single and half precision
Implement the MVE VCVT instruction which converts between single
and half precision floating point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 98e40fbd792e13e98abd7f3d17f18a24edea4984
https://github.com/qemu/qemu/commit/98e40fbd792e13e98abd7f3d17f18a24edea4984
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VRINT insns
Implement the MVE VRINT insns, which round floating point inputs
to integer values, leaving them in floating point format.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d4cc1c21965b3df527cbfbae5a317a9c2ac441e5
https://github.com/qemu/qemu/commit/d4cc1c21965b3df527cbfbae5a317a9c2ac441e5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Enable MVE in Cortex-M55
We now have a complete MVE emulation, so we can enable it in our
Cortex-M55 model by setting the ID registers to match those of a
Cortex-M55 with full MVE support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e31c70ac04001df5e540b79843834277e283fa71
https://github.com/qemu/qemu/commit/e31c70ac04001df5e540b79843834277e283fa71
Author: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target-arm: Add support for Fujitsu A64FX
Add a definition for the Fujitsu A64FX processor.
The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.
For SVE, the A64FX processor supports only 128,256 and 512bit vector
lengths.
The Identification register values are defined based on the FX700,
and have been tested and confirmed.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d39fcd8af11c0395d7b5112828d65d48cf0cfae
https://github.com/qemu/qemu/commit/4d39fcd8af11c0395d7b5112828d65d48cf0cfae
Author: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: target-arm: Add A64FX processor support to virt machine
Add -cpu a64fx to use A64FX processor when -machine virt option is
specified. In addition, add a64fx to the Supported guest CPU types
in the virt.rst document.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 499243e189429d3e5a0572be14ed2f98251e38a1
https://github.com/qemu/qemu/commit/499243e189429d3e5a0572be14ed2f98251e38a1
Author: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M tests/qtest/arm-cpu-features.c
Log Message:
-----------
tests/arm-cpu-features: Add A64FX processor related tests
Add tests that the A64FX CPU model exposes the expected features.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
[PMM: added commit message body]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2f9db77ea8330db9d038603055e0543512365283
https://github.com/qemu/qemu/commit/2f9db77ea8330db9d038603055e0543512365283
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M MAINTAINERS
M hw/arm/armv7m.c
M hw/intc/armv7m_nvic.c
A hw/misc/armv7m_ras.c
M hw/misc/meson.build
M include/hw/arm/armv7m.h
M include/hw/intc/armv7m_nvic.h
A include/hw/misc/armv7m_ras.h
Log Message:
-----------
arm: Move M-profile RAS register block into its own device
Currently we implement the RAS register block within the NVIC device.
It isn't really very tightly coupled with the NVIC proper, so instead
move it out into a sysbus device of its own and have the top level
ARMv7M container create it and map it into memory at the right
address.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
Commit: e36a25cb4759b9cfc122650a720e5a968b370a46
https://github.com/qemu/qemu/commit/e36a25cb4759b9cfc122650a720e5a968b370a46
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/armv7m.c
M hw/intc/armv7m_nvic.c
M include/hw/arm/armv7m.h
M include/hw/intc/armv7m_nvic.h
Log Message:
-----------
arm: Move systick device creation from NVIC to ARMv7M object
There's no particular reason why the NVIC should be owning the
SysTick device objects; move them into the ARMv7M container object
instead, as part of consolidating the "create the devices which are
built into an M-profile CPU and map them into their architected
locations in the address space" work into one place.
This involves temporarily creating a duplicate copy of the
nvic_sysreg_ns_ops struct and its read/write functions (renamed as
v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in
a subsequent patch.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-3-peter.maydell@linaro.org
Commit: 2089c0102d6c8f5abead691e045d5d73aef717c1
https://github.com/qemu/qemu/commit/2089c0102d6c8f5abead691e045d5d73aef717c1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/armv7m.c
M hw/intc/armv7m_nvic.c
M include/hw/arm/armv7m.h
M include/hw/intc/armv7m_nvic.h
Log Message:
-----------
arm: Move system PPB container handling to armv7m
Instead of having the NVIC device provide a single sysbus memory
region covering the whole of the "System PPB" space, which implements
the default behaviour for unimplemented ranges and provides the NS
alias window to the sysregs as well as the main sysreg MR, move this
handling to the container armv7m device. The NVIC now provides a
single memory region which just implements the system registers.
This consolidates all the handling of "map various devices in the
PPB" into the armv7m container where it belongs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
Commit: feb8ef35af34fea2b508426ea210681cd354378c
https://github.com/qemu/qemu/commit/feb8ef35af34fea2b508426ea210681cd354378c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M include/hw/timer/armv7m_systick.h
Log Message:
-----------
hw/timer/armv7m_systick: Add usual QEMU interface comment
Add the usual-style QEMU interface comment documenting what
properties, etc, this device exposes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-5-peter.maydell@linaro.org
Commit: 5c6e1a1cf95f044987fe475560f296b7a4058c58
https://github.com/qemu/qemu/commit/5c6e1a1cf95f044987fe475560f296b7a4058c58
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/timer/armv7m_systick.c
M include/hw/timer/armv7m_systick.h
Log Message:
-----------
hw/timer/armv7m_systick: Add input clocks
The v7M systick timer can be programmed to run from either of
two clocks:
* an "external reference clock" (when SYST_CSR.CLKSOURCE == 0)
* the main CPU clock (when SYST_CSR.CLKSOURCE == 1)
Our implementation currently hardwires the external reference clock
to be 1MHz, and allows boards to set the main CPU clock frequency via
the global 'system_clock_scale'. (Most boards set that to a constant
value; the Stellaris boards allow the guest to reprogram it via the
board-specific RCC registers).
As the first step in converting this to use the Clock infrastructure,
add input clocks to the systick device for the reference clock and
the CPU clock. The device implementation ignores them; once we have
made all the users of the device correctly wire up the new Clocks we
will switch the implementation to use them and ignore the old
system_clock_scale.
This is a migration compat break for all M-profile boards, because of
the addition of the new clock objects to the vmstate struct.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-6-peter.maydell@linaro.org
Commit: d5093d961585f02126191951ded9b90dbc52883b
https://github.com/qemu/qemu/commit/d5093d961585f02126191951ded9b90dbc52883b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/armv7m.c
M include/hw/arm/armv7m.h
Log Message:
-----------
hw/arm/armv7m: Create input clocks
Create input clocks on the armv7m container object which pass through
to the systick timers, so that users of the armv7m object can specify
the clocks being used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-7-peter.maydell@linaro.org
Commit: 712bd17f3e6c5b33ad1e33661350164c9f8468bf
https://github.com/qemu/qemu/commit/712bd17f3e6c5b33ad1e33661350164c9f8468bf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
armsse: Wire up systick cpuclk clock
Wire up the cpuclk for the systick devices to the SSE object's
existing mainclk clock.
We do not wire up the refclk because the SSE subsystems do not
provide a refclk. (This is documented in the IoTKit and SSE-200
TRMs; the SSE-300 TRM doesn't mention it but we assume it follows the
same approach.) When we update the systick device later to honour "no
refclk connected" this will fix a minor emulation inaccuracy for the
SSE-based boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-8-peter.maydell@linaro.org
Commit: a860df4f540d438a9531c70ff4eb0995841e7202
https://github.com/qemu/qemu/commit/a860df4f540d438a9531c70ff4eb0995841e7202
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2.c: Connect up armv7m clocks
Connect up the armv7m clocks on the mps2-an385/386/500/511.
Connect up the armv7m object's clocks on the MPS boards defined in
mps2.c. The documentation for these FPGA images doesn't specify what
systick reference clock is used (if any), so for the moment we
provide a 1MHz refclock, which will result in no behavioural change
from the current hardwired 1MHz clock implemented in
armv7m_systick.c:systick_scale().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-9-peter.maydell@linaro.org
Commit: 99abcbc7600c62c294e973db340adf6939932a93
https://github.com/qemu/qemu/commit/99abcbc7600c62c294e973db340adf6939932a93
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M docs/devel/clocks.rst
M hw/core/clock-vmstate.c
M hw/core/clock.c
M hw/core/trace-events
M include/hw/clock.h
Log Message:
-----------
clock: Provide builtin multiplier/divider
It is quite common for a clock tree to involve possibly programmable
clock multipliers or dividers, where the frequency of a clock is for
instance divided by 8 to produce a slower clock to feed to a
particular device.
Currently we provide no convenient mechanism for modelling this. You
can implement it by having an input Clock and an output Clock, and
manually setting the period of the output clock in the period-changed
callback of the input clock, but that's quite clunky.
This patch adds support in the Clock objects themselves for setting a
multiplier or divider. The effect of setting this on a clock is that
when the clock's period is changed, all the children of the clock are
set to period * multiplier / divider, rather than being set to the
same period as the parent clock.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-10-peter.maydell@linaro.org
Commit: cabc613f78fc0409ed3cd35994cd85ed3a0915f1
https://github.com/qemu/qemu/commit/cabc613f78fc0409ed3cd35994cd85ed3a0915f1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stm32f100_soc.c
M hw/arm/stm32f205_soc.c
M include/hw/arm/stm32f100_soc.h
M include/hw/arm/stm32f205_soc.h
Log Message:
-----------
hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
In the realize methods of the stm32f100 and stm32f205 SoC objects, we
call g_new() to create new MemoryRegion objects for the sram, flash,
and flash_alias. This is unnecessary (and leaves open the
possibility of leaking the allocations if we exit from realize with
an error). Make these MemoryRegions member fields of the device
state struct instead, as stm32f405 already does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-11-peter.maydell@linaro.org
Commit: b5ff0c6183e0c060725becd6fdb43a08b494fdc1
https://github.com/qemu/qemu/commit/b5ff0c6183e0c060725becd6fdb43a08b494fdc1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stm32f100_soc.c
M hw/arm/stm32vldiscovery.c
M include/hw/arm/stm32f100_soc.h
Log Message:
-----------
hw/arm/stm32f100: Wire up sysclk and refclk
Wire up the sysclk and refclk for the stm32f100 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the stm32vldiscovery board where the
systick reference clock was running at 1MHz rather than 3MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-12-peter.maydell@linaro.org
Commit: 68ba05fba411a9dd7281498c7f7aae05e0b76005
https://github.com/qemu/qemu/commit/68ba05fba411a9dd7281498c7f7aae05e0b76005
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/netduino2.c
M hw/arm/stm32f205_soc.c
M include/hw/arm/stm32f205_soc.h
Log Message:
-----------
hw/arm/stm32f205: Wire up sysclk and refclk
Wire up the sysclk and refclk for the stm32f205 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the netduino2 board where the systick
reference clock was running at 1MHz rather than 15MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-13-peter.maydell@linaro.org
Commit: 66e6a43818734a2423dcfcd5bf52a33df86e89aa
https://github.com/qemu/qemu/commit/66e6a43818734a2423dcfcd5bf52a33df86e89aa
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/netduinoplus2.c
M hw/arm/stm32f405_soc.c
M include/hw/arm/stm32f405_soc.h
Log Message:
-----------
hw/arm/stm32f405: Wire up sysclk and refclk
Wire up the sysclk and refclk for the stm32f405 SoC. This SoC always
runs the systick refclk at 1/8 the frequency of the main CPU clock,
so the board code only needs to provide a single sysclk clock.
Because there is only one board using this SoC, we convert the SoC
and the board together, rather than splitting it into "add clock to
SoC; connect clock in board; add error check in SoC code that clock
is wired up".
When the systick device starts honouring its clock inputs, this will
fix an emulation inaccuracy in the netduinoplus2 board where the
systick reference clock was running at 1MHz rather than 21MHz.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-14-peter.maydell@linaro.org
Commit: 7580384b34da99134d1162729957ed63ae2da230
https://github.com/qemu/qemu/commit/7580384b34da99134d1162729957ed63ae2da230
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stm32vldiscovery.c
Log Message:
-----------
hw/arm/stm32vldiscovery: Delete trailing blank line
Delete the trailing blank line at the end of the source file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210812093356.1946-15-peter.maydell@linaro.org
Commit: c08e612662e4bdc84f2e9bd4ae598e8c07a23565
https://github.com/qemu/qemu/commit/c08e612662e4bdc84f2e9bd4ae598e8c07a23565
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/nrf51_soc.c
M include/hw/arm/nrf51_soc.h
Log Message:
-----------
hw/arm/nrf51: Wire up sysclk
Wire up the sysclk input to the armv7m object.
Strictly this SoC should not have a systick device at all, but our
armv7m container object doesn't currently support disabling the
systick device. For the moment, add a TODO comment, but note that
this is why we aren't wiring up a refclk (no need for one).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-16-peter.maydell@linaro.org
Commit: a861b3e94eb62495c0e3caac8ef2fb0ce4400a95
https://github.com/qemu/qemu/commit/a861b3e94eb62495c0e3caac8ef2fb0ce4400a95
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: split stellaris_sys_init()
Currently the stellaris_sys_init() function creates the
TYPE_STELLARIS_SYS object, sets its properties, realizes it, maps its
MMIO region and connects its IRQ. In order to support wiring the
sysclk up to the armv7m object, we need to split this function apart,
because to connect the clock output of the STELLARIS_SYS object to
the armv7m object we need to create the STELLARIS_SYS object before
the armv7m object, but we can't wire up the IRQ until after we've
created the armv7m object.
Remove the stellaris_sys_init() function, and instead put the
create/configure/realize parts before we create the armv7m object and
the mmio/irq connection parts afterwards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-17-peter.maydell@linaro.org
Commit: 8ecda75f721b0673e9ad1420198a4f4ec3ae2cb9
https://github.com/qemu/qemu/commit/8ecda75f721b0673e9ad1420198a4f4ec3ae2cb9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Wire sysclk up to armv7m
Connect the sysclk to the armv7m object. This board's SoC does not
connect up the systick reference clock, so we don't need to connect a
refclk.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-18-peter.maydell@linaro.org
Commit: a4b1e9d3f863a8dfbf28f5469dcc95a07c9ac105
https://github.com/qemu/qemu/commit/a4b1e9d3f863a8dfbf28f5469dcc95a07c9ac105
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/msf2-soc.c
M include/hw/arm/msf2-soc.h
Log Message:
-----------
hw/arm/msf2_soc: Don't allocate separate MemoryRegions
In the realize method of the msf2-soc SoC object, we call g_new() to
create new MemoryRegion objects for the nvm, nvm_alias, and sram.
This is unnecessary; make these MemoryRegions member fields of the
device state struct instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-19-peter.maydell@linaro.org
Commit: 9bfaf3754b71b72296f24f73876da67cf43c3e10
https://github.com/qemu/qemu/commit/9bfaf3754b71b72296f24f73876da67cf43c3e10
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M include/hw/arm/msf2-soc.h
Log Message:
-----------
hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
Instead of passing the MSF2 SoC an integer property specifying the
CPU clock rate, pass it a Clock instead. This lets us wire that
clock up to the armv7m object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-20-peter.maydell@linaro.org
Commit: 3b76e18520330e2a23c86d7c627c1cd4a3ed32f2
https://github.com/qemu/qemu/commit/3b76e18520330e2a23c86d7c627c1cd4a3ed32f2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/msf2-soc.c
M include/hw/arm/msf2-soc.h
Log Message:
-----------
hw/arm/msf2-soc: Wire up refclk
Wire up the refclk for the msf2 SoC. This SoC runs the refclk at a
frequency which is programmably either /4, /8, /16 or /32 of the main
CPU clock. We don't currently model the register which allows the
guest to set the divisor, so implement the refclk as a fixed /32 of
the CPU clock (which is the value of the divisor at reset).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-21-peter.maydell@linaro.org
Commit: a40e10f1dc3e0fedd12042e8dddee0a8cad5dc30
https://github.com/qemu/qemu/commit/a40e10f1dc3e0fedd12042e8dddee0a8cad5dc30
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/timer/armv7m_systick.c
Log Message:
-----------
hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
Now that all users of the systick devices wire up the clock inputs,
use those instead of the system_clock_scale and the hardwired 1MHz
value for the reference clock.
This will fix various board models where we were incorrectly
providing a 1MHz reference clock instead of some other value or
instead of providing no reference clock at all.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-22-peter.maydell@linaro.org
Commit: 0d883c540462bed9b6fa64594290edfd27cb0fc0
https://github.com/qemu/qemu/commit/0d883c540462bed9b6fa64594290edfd27cb0fc0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stellaris.c
Log Message:
-----------
hw/arm/stellaris: Fix code style issues in GPTM code
Fix the code style issues in the Stellaris general purpose timer
module code, so that when we move it to a different file in a
following patch checkpatch doesn't complain.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alexandre Iooss <erdnaxe@crans.org>
Message-id: 20210812093356.1946-23-peter.maydell@linaro.org
Commit: f3eb7557284db7d9eba8843c5705b4dc90dc6fd3
https://github.com/qemu/qemu/commit/f3eb7557284db7d9eba8843c5705b4dc90dc6fd3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/stellaris.c
M hw/timer/Kconfig
M hw/timer/meson.build
A hw/timer/stellaris-gptm.c
A include/hw/timer/stellaris-gptm.h
Log Message:
-----------
hw/arm/stellaris: Split stellaris-gptm into its own file
The implementation of the Stellaris general purpose timer module
device stellaris-gptm is currently in the same source file as the
board model. Split it out into its own source file in hw/timer.
Apart from the new file comment headers and the Kconfig and
meson.build changes, this is just code movement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-24-peter.maydell@linaro.org
Commit: d18fdd69d0e417f15a388bd7a2e3d6bd2d3672a5
https://github.com/qemu/qemu/commit/d18fdd69d0e417f15a388bd7a2e3d6bd2d3672a5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/stellaris.c
M hw/timer/stellaris-gptm.c
M include/hw/timer/stellaris-gptm.h
Log Message:
-----------
hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale
The stellaris-gptm timer currently uses system_clock_scale for one of
its timer modes where the timer runs at the CPU clock rate. Make it
use a Clock input instead.
We don't try to make the timer handle changes in the clock frequency
while the downcounter is running. This is not a change in behaviour
from the previous system_clock_scale implementation -- we will pick
up the new frequency only when the downcounter hits zero. Handling
dynamic clock changes when the counter is running would require state
that the current gptm implementation doesn't have.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Damien Hedde <damien.hedde@greensocs.com>
Message-id: 20210812093356.1946-25-peter.maydell@linaro.org
Commit: 683754c7b61f9e2ff098720ec80c9ab86c54663d
https://github.com/qemu/qemu/commit/683754c7b61f9e2ff098720ec80c9ab86c54663d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M hw/arm/armsse.c
M hw/arm/mps2.c
M hw/arm/msf2-soc.c
M hw/arm/netduino2.c
M hw/arm/netduinoplus2.c
M hw/arm/nrf51_soc.c
M hw/arm/stellaris.c
M hw/arm/stm32vldiscovery.c
M hw/timer/armv7m_systick.c
M include/hw/timer/armv7m_systick.h
Log Message:
-----------
arm: Remove system_clock_scale global
All the devices that used to use system_clock_scale have now been
converted to use Clock inputs instead, so the global is no longer
needed; remove it and all the code that sets it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210812093356.1946-26-peter.maydell@linaro.org
Commit: 079b1252e9de384385c9da910262312ec2e574c8
https://github.com/qemu/qemu/commit/079b1252e9de384385c9da910262312ec2e574c8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/about/removed-features.rst
M docs/devel/clocks.rst
M docs/devel/qgraph.rst
M docs/system/arm/virt.rst
M fpu/softfloat-specialize.c.inc
M hw/arm/Kconfig
M hw/arm/armsse.c
M hw/arm/armv7m.c
M hw/arm/mps2.c
M hw/arm/msf2-soc.c
M hw/arm/msf2-som.c
M hw/arm/netduino2.c
M hw/arm/netduinoplus2.c
M hw/arm/nrf51_soc.c
M hw/arm/raspi.c
M hw/arm/stellaris.c
M hw/arm/stm32f100_soc.c
M hw/arm/stm32f205_soc.c
M hw/arm/stm32f405_soc.c
M hw/arm/stm32vldiscovery.c
M hw/arm/virt.c
M hw/core/clock-vmstate.c
M hw/core/clock.c
M hw/core/machine.c
M hw/core/trace-events
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/intc/arm_gicv3_dist.c
M hw/intc/armv7m_nvic.c
A hw/misc/armv7m_ras.c
M hw/misc/meson.build
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M hw/timer/Kconfig
M hw/timer/armv7m_systick.c
M hw/timer/meson.build
A hw/timer/stellaris-gptm.c
M include/hw/arm/armv7m.h
M include/hw/arm/msf2-soc.h
M include/hw/arm/nrf51_soc.h
M include/hw/arm/stm32f100_soc.h
M include/hw/arm/stm32f205_soc.h
M include/hw/arm/stm32f405_soc.h
M include/hw/boards.h
M include/hw/clock.h
M include/hw/i386/pc.h
M include/hw/intc/armv7m_nvic.h
A include/hw/misc/armv7m_ras.h
M include/hw/timer/armv7m_systick.h
A include/hw/timer/stellaris-gptm.h
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
M target/arm/translate-neon.c
M target/arm/translate.h
M tests/acceptance/boot_linux_console.py
M tests/qtest/arm-cpu-features.c
M tests/qtest/boot-serial-test.c
M tests/qtest/libqos/arm-raspi2-machine.c
M tests/qtest/libqos/qgraph.h
M tests/qtest/libqos/qgraph_internal.h
M tests/unit/test-qgraph.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210901'
into staging
* Refactor M-profile systick to use Clocks instead of system_clock_scale global
* clock: Provide builtin multiplier/divider
* Add A64FX processor model
* Enable MVE emulation in Cortex-M55
* hw: Add compat machines for 6.2
* hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans
* hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases
# gpg: Signature made Wed 01 Sep 2021 11:35:57 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210901: (51 commits)
arm: Remove system_clock_scale global
hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale
hw/arm/stellaris: Split stellaris-gptm into its own file
hw/arm/stellaris: Fix code style issues in GPTM code
hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale
hw/arm/msf2-soc: Wire up refclk
hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property
hw/arm/msf2_soc: Don't allocate separate MemoryRegions
hw/arm/stellaris: Wire sysclk up to armv7m
hw/arm/stellaris: split stellaris_sys_init()
hw/arm/nrf51: Wire up sysclk
hw/arm/stm32vldiscovery: Delete trailing blank line
hw/arm/stm32f405: Wire up sysclk and refclk
hw/arm/stm32f205: Wire up sysclk and refclk
hw/arm/stm32f100: Wire up sysclk and refclk
hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize
clock: Provide builtin multiplier/divider
hw/arm/mps2.c: Connect up armv7m clocks
armsse: Wire up systick cpuclk clock
hw/arm/armv7m: Create input clocks
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/4c41a1c595e1...079b1252e9de