[Qemu-commits] [qemu/qemu] 46b3e2: hw/char: Add config for shakti uart

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[Qemu-commits] [qemu/qemu] 46b3e2: hw/char: Add config for shakti uart

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 46b3e2: hw/char: Add config for shakti uart
Date:	Wed, 01 Sep 2021 02:56:57 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 46b3e2548bd49f9bc8866bf5e20f74c86948cefc
      
https://github.com/qemu/qemu/commit/46b3e2548bd49f9bc8866bf5e20f74c86948cefc
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/char/Kconfig
    M hw/char/meson.build
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/char: Add config for shakti uart

Use a dedicated UART config(CONFIG_SHAKTI_UART) to select
shakti uart.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210731190229.137483-1-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 58bde469ba0208497eea49650df7e9f832875e56
      
https://github.com/qemu/qemu/commit/58bde469ba0208497eea49650df7e9f832875e56
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Move flash node to root

The flash is not inside the SoC, so it's inappropriate to put it
under the /soc node. Move it to root instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210807035641.22449-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 65e728a28aa6c9df62711e2ece09f142b97825a6
      
https://github.com/qemu/qemu/commit/65e728a28aa6c9df62711e2ece09f142b97825a6
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Correct a comment in riscv_csrrw()

When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned,
not -1 (RISCV_EXCP_NONE).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a8b37120d459a7fdd353f08e9ccb75178086c6cc
      
https://github.com/qemu/qemu/commit/a8b37120d459a7fdd353f08e9ccb75178086c6cc
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Don't wrongly override isa version

For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210811144612.68674-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 42109837b521e3a1f93e38f5058126a85ebc7f9f
      
https://github.com/qemu/qemu/commit/42109837b521e3a1f93e38f5058126a85ebc7f9f
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add User CSRs read-only check

For U-mode CSRs, read-only check is also needed.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210810014552.4884-1-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 33fcedfac8af376afad478f029cebb9ddb09f74a
      
https://github.com/qemu/qemu/commit/33fcedfac8af376afad478f029cebb9ddb09f74a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv/virt.c: Assemble plic_hart_config string with g_strjoinv()

In the riscv virt machine init function, We assemble a string
plic_hart_config which is a comma-separated list of N copies of the
VIRT_PLIC_HART_CONFIG string.  The code that does this has a
misunderstanding of the strncat() length argument.  If the source
string is too large strncat() will write a maximum of length+1 bytes
(length bytes from the source string plus a trailing NUL), but the
code here assumes that it will write only length bytes at most.

This isn't an actual bug because the code has correctly precalculated
the amount of memory it needs to allocate so that it will never be
too small (i.e.  we could have used plain old strcat()), but it does
mean that the code looks like it has a guard against accidental
overrun when it doesn't.

Rewrite the string handling here to use the glib g_strjoinv()
function, which means we don't need to do careful accountancy of
string lengths, and makes it clearer that what we're doing is
"create a comma-separated string".

Fixes: Coverity 1460752
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210812144647.10516-1-peter.maydell@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4dc06bb8167fb18b8eb7e40762a94dcc36101047
      
https://github.com/qemu/qemu/commit/4dc06bb8167fb18b8eb7e40762a94dcc36101047
  Author: David Hoppenbrouwers <david@salt-inc.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/intc/sifive_clint.c

  Log Message:
  -----------
  hw/intc/sifive_clint: Fix muldiv64 overflow in sifive_clint_write_timecmp()

`muldiv64` would overflow in cases where the final 96-bit value does not
fit in a `uint64_t`. This would result in small values that cause an
interrupt to be triggered much sooner than intended.

The overflow can be detected in most cases by checking if the new value is
smaller than the previous value. If the final result is larger than
`diff` it is either correct or it doesn't matter as it is effectively
infinite anyways.

`next` is an `uint64_t` value, but `timer_mod` takes an `int64_t`. This
resulted in high values such as `UINT64_MAX` being converted to `-1`,
which caused an immediate timer interrupt.

By limiting `next` to `INT64_MAX` no overflow will happen while the
timer will still be effectively set to "infinitely" far in the future.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/493
Signed-off-by: David Hoppenbrouwers <david@salt-inc.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210827152324.5201-1-david@salt-inc.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4d63ef20cf970901be1d6dd98743a4851e48f938
      
https://github.com/qemu/qemu/commit/4d63ef20cf970901be1d6dd98743a4851e48f938
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/core/register.c
    M include/hw/register.h
    M include/hw/registerfields.h

  Log Message:
  -----------
  hw/core/register: Add more 64-bit utilities

We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-2-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2a4b4089305daf98a42f165111474ae3e92d5f1f
      
https://github.com/qemu/qemu/commit/2a4b4089305daf98a42f165111474ae3e92d5f1f
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M include/hw/registerfields.h

  Log Message:
  -----------
  hw/registerfields: Use 64-bit bitfield for FIELD_DP64

If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1626805903-162860-3-git-send-email-joe.komlodi@xilinx.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 05b80ed0a17201858a924f1bfc21508930e13073
      
https://github.com/qemu/qemu/commit/05b80ed0a17201858a924f1bfc21508930e13073
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use tcg_constant_*

Replace uses of tcg_const_* with the allocate and free close together.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-2-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9b17ae9c6a143caebdbb9a0c0b2ba66bae900f56
      
https://github.com/qemu/qemu/commit/9b17ae9c6a143caebdbb9a0c0b2ba66bae900f56
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    A tests/tcg/riscv64/Makefile.target
    A tests/tcg/riscv64/test-div.c

  Log Message:
  -----------
  tests/tcg/riscv64: Add test for division

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-3-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4a083b563a2c1bfed9c2b9dc5267d149ea109bde
      
https://github.com/qemu/qemu/commit/4a083b563a2c1bfed9c2b9dc5267d149ea109bde
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Clean up division helpers

Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2.  Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.

Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 867c81968a72e2250604963ea8cacf47c434651f
      
https://github.com/qemu/qemu/commit/867c81968a72e2250604963ea8cacf47c434651f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr

We will require the context to handle RV64 word operations.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ecda15d137457ebed937dc209f4bad2e7f36b4e4
      
https://github.com/qemu/qemu/commit/ecda15d137457ebed937dc209f4bad2e7f36b4e4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Introduce DisasExtend and new helpers

Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
tcg globals into temps, returning a constant 0 for $zero as source and
a new temp for $zero as destination.

Introduce ctx->w for simplifying word operations, such as addw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 191d1dafae9cd502ef2d771f9e35c221815fe7ba
      
https://github.com/qemu/qemu/commit/191d1dafae9cd502ef2d771f9e35c221815fe7ba
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add DisasExtend to gen_arith*

Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.

Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-7-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: afbbec820149299943976ef8b957a37073f3a0b5
      
https://github.com/qemu/qemu/commit/afbbec820149299943976ef8b957a37073f3a0b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove gen_arith_div*

Use ctx->w and the enhanced gen_arith function.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-8-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8a1b4917c576abf61c27cc74cb7cd28df3697c7c
      
https://github.com/qemu/qemu/commit/8a1b4917c576abf61c27cc74cb7cd28df3697c7c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvm.c.inc

  Log Message:
  -----------
  target/riscv: Use gen_arith for mulh and mulhu

Split out gen_mulh and gen_mulhu and use the common helper.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-9-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b66a0585f033a5505f1da2f624966b4fce40cddb
      
https://github.com/qemu/qemu/commit/b66a0585f033a5505f1da2f624966b4fce40cddb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Move gen_* helpers for RVM

Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f84ed8c2dffd938befc882cf5d347b57c4ee616f
      
https://github.com/qemu/qemu/commit/f84ed8c2dffd938befc882cf5d347b57c4ee616f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Move gen_* helpers for RVB

Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-11-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 609039150504306a33cd7abf091fd125019bda9d
      
https://github.com/qemu/qemu/commit/609039150504306a33cd7abf091fd125019bda9d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Add DisasExtend to gen_unary

Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 89c883091f257d5c2b46f9a5b6ea975b75f41301
      
https://github.com/qemu/qemu/commit/89c883091f257d5c2b46f9a5b6ea975b75f41301
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use DisasExtend in shift operations

These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift.  Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 23c108868943f9315be0bb675f6cd4dac7295b99
      
https://github.com/qemu/qemu/commit/23c108868943f9315be0bb675f6cd4dac7295b99
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.c.inc

  Log Message:
  -----------
  target/riscv: Use extracts for sraiw and srliw

These operations can be done in one instruction on some hosts.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9b21b64345c91ca71c7c33ac7caffd8804ae32cb
      
https://github.com/qemu/qemu/commit/9b21b64345c91ca71c7c33ac7caffd8804ae32cb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.c.inc

  Log Message:
  -----------
  target/riscv: Use get_gpr in branches

Narrow the scope of t0 in trans_jalr.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6ecf39e2dd854ff7ea21c365165c1957061263bb
      
https://github.com/qemu/qemu/commit/6ecf39e2dd854ff7ea21c365165c1957061263bb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.c.inc

  Log Message:
  -----------
  target/riscv: Use {get, dest}_gpr for integer load/store

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-16-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 33979526cad412b72afd1989a22dcd218b2ce170
      
https://github.com/qemu/qemu/commit/33979526cad412b72afd1989a22dcd218b2ce170
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation

We distinguish write-only by passing ret_value as NULL.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-17-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 377cbb4bdbe2ee4155d740bf1d7fc9a081a61219
      
https://github.com/qemu/qemu/commit/377cbb4bdbe2ee4155d740bf1d7fc9a081a61219
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix hgeie, hgeip

We failed to write into *val for these read functions;
replace them with read_zero.  Only warn about unsupported
non-zero value when writing a non-zero value.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-18-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a974879b4581b58369a1e5e01d8ce6736764c679
      
https://github.com/qemu/qemu/commit/a974879b4581b58369a1e5e01d8ce6736764c679
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/helper.h
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Reorg csr instructions

Introduce csrr and csrw helpers, for read-only and write-only insns.

Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
exception for read-only registers.

Only issue gen_io_start for CF_USE_ICOUNT.
Use ctx->zero for csrrc.
Use get_gpr and dest_gpr.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-19-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cce762a75e2cd9d9f121949c68f04ab8fabcdd3a
      
https://github.com/qemu/qemu/commit/cce762a75e2cd9d9f121949c68f04ab8fabcdd3a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rva.c.inc

  Log Message:
  -----------
  target/riscv: Use {get,dest}_gpr for RVA

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-20-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6922eee6acc09720883653246daa16e7dc4e2d3c
      
https://github.com/qemu/qemu/commit/6922eee6acc09720883653246daa16e7dc4e2d3c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvb.c.inc

  Log Message:
  -----------
  target/riscv: Use gen_shift_imm_fn for slli_uw

Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-21-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 75234a284316610c55749962b302a6ef46c0f745
      
https://github.com/qemu/qemu/commit/75234a284316610c55749962b302a6ef46c0f745
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvf.c.inc

  Log Message:
  -----------
  target/riscv: Use {get,dest}_gpr for RVF

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-22-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7976837f9a1faa80a7b0eb12d2b8209b596fb3e2
      
https://github.com/qemu/qemu/commit/7976837f9a1faa80a7b0eb12d2b8209b596fb3e2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvd.c.inc

  Log Message:
  -----------
  target/riscv: Use {get,dest}_gpr for RVD

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-23-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: f33960df5b377ba4b6b673f5e239402395fab6e3
      
https://github.com/qemu/qemu/commit/f33960df5b377ba4b6b673f5e239402395fab6e3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rvh.c.inc

  Log Message:
  -----------
  target/riscv: Tidy trans_rvh.c.inc

Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-24-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8e034ae44dba6291beb07f7f2a932c1e5ab83e98
      
https://github.com/qemu/qemu/commit/8e034ae44dba6291beb07f7f2a932c1e5ab83e98
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use {get,dest}_gpr for RVV

Remove gen_get_gpr, as the function becomes unused.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210823195529.560295-25-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ec397e90d21269037280633b6058d1f280e27667
      
https://github.com/qemu/qemu/commit/ec397e90d21269037280633b6058d1f280e27667
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-09-01 (Wed, 01 Sep 2021)

  Changed paths:
    M hw/char/Kconfig
    M hw/char/meson.build
    M hw/core/register.c
    M hw/intc/sifive_clint.c
    M hw/riscv/Kconfig
    M hw/riscv/virt.c
    M include/hw/register.h
    M include/hw/registerfields.h
    M target/riscv/cpu.c
    M target/riscv/csr.c
    M target/riscv/helper.h
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvb.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/op_helper.c
    M target/riscv/translate.c
    A tests/tcg/riscv64/Makefile.target
    A tests/tcg/riscv64/test-div.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210901-2' into staging

First RISC-V PR for QEMU 6.2

 - Add a config for Shakti UART
 - Fixup virt flash node
 - Don't override users supplied ISA version
 - Fixup some CSR accesses
 - Use g_strjoinv() for virt machine PLIC string config
 - Fix an overflow in the SiFive CLINT
 - Add 64-bit register access helpers
 - Replace tcg_const_* with direct constant usage

# gpg: Signature made Wed 01 Sep 2021 03:08:48 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210901-2: (33 commits)
  target/riscv: Use {get,dest}_gpr for RVV
  target/riscv: Tidy trans_rvh.c.inc
  target/riscv: Use {get,dest}_gpr for RVD
  target/riscv: Use {get,dest}_gpr for RVF
  target/riscv: Use gen_shift_imm_fn for slli_uw
  target/riscv: Use {get,dest}_gpr for RVA
  target/riscv: Reorg csr instructions
  target/riscv: Fix hgeie, hgeip
  target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
  target/riscv: Use {get, dest}_gpr for integer load/store
  target/riscv: Use get_gpr in branches
  target/riscv: Use extracts for sraiw and srliw
  target/riscv: Use DisasExtend in shift operations
  target/riscv: Add DisasExtend to gen_unary
  target/riscv: Move gen_* helpers for RVB
  target/riscv: Move gen_* helpers for RVM
  target/riscv: Use gen_arith for mulh and mulhu
  target/riscv: Remove gen_arith_div*
  target/riscv: Add DisasExtend to gen_arith*
  target/riscv: Introduce DisasExtend and new helpers
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d52dff5d8048...ec397e90d212
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