[Qemu-commits] [qemu/qemu] 585edb: xive: Remove extra '0x' prefix in tra

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[Qemu-commits] [qemu/qemu] 585edb: xive: Remove extra '0x' prefix in tra

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 585edb: xive: Remove extra '0x' prefix in trace events
Date:	Fri, 27 Aug 2021 03:39:47 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 585edbb0a1eaaf950ea276d47dbc81cff1869620
      
https://github.com/qemu/qemu/commit/585edbb0a1eaaf950ea276d47dbc81cff1869620
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/intc/trace-events

  Log Message:
  -----------
  xive: Remove extra '0x' prefix in trace events

Cc: thuth@redhat.com
Fixes: 4e960974d4ee ("xive: Add trace events")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/519
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809085227.288523-1-clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: a4e4c4b45f39082f581e8bf71fb1cb06bdb8a4c6
      
https://github.com/qemu/qemu/commit/a4e4c4b45f39082f581e8bf71fb1cb06bdb8a4c6
  Author: David Gibson <david@gibson.dropbear.id.au>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree

This uses g_autofree to simplify logic in spapr_phb_vfio_get_loc_code(),
in the process fixing a leak in one of the paths.  I'm told this fixes
Coverity error CID 1460454

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Fixes: 16b0ea1d852 ("spapr_pci: populate ibm,loc-code")
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 5118ebe8396d2b98217b3d4719e3a420dfb0a929
      
https://github.com/qemu/qemu/commit/5118ebe8396d2b98217b3d4719e3a420dfb0a929
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/internal.h
    M target/ppc/meson.build
    A target/ppc/mmu_common.c
    M target/ppc/mmu_helper.c

  Log Message:
  -----------
  target/ppc: divided mmu_helper.c in 2 files

Divided mmu_helper.c in 2 files, functions inside #ifdef CONFIG_SOFTMMU
stayed in mmu_helper.c, other functions moved to mmu_common.c. Updated
meson.build to compile mmu_common.c and only compile mmu_helper.c when
CONFIG_TCG is set.
Moved function declarations, #define and structs used by both files to
internal.h except for functions that use structures defined in cpu.h,
those were moved to cpu.h.

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20210723175627.72847-2-lucas.araujo@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: d6ae8ec6ef2635e521e89fc8708b84245cf00013
      
https://github.com/qemu/qemu/commit/d6ae8ec6ef2635e521e89fc8708b84245cf00013
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/cpu.c
    M target/ppc/mmu_common.c

  Log Message:
  -----------
  target/ppc: moved ppc_store_sdr1 to mmu_common.c

ppc_store_sdr1 was at first in mmu_helper.c and was moved as part
the patches to enable the disable-tcg option, now it's being moved
back to a file that will be compiled with that option

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20210723175627.72847-3-lucas.araujo@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: c06ba89293adc95612bc8ece74c09dce6b402cd1
      
https://github.com/qemu/qemu/commit/c06ba89293adc95612bc8ece74c09dce6b402cd1
  Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/helper_regs.c
    M target/ppc/mmu_common.c

  Log Message:
  -----------
  target/ppc: moved store_40x_sler to helper_regs.c

moved store_40x_sler from mmu_common.c to helper_regs.c as it is
a function to store a value in a special purpose register, so
moving it to a file focused in special register manipulation
is more appropriate.

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20210723175627.72847-4-lucas.araujo@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 1d76437b45ab9982307b95d325d627f7b6f06088
      
https://github.com/qemu/qemu/commit/1d76437b45ab9982307b95d325d627f7b6f06088
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M pc-bios/skiboot.lid
    M roms/skiboot

  Log Message:
  -----------
  ppc/pnv: update skiboot to commit 820d43c0a775.

It includes support for the POWER10 processor and the QEMU platform.

Built from submodule.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210806180040.156999-1-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 363fd548abd5fbef040ee001c6694672bfb0d798
      
https://github.com/qemu/qemu/commit/363fd548abd5fbef040ee001c6694672bfb0d798
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/cpu-models.c
    M target/ppc/cpu-models.h
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  ppc: Add a POWER10 DD2 CPU

The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have
HAIL but since it does not break the modeling and that we don't plan
to support DD1, modify the LPCR mask of all the POWER10 family.

Setting the HAIL bit is a requirement to support the scv instruction
on PowerNV POWER10 platforms since glibc-2.33.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-2-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 6bc8c046485463d9fb513a4a6bcc31460e6e8ba6
      
https://github.com/qemu/qemu/commit/6bc8c046485463d9fb513a4a6bcc31460e6e8ba6
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Change the POWER10 machine to support DD2 only

There is no need to keep the DD1 chip model as it will never be
publicly available.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-3-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: c944a3ba7bae52512a8cb781a2e3ffe8c678fc9c
      
https://github.com/qemu/qemu/commit/c944a3ba7bae52512a8cb781a2e3ffe8c678fc9c
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/excp_helper.c

  Log Message:
  -----------
  ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering 
power-saving mode

The Hypervisor Decrementer exception should not be generated while the
CPU is in power-saving mode (see cpu_ppc_hdecr_excp()). However,
discarding the exception before entering the power-saving mode is
wrong since we would loose a previously generated HDEC.

Fixes: 4b236b621bf0 ("ppc: Initial HDEC support")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-4-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: ab17a3fe7454c61d358b5fd47c05336687b78690
      
https://github.com/qemu/qemu/commit/ab17a3fe7454c61d358b5fd47c05336687b78690
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/ppc/pnv.c
    M include/hw/ppc/pnv.h

  Log Message:
  -----------
  ppc/pnv: Use a simple incrementing index for the chip-id

When the QEMU PowerNV machine was introduced, multi chip support
modeled a two socket system with dual chip modules as found on some P8
Tuleta systems (8286-42A). But this is hardly used and not relevant
for QEMU. Use a simple index instead.

With this change, we can now increase the max socket number to 16 as
found on high end systems.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-5-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 458c6f0180de9978c6e88b6afef19be2214b01d7
      
https://github.com/qemu/qemu/commit/458c6f0180de9978c6e88b6afef19be2214b01d7
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/ppc/pnv.c

  Log Message:
  -----------
  ppc/pnv: Distribute RAM among the chips

But always give the first 1GB to chip 0 as skiboot requires it.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-6-clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 379090306cbb9202375dbb66fb3415e82f46ed2f
      
https://github.com/qemu/qemu/commit/379090306cbb9202375dbb66fb3415e82f46ed2f
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/ppc/pnv_xscom.c

  Log Message:
  -----------
  ppc/pnv: add a chip topology index for POWER10

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-7-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: fb8dc327f4647ca49292b50b75d3304cbcb66723
      
https://github.com/qemu/qemu/commit/fb8dc327f4647ca49292b50b75d3304cbcb66723
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/xive.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  ppc/xive: Export PQ get/set routines

These will be shared with the XIVE2 router.

Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-8-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: dd4e4d1296a4aeb2fccbc1019027133f1beabf82
      
https://github.com/qemu/qemu/commit/dd4e4d1296a4aeb2fccbc1019027133f1beabf82
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/intc/xive.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  ppc/xive: Export xive_presenter_notify()

It's generic enough to be used from the XIVE2 router and avoid more
duplication.

Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210809134547.689560-9-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 181b0c333d1fb278fe72df67e9d35558fcdf3623
      
https://github.com/qemu/qemu/commit/181b0c333d1fb278fe72df67e9d35558fcdf3623
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M include/qemu/int128.h

  Log Message:
  -----------
  include/qemu/int128.h: define struct Int128 according to the host endianness

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826141446.2488609-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: f297c4c605e5f4412d12c4d7241df62326f47542
      
https://github.com/qemu/qemu/commit/f297c4c605e5f4412d12c4d7241df62326f47542
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: fix vextu[bhw][lr]x helpers

These helpers shouldn't depend on the host endianness, as they only use
shifts, ands, and int128_* methods.

Fixes: 60caf2216bf0 ("target-ppc: add vextu[bhw][lr]x instructions")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826141446.2488609-3-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 2484cd9c777f6877b178901bcb26663c411fc231
      
https://github.com/qemu/qemu/commit/2484cd9c777f6877b178901bcb26663c411fc231
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M include/qemu/int128.h

  Log Message:
  -----------
  include/qemu/int128.h: introduce bswap128s

Changes the current bswap128 implementation to use __builtin_bswap128
when available, adds a bswap128 implementation for !CONFIG_INT128
builds, and introduces bswap128s based on bswap128.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826145656.2507213-2-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 0ff16b6b78831240c39cfaaeab1f22ae52c84b09
      
https://github.com/qemu/qemu/commit/0ff16b6b78831240c39cfaaeab1f22ae52c84b09
  Author: Matheus Ferst <matheus.ferst@eldorado.org.br>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M target/ppc/gdbstub.c

  Log Message:
  -----------
  target/ppc: fix vector registers access in gdbstub for little-endian

As vector registers are stored in host endianness, we shouldn't swap its
64-bit elements in user mode. Add a 16-byte case in
ppc_maybe_bswap_register to handle the reordering of elements in softmmu
and remove avr_need_swap which is now unused.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826145656.2507213-3-matheus.ferst@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: ad22d0583300df420819e6c89b1c022b998fac8a
      
https://github.com/qemu/qemu/commit/ad22d0583300df420819e6c89b1c022b998fac8a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M hw/intc/spapr_xive_kvm.c
    M hw/intc/trace-events
    M hw/intc/xive.c
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/pnv_xscom.c
    M hw/ppc/spapr_pci.c
    M include/hw/ppc/pnv.h
    M include/hw/ppc/xive.h
    M include/qemu/int128.h
    M pc-bios/skiboot.lid
    M roms/skiboot
    M target/ppc/cpu-models.c
    M target/ppc/cpu-models.h
    M target/ppc/cpu.c
    M target/ppc/cpu.h
    M target/ppc/cpu_init.c
    M target/ppc/excp_helper.c
    M target/ppc/gdbstub.c
    M target/ppc/helper_regs.c
    M target/ppc/int_helper.c
    M target/ppc/internal.h
    M target/ppc/meson.build
    A target/ppc/mmu_common.c
    M target/ppc/mmu_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' 
into staging

ppc patch queue 2021-08-27

First ppc pull request for qemu-6.2.  As usual, there's a fair bit
here, since it's been queued during the 6.1 freeze.  Highlights are:

 * Some fixes for 128 bit arithmetic and some vector opcodes that use
   them
 * Significant improvements to the powernv to support POWER10 cpus
   (more to come though)
 * Several cleanups to the ppc softmmu code
 * A few other assorted fixes

# gpg: Signature made Fri 27 Aug 2021 08:09:12 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" 
[full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dg-gitlab/tags/ppc-for-6.2-20210827:
  target/ppc: fix vector registers access in gdbstub for little-endian
  include/qemu/int128.h: introduce bswap128s
  target/ppc: fix vextu[bhw][lr]x helpers
  include/qemu/int128.h: define struct Int128 according to the host endianness
  ppc/xive: Export xive_presenter_notify()
  ppc/xive: Export PQ get/set routines
  ppc/pnv: add a chip topology index for POWER10
  ppc/pnv: Distribute RAM among the chips
  ppc/pnv: Use a simple incrementing index for the chip-id
  ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering 
power-saving mode
  ppc/pnv: Change the POWER10 machine to support DD2 only
  ppc: Add a POWER10 DD2 CPU
  ppc/pnv: update skiboot to commit 820d43c0a775.
  target/ppc: moved store_40x_sler to helper_regs.c
  target/ppc: moved ppc_store_sdr1 to mmu_common.c
  target/ppc: divided mmu_helper.c in 2 files
  spapr_pci: Fix leak in spapr_phb_vfio_get_loc_code() with g_autofree
  xive: Remove extra '0x' prefix in trace events

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/0289f62335b2...ad22d0583300
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