[Qemu-commits] [qemu/qemu] 9dacf0: target/arm: Note that we handle VMOVL as a special...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9dacf0764b506a67f33dd63bdf48fc273c0bdb7f
      
https://github.com/qemu/qemu/commit/9dacf0764b506a67f33dd63bdf48fc273c0bdb7f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve.decode

  Log Message:
  -----------
  target/arm: Note that we handle VMOVL as a special case of VSHLL

Although the architecture doesn't define it as an alias, VMOVL
(vector move long) is encoded as a VSHLL with a zero shift.
Add a comment in the decode file noting that we handle VMOVL
as part of VSHLL.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: aa29190826f2f061ed3ffad0a6cabb30eaf7f8f0
      
https://github.com/qemu/qemu/commit/aa29190826f2f061ed3ffad0a6cabb30eaf7f8f0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Print MVE VPR in CPU dumps

Include the MVE VPR register value in the CPU dumps produced by
arm_cpu_dump_state() if we are printing FPU information. This
makes it easier to interpret debug logs when predication is
active.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c88ff88498ea95e78d5fbd192de5123c1d88f9a8
      
https://github.com/qemu/qemu/commit/c88ff88498ea95e78d5fbd192de5123c1d88f9a8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix MVE VSLI by 0 and VSRI by <dt>

In the MVE shift-and-insert insns, we special case VSLI by 0
and VSRI by <dt>. VSRI by <dt> means "don't update the destination",
which is what we've implemented. However VSLI by 0 is "set
destination to the input", so we don't want to use the same
special-casing that we do for VSRI by <dt>.

Since the generic logic gives the right answer for a shift
by 0, just use that.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ed5a59d61f1619f4015a7a02f72e3590528008b4
      
https://github.com/qemu/qemu/commit/ed5a59d61f1619f4015a7a02f72e3590528008b4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix signed VADDV

A cut-and-paste error meant we handled signed VADDV like
unsigned VADDV; fix the type used.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a5e59e8dcbbf7b1205370b3f4519749df5d0b726
      
https://github.com/qemu/qemu/commit/a5e59e8dcbbf7b1205370b3f4519749df5d0b726
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix mask handling for MVE narrowing operations

In the MVE helpers for the narrowing operations (DO_VSHRN and
DO_VSHRN_SAT) we were using the wrong bits of the predicate mask for
the 'top' versions of the insn.  This is because the loop works over
the double-sized input elements and shifts the predicate mask by that
many bits each time, but when we write out the half-sized output we
must look at the mask bits for whichever half of the element we are
writing to.

Correct this by shifting the whole mask right by ESIZE bits for the
'top' insns.  This allows us also to simplify the saturation bit
checking (where we had noticed that we needed to look at a different
mask bit for the 'top' insn.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 95351aa76c8f68564c4be547c1d19d9cabffc147
      
https://github.com/qemu/qemu/commit/95351aa76c8f68564c4be547c1d19d9cabffc147
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix 48-bit saturating shifts

In do_sqrshl48_d() and do_uqrshl48_d() we got some of the edge
cases wrong and failed to saturate correctly:

(1) In do_sqrshl48_d() we used the same code that do_shrshl_bhs()
does to obtain the saturated most-negative and most-positive 48-bit
signed values for the large-shift-left case.  This gives (1 << 47)
for saturate-to-most-negative, but we weren't sign-extending this
value to the 64-bit output as the pseudocode requires.

(2) For left shifts by less than 48, we copied the "8/16 bit" code
from do_sqrshl_bhs() and do_uqrshl_bhs().  This doesn't do the right
thing because it assumes the C type we're working with is at least
twice the number of bits we're saturating to (so that a shift left by
bits-1 can't shift anything off the top of the value).  This isn't
true for bits == 48, so we would incorrectly return 0 rather than the
most-positive value for situations like "shift (1 << 44) right by
20".  Instead check for saturation by doing the shift and signextend
and then testing whether shifting back left again gives the original
value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fdcf2269c4e0e4f5ca3a389290a71d7aa98bd5c7
      
https://github.com/qemu/qemu/commit/fdcf2269c4e0e4f5ca3a389290a71d7aa98bd5c7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix MVE 48-bit SQRSHRL for small right shifts

We got an edge case wrong in the 48-bit SQRSHRL implementation: if
the shift is to the right, although it always makes the result
smaller than the input value it might not be within the 48-bit range
the result is supposed to be if the input had some bits in [63..48]
set and the shift didn't bring all of those within the [47..0] range.

Handle this similarly to the way we already do for this case in
do_uqrshl48_d(): extend the calculated result from 48 bits,
and return that if not saturating or if it doesn't change the
result; otherwise fall through to return a saturated value.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3f4f1880c245453b75d4c09049845b19de9964bf
      
https://github.com/qemu/qemu/commit/3f4f1880c245453b75d4c09049845b19de9964bf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix calculation of LTP mask when LR is 0

In mve_element_mask(), we calculate a mask for tail predication which
should have a number of 1 bits based on the value of LR.  However,
our MAKE_64BIT_MASK() macro has undefined behaviour when passed a
zero length.  Special case this to give the all-zeroes mask we
require.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e0d40070e1b3b6cf16ad2a51e85fb92261363d2a
      
https://github.com/qemu/qemu/commit/e0d40070e1b3b6cf16ad2a51e85fb92261363d2a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Factor out mve_eci_mask()

In some situations we need a mask telling us which parts of the
vector correspond to beats that are not being executed because of
ECI, separately from the combined "which bytes are predicated away"
mask.  Factor this mask calculation out of mve_element_mask() into
its own function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e3152d02da21ac6e2169b1bf104a2d0478664a4a
      
https://github.com/qemu/qemu/commit/e3152d02da21ac6e2169b1bf104a2d0478664a4a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VPT advance when ECI is non-zero

We were not paying attention to the ECI state when advancing the VPT
state.  Architecturally, VPT state advance happens for every beat
(see the pseudocode VPTAdvance()), so on every beat the 4 bits of
VPR.P0 corresponding to the current beat are inverted if required,
and at the end of beats 1 and 3 the VPR MASK fields are updated.
This means that if the ECI state says we should not be executing all
4 beats then we need to skip some of the updating of the VPR that we
currently do in mve_advance_vpt().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 41704cc262d6f451470c2074560bc7309064865d
      
https://github.com/qemu/qemu/commit/41704cc262d6f451470c2074560bc7309064865d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve_helper.c

  Log Message:
  -----------
  target/arm: Fix VLDRB/H/W for predicated elements

For vector loads, predicated elements are zeroed, instead of
retaining their previous values (as happens for most data
processing operations). This means we need to distinguish
"beat not executed due to ECI" (don't touch destination
element) from "beat executed but predicated out" (zero
destination element).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c1bd78cb06afb37e4043d2b0db000abfecab5fe4
      
https://github.com/qemu/qemu/commit/c1bd78cb06afb37e4043d2b0db000abfecab5fe4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement MVE VMULL (polynomial)

Implement the MVE VMULL (polynomial) insn.  Unlike Neon, this comes
in two flavours: 8x8->16 and a 16x16->32.  Also unlike Neon, the
inputs are in either the low or the high half of each double-width
element.

The assembler for this insn indicates the size with "P8" or "P16",
encoded into bit 28 as size = 0 or 1. We choose to follow the
same encoding as VQDMULL and decode this into a->size as MO_16
or MO_32 indicating the size of the result elements. This then
carries through to the helper function names where it then
matches up with the existing pmull_h() which does an 8x8->16
operation and a new pmull_w() which does the 16x16->32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 395b92d50ee2b62b662d5524a61c532a2752336c
      
https://github.com/qemu/qemu/commit/395b92d50ee2b62b662d5524a61c532a2752336c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE incrementing/decrementing dup insns

Implement the MVE incrementing/decrementing dup insns VIDUP, VDDUP,
VIWDUP and VDWDUP.  These fill the elements of a vector with
successively incrementing values, starting at the offset specified in
a general purpose register.  The final value of the offset is written
back to this register.  The wrapping variants take a second general
purpose register which specifies the point where the count should
wrap back to 0.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 552517861c6553941e8bfbbafbf97b6a6d992636
      
https://github.com/qemu/qemu/commit/552517861c6553941e8bfbbafbf97b6a6d992636
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Factor out gen_vpst()

Factor out the "generate code to update VPR.MASK01/MASK23" part of
trans_VPST(); we are going to want to reuse it for the VPT insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eff5d9a9bdbabfb1ccdb62c1c61311a575b11e9c
      
https://github.com/qemu/qemu/commit/eff5d9a9bdbabfb1ccdb62c1c61311a575b11e9c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE integer vector comparisons

Implement the MVE integer vector comparison instructions.  These are
"VCMP (vector)" encodings T1, T2 and T3, and "VPT (vector)" encodings
T1, T2 and T3.

These insns compare corresponding elements in each vector, and update
the VPR.P0 predicate bits with the results of the comparison.  VPT
also sets the VPR.MASK01 and VPR.MASK23 fields -- it is effectively
"VCMP then VPST".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cce81873bcc163a86488deec1e122c303c6762a4
      
https://github.com/qemu/qemu/commit/cce81873bcc163a86488deec1e122c303c6762a4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE integer vector-vs-scalar comparisons

Implement the MVE integer vector comparison instructions that compare
each element against a scalar from a general purpose register.  These
are "VCMP (vector)" encodings T4, T5 and T6 and "VPT (vector)"
encodings T4, T5 and T6.

We have to move the decodetree pattern for VPST, because it
overlaps with VCMP T4 with size = 0b11.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c386443b163965e44ae7a7f7858ec7985e97926b
      
https://github.com/qemu/qemu/commit/c386443b163965e44ae7a7f7858ec7985e97926b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VPSEL

Implement the MVE VPSEL insn, which sets each byte of the destination
vector Qd to the byte from either Qn or Qm depending on the value of
the corresponding bit in VPR.P0.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6b895bf8fb088a04a91714a555d2b6234cf1e98d
      
https://github.com/qemu/qemu/commit/6b895bf8fb088a04a91714a555d2b6234cf1e98d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VMLAS

Implement the MVE VMLAS insn, which multiplies a vector by a vector
and adds a scalar.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1b15a97d4cf99efdd60e60e0bfd2d185174ab0eb
      
https://github.com/qemu/qemu/commit/1b15a97d4cf99efdd60e60e0bfd2d185174ab0eb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE shift-by-scalar

Implement the MVE instructions which perform shifts by a scalar.
These are VSHL T2, VRSHL T2, VQSHL T1 and VQRSHL T2.  They take the
shift amount in a general purpose register and shift every element in
the vector by that amount.

Mostly we can reuse the helper functions for shift-by-immediate; we
do need two new helpers for VQRSHL.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 345910f8c1d687404b62194d929ca32f2ab54e80
      
https://github.com/qemu/qemu/commit/345910f8c1d687404b62194d929ca32f2ab54e80
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve.decode

  Log Message:
  -----------
  target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats

All the users of the vmlaldav formats have an 'x bit in bit 12 and an
'a' bit in bit 5; move these to the format rather than specifying them
in each insn pattern.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 688ba4cf33f4976e26124c4c24e9eb738615b0bf
      
https://github.com/qemu/qemu/commit/688ba4cf33f4976e26124c4c24e9eb738615b0bf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE integer min/max across vector

Implement the MVE integer min/max across vector insns
VMAXV, VMINV, VMAXAV and VMINAV, which find the maximum
from the vector elements and a general purpose register,
and store the maximum back into the general purpose
register.

These insns overlap with VRMLALDAVH (they use what would
be RdaHi=0b110).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7f061c0ab9289cb0ed55eaf09bec1b6cb474e6ee
      
https://github.com/qemu/qemu/commit/7f061c0ab9289cb0ed55eaf09bec1b6cb474e6ee
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VABAV

Implement the MVE VABAV insn, which computes absolute differences
between elements of two vectors and accumulates the result into
a general purpose register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 54dc78a901188d208a3dfedb0f98230043509120
      
https://github.com/qemu/qemu/commit/54dc78a901188d208a3dfedb0f98230043509120
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE narrowing moves

Implement the MVE narrowing move insns VMOVN, VQMOVN and VQMOVUN.
These take a double-width input, narrow it (possibly saturating) and
store the result to either the top or bottom half of the output
element.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 640cdf20a25d0021f4e93b6207b648a973df320b
      
https://github.com/qemu/qemu/commit/640cdf20a25d0021f4e93b6207b648a973df320b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn

The MVEGenDualAccOpFn is a bit misnamed, since it is used for
the "long dual accumulate" operations that use a 64-bit
accumulator. Rename it to MVEGenLongDualAccOpFn so we can
use the former name for the 32-bit accumulator insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f0ffff5163cb503de236fc766121601592f08744
      
https://github.com/qemu/qemu/commit/f0ffff5163cb503de236fc766121601592f08744
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VMLADAV and VMLSLDAV

Implement the MVE VMLADAV and VMLSLDAV insns.  Like the VMLALDAV and
VMLSLDAV insns already implemented, these accumulate multiplied
vector elements; but they accumulate a 32-bit result rather than a
64-bit one.

Note that these encodings overlap with what would be RdaHi=0b111 for
VMLALDAV, VMLSLDAV, VRMLALDAVH and VRMLSLDAVH.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c69e34c6debfb567f6118b59e6efa96a20765dda
      
https://github.com/qemu/qemu/commit/c69e34c6debfb567f6118b59e6efa96a20765dda
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VMLA

Implement the MVE VMLA insn, which multiplies a vector by a scalar
and accumulates into another vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8be9a25058f9a5505d6864f06de86ee01d42fc59
      
https://github.com/qemu/qemu/commit/8be9a25058f9a5505d6864f06de86ee01d42fc59
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE saturating doubling multiply accumulates

Implement the MVE saturating doubling multiply accumulate insns
VQDMLAH, VQRDMLAH, VQDMLASH and VQRDMLASH.  These perform a multiply,
double, add the accumulator shifted by the element size, possibly
round, saturate to twice the element size, then take the high half of
the result.  The *MLAH insns do vector * scalar + vector, and the
*MLASH insns do vector * vector + scalar.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 398e7cd3cd7a82eb04d236c7e30171f058f234b7
      
https://github.com/qemu/qemu/commit/398e7cd3cd7a82eb04d236c7e30171f058f234b7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VQABS, VQNEG

Implement the MVE 1-operand saturating operations VQABS and VQNEG.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d5c571ea6d1558934b0d1a95c51a2c084cf4fd85
      
https://github.com/qemu/qemu/commit/d5c571ea6d1558934b0d1a95c51a2c084cf4fd85
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VMAXA, VMINA

Implement the MVE VMAXA and VMINA insns, which take the absolute
value of the signed elements in the input vector and then accumulate
the unsigned max or min into the destination vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1241f148d52eea7c9350df918da0eafdfc539327
      
https://github.com/qemu/qemu/commit/1241f148d52eea7c9350df918da0eafdfc539327
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/mve.decode
    M target/arm/translate-a32.h
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c

  Log Message:
  -----------
  target/arm: Implement MVE VMOV to/from 2 general-purpose registers

Implement the MVE VMOV forms that move data between 2 general-purpose
registers and 2 32-bit lanes in a vector register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fea3958fa11c75b4f3f335ac0ce4cfc5cf0af7de
      
https://github.com/qemu/qemu/commit/fea3958fa11c75b4f3f335ac0ce4cfc5cf0af7de
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE VPNOT

Implement the MVE VPNOT insn, which inverts the bits in VPR.P0
(subject to both predication and to beatwise execution).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0f31e37c7f0b9577c6ce46304158ccd7c935006b
      
https://github.com/qemu/qemu/commit/0f31e37c7f0b9577c6ce46304158ccd7c935006b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve_helper.c
    M target/arm/t32.decode
    M target/arm/translate-a32.h
    M target/arm/translate-mve.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement MVE VCTP

Implement the MVE VCTP insn, which sets the VPR.P0 predicate bits so
as to predicate any element at index Rn or greater is predicated.  As
with VPNOT, this insn itself is predicable and subject to beatwise
execution.

The calculation of the mask is the same as is used to determine
ltpmask in mve_element_mask(), but we precalculate masklen in
generated code to avoid having to have 4 helpers specialized by size.

We put the decode line in with the low-overhead-loop insns in
t32.decode because it's logically part of that collection of insn
patterns, even though it is an MVE only insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dc18628b1833157a50a424cb6b83b63eca560402
      
https://github.com/qemu/qemu/commit/dc18628b1833157a50a424cb6b83b63eca560402
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE scatter-gather insns

Implement the MVE gather-loads and scatter-stores which
form the address by adding a base value from a scalar
register to an offset in each element of a vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fac80f0856cc465b21e2e59a64146b3540e055db
      
https://github.com/qemu/qemu/commit/fac80f0856cc465b21e2e59a64146b3540e055db
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE scatter-gather immediate forms

Implement the MVE VLDR/VSTR insns which do scatter-gather using base
addresses from Qm plus or minus an immediate offset (possibly with
writeback). Note that writeback is not predicated but it does have
to honour ECI state, so we have to add an eci_mask check to the
VSTR_SG macros (the VLDR_SG macros already needed this to be able
to distinguish "skip beat" from "set predicated element to 0").

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 075e7e97e3a042854b8ea2827559891a577b4a6b
      
https://github.com/qemu/qemu/commit/075e7e97e3a042854b8ea2827559891a577b4a6b
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper-mve.h
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/translate-mve.c

  Log Message:
  -----------
  target/arm: Implement MVE interleaving loads/stores

Implement the MVE interleaving load/store functions VLD2, VLD4, VST2
and VST4.  VLD2 loads 16 bytes of data from memory and writes to 2
consecutive Qregs; VLD4 loads 16 bytes of data from memory and writes
to 4 consecutive Qregs.  The 'pattern' field in the encoding
determines the offset into memory which is accessed and also which
elements in the Qregs are written to.  (The intention is that a
sequence of four consecutive VLD4 with different pattern values
performs a complete de-interleaving load of 64 bytes into all
elements of the 4 Qregs.) VST2 and VST4 do the same, but for stores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fc7a5038a6b70a3e474e58a5ed9845e4f5eed6dd
      
https://github.com/qemu/qemu/commit/fc7a5038a6b70a3e474e58a5ed9845e4f5eed6dd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Re-indent sdiv and udiv helpers

We're about to make a code change to the sdiv and udiv helper
functions, so first fix their indentation and coding style.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210730151636.17254-2-peter.maydell@linaro.org


  Commit: e5346292966f5348cd36668f2451ca0e44d820b2
      
https://github.com/qemu/qemu/commit/e5346292966f5348cd36668f2451ca0e44d820b2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/m_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement M-profile trapping on division by zero

Unlike A-profile, for M-profile the UDIV and SDIV insns can be
configured to raise an exception on division by zero, using the CCR
DIV_0_TRP bit.

Implement support for setting this bit by making the helper functions
raise the appropriate exception.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210730151636.17254-3-peter.maydell@linaro.org


  Commit: dfa0d9b80ed36c3e3a92346c35e7e7b1e4afc49d
      
https://github.com/qemu/qemu/commit/dfa0d9b80ed36c3e3a92346c35e7e7b1e4afc49d
  Author: Hamza Mahfooz <someguy@effective-light.com>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M target/arm/kvm.c

  Log Message:
  -----------
  target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()

As per commit 5626f8c6d468 ("rcu: Add automatically released rcu_read_lock
variants"), RCU_READ_LOCK_GUARD() should be used instead of
rcu_read_{un}lock().

Signed-off-by: Hamza Mahfooz <someguy@effective-light.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20210727235201.11491-1-someguy@effective-light.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d60af909d5131300596d4f6f052b2d0f44e76560
      
https://github.com/qemu/qemu/commit/d60af909d5131300596d4f6f052b2d0f44e76560
  Author: Jan Luebbe <jlu@pengutronix.de>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M hw/char/pl011.c

  Log Message:
  -----------
  hw/char/pl011: add support for sending break

Break events are currently only handled by chardev/char-serial.c, so we
just ignore errors, which results in no behaviour change for other
chardevs.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Message-id: 20210806144700.3751979-1-jlu@pengutronix.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ff31cca71ef257f8da2d9bc647ddd53f080ce580
      
https://github.com/qemu/qemu/commit/ff31cca71ef257f8da2d9bc647ddd53f080ce580
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M hw/arm/fsl-imx6ul.c

  Log Message:
  -----------
  fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices

Instantiate SAI1/2/3 and ASRC as unimplemented devices to avoid random
Linux kernel crashes, such as

Unhandled fault: external abort on non-linefetch (0x808) at 0xd1580010
pgd = (ptrval)
[d1580010] *pgd=8231b811, *pte=02034653, *ppte=02034453
Internal error: : 808 [#1] SMP ARM
...
[<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] 
(regmap_mmio_write+0x3c/0x54)
[<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0)
[<c09580f4>] (_regmap_write) from [<c095837c>] (_regmap_update_bits+0xe4/0xec)
[<c095837c>] (_regmap_update_bits) from [<c09599b4>] 
(regmap_update_bits_base+0x50/0x74)
[<c09599b4>] (regmap_update_bits_base) from [<c0d3e9e4>] 
(fsl_asrc_runtime_resume+0x1e4/0x21c)
[<c0d3e9e4>] (fsl_asrc_runtime_resume) from [<c0942464>] 
(__rpm_callback+0x3c/0x108)
[<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64)
[<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808)
[<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0)
[<c0942dfc>] (__pm_runtime_resume) from [<c0d3ecc4>] 
(fsl_asrc_probe+0x2a8/0x708)
[<c0d3ecc4>] (fsl_asrc_probe) from [<c0935b08>] (platform_probe+0x58/0xb8)
[<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334)
[<c0933264>] (really_probe.part.0) from [<c093359c>] 
(__driver_probe_device+0xa0/0x138)
[<c093359c>] (__driver_probe_device) from [<c0933664>] 
(driver_probe_device+0x30/0xc8)
[<c0933664>] (driver_probe_device) from [<c0933c88>] 
(__driver_attach+0x90/0x130)
[<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8)
[<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8)
[<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118)
[<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4)
[<c01022c0>] (do_one_initcall) from [<c1601204>] 
(kernel_init_freeable+0x198/0x22c)
[<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128)
[<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38)

or

Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000
pgd = (ptrval)
[d19b0000] *pgd=82711811, *pte=308a0653, *ppte=308a0453
Internal error: : 808 [#1] SMP ARM
...
[<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] 
(regmap_mmio_write+0x3c/0x54)
[<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0)
[<c09580f4>] (_regmap_write) from [<c0959b28>] (regmap_write+0x3c/0x60)
[<c0959b28>] (regmap_write) from [<c0d41130>] 
(fsl_sai_runtime_resume+0x9c/0x1ec)
[<c0d41130>] (fsl_sai_runtime_resume) from [<c0942464>] 
(__rpm_callback+0x3c/0x108)
[<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64)
[<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808)
[<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0)
[<c0942dfc>] (__pm_runtime_resume) from [<c0d4231c>] (fsl_sai_probe+0x2b8/0x65c)
[<c0d4231c>] (fsl_sai_probe) from [<c0935b08>] (platform_probe+0x58/0xb8)
[<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334)
[<c0933264>] (really_probe.part.0) from [<c093359c>] 
(__driver_probe_device+0xa0/0x138)
[<c093359c>] (__driver_probe_device) from [<c0933664>] 
(driver_probe_device+0x30/0xc8)
[<c0933664>] (driver_probe_device) from [<c0933c88>] 
(__driver_attach+0x90/0x130)
[<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8)
[<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8)
[<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118)
[<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4)
[<c01022c0>] (do_one_initcall) from [<c1601204>] 
(kernel_init_freeable+0x198/0x22c)
[<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128)
[<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210810160318.87376-1-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 77844cc51aa0714d54ae6f5a12279ce0e7f5ef55
      
https://github.com/qemu/qemu/commit/77844cc51aa0714d54ae6f5a12279ce0e7f5ef55
  Author: Wen, Jianxian <Jianxian.Wen@verisilicon.com>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M hw/arm/exynos4210.c
    M hw/arm/xilinx_zynq.c
    M hw/dma/pl330.c

  Log Message:
  -----------
  hw/dma/pl330: Add memory region to replace default

Add property memory region which can connect with IOMMU region to support SMMU 
translate.

Signed-off-by: Jianxian Wen <jianxian.wen@verisilicon.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 4C23C17B8E87E74E906A25A3254A03F4FA1FEC31@SHASXM03.verisilicon.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 80d60a6d1efebcf35ff96e2d0a51373b0383bc10
      
https://github.com/qemu/qemu/commit/80d60a6d1efebcf35ff96e2d0a51373b0383bc10
  Author: Eduardo Habkost <ehabkost@redhat.com>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  sbsa-ref: Rename SBSA_GWDT enum value

The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type
checking helper, preventing us from using a OBJECT_DEFINE* or
DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper.

If I understand the SBSA 6.0 specification correctly, the signal
being connected to IRQ 16 is the WS0 output signal from the
Generic Watchdog.  Rename the enum value to SBSA_GWDT_WS0 to be
more explicit and avoid the name conflict.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-id: 20210806023119.431680-1-ehabkost@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6f287c700c5fad924585dee1308477aa9e73ae50
      
https://github.com/qemu/qemu/commit/6f287c700c5fad924585dee1308477aa9e73ae50
  Author: Guenter Roeck <linux@roeck-us.net>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M hw/arm/fsl-imx7.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices

Instantiate SAI1/2/3 as unimplemented devices to avoid Linux kernel crashes
such as the following.

Unhandled fault: external abort on non-linefetch (0x808) at 0xd19b0000
pgd = (ptrval)
[d19b0000] *pgd=82711811, *pte=308a0653, *ppte=308a0453
Internal error: : 808 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-rc5 #1
...
[<c095e974>] (regmap_mmio_write32le) from [<c095eb48>] 
(regmap_mmio_write+0x3c/0x54)
[<c095eb48>] (regmap_mmio_write) from [<c09580f4>] (_regmap_write+0x4c/0x1f0)
[<c09580f4>] (_regmap_write) from [<c0959b28>] (regmap_write+0x3c/0x60)
[<c0959b28>] (regmap_write) from [<c0d41130>] 
(fsl_sai_runtime_resume+0x9c/0x1ec)
[<c0d41130>] (fsl_sai_runtime_resume) from [<c0942464>] 
(__rpm_callback+0x3c/0x108)
[<c0942464>] (__rpm_callback) from [<c0942590>] (rpm_callback+0x60/0x64)
[<c0942590>] (rpm_callback) from [<c0942b60>] (rpm_resume+0x5cc/0x808)
[<c0942b60>] (rpm_resume) from [<c0942dfc>] (__pm_runtime_resume+0x60/0xa0)
[<c0942dfc>] (__pm_runtime_resume) from [<c0d4231c>] (fsl_sai_probe+0x2b8/0x65c)
[<c0d4231c>] (fsl_sai_probe) from [<c0935b08>] (platform_probe+0x58/0xb8)
[<c0935b08>] (platform_probe) from [<c0933264>] (really_probe.part.0+0x9c/0x334)
[<c0933264>] (really_probe.part.0) from [<c093359c>] 
(__driver_probe_device+0xa0/0x138)
[<c093359c>] (__driver_probe_device) from [<c0933664>] 
(driver_probe_device+0x30/0xc8)
[<c0933664>] (driver_probe_device) from [<c0933c88>] 
(__driver_attach+0x90/0x130)
[<c0933c88>] (__driver_attach) from [<c0931060>] (bus_for_each_dev+0x78/0xb8)
[<c0931060>] (bus_for_each_dev) from [<c093254c>] (bus_add_driver+0xf0/0x1d8)
[<c093254c>] (bus_add_driver) from [<c0934a30>] (driver_register+0x88/0x118)
[<c0934a30>] (driver_register) from [<c01022c0>] (do_one_initcall+0x7c/0x3a4)
[<c01022c0>] (do_one_initcall) from [<c1601204>] 
(kernel_init_freeable+0x198/0x22c)
[<c1601204>] (kernel_init_freeable) from [<c0f5ff2c>] (kernel_init+0x10/0x128)
[<c0f5ff2c>] (kernel_init) from [<c010013c>] (ret_from_fork+0x14/0x38)

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20210810175607.538090-1-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 24b1a6aa43615be22c7ee66bd68ec5675f6a6a9a
      
https://github.com/qemu/qemu/commit/24b1a6aa43615be22c7ee66bd68ec5675f6a6a9a
  Author: Sebastian Meyer <meyer@absint.com>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M docs/system/gdb.rst

  Log Message:
  -----------
  docs: Document how to use gdb with unix sockets

With gdb 9.0 and better it is possible to connect to a gdbstub
over unix sockets, which is better than a TCP socket connection
in some situations. The QEMU command line to set this up is
non-obvious; document it.

Signed-off-by: Sebastian Meyer <meyer@absint.com>
Message-id: 162867284829.27377.4784930719350564918-0@git.sr.ht
[PMM: Tweaked commit message; adjusted wording in a couple of
places; fixed rST formatting issue; moved section up out of
the 'advanced debugging options' subsection]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 52fecb866923890b16202be8e0f360bf247db6a7
      
https://github.com/qemu/qemu/commit/52fecb866923890b16202be8e0f360bf247db6a7
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M docs/system/gdb.rst
    M hw/arm/exynos4210.c
    M hw/arm/fsl-imx6ul.c
    M hw/arm/fsl-imx7.c
    M hw/arm/sbsa-ref.c
    M hw/arm/xilinx_zynq.c
    M hw/char/pl011.c
    M hw/dma/pl330.c
    M include/hw/arm/fsl-imx7.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper-mve.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm.c
    M target/arm/m_helper.c
    M target/arm/mve.decode
    M target/arm/mve_helper.c
    M target/arm/t32.decode
    M target/arm/translate-a32.h
    M target/arm/translate-mve.c
    M target/arm/translate-vfp.c
    M target/arm/translate.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210825' 
into staging

target-arm queue:
 * More MVE emulation work
 * Implement M-profile trapping on division by zero
 * kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
 * hw/char/pl011: add support for sending break
 * fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices
 * hw/dma/pl330: Add memory region to replace default
 * sbsa-ref: Rename SBSA_GWDT enum value
 * fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices
 * docs: Document how to use gdb with unix sockets

# gpg: Signature made Wed 25 Aug 2021 11:34:50 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210825: (44 commits)
  docs: Document how to use gdb with unix sockets
  fsl-imx7: Instantiate SAI1/2/3 as unimplemented devices
  sbsa-ref: Rename SBSA_GWDT enum value
  hw/dma/pl330: Add memory region to replace default
  fsl-imx6ul: Instantiate SAI1/2/3 and ASRC as unimplemented devices
  hw/char/pl011: add support for sending break
  target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()
  target/arm: Implement M-profile trapping on division by zero
  target/arm: Re-indent sdiv and udiv helpers
  target/arm: Implement MVE interleaving loads/stores
  target/arm: Implement MVE scatter-gather immediate forms
  target/arm: Implement MVE scatter-gather insns
  target/arm: Implement MVE VCTP
  target/arm: Implement MVE VPNOT
  target/arm: Implement MVE VMOV to/from 2 general-purpose registers
  target/arm: Implement MVE VMAXA, VMINA
  target/arm: Implement MVE VQABS, VQNEG
  target/arm: Implement MVE saturating doubling multiply accumulates
  target/arm: Implement MVE VMLA
  target/arm: Implement MVE VMLADAV and VMLSLDAV
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/d42685765653...52fecb866923