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[Qemu-commits] [qemu/qemu] 1b4184: hw/arm/smmuv3: Check 31st bit to see

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 1b4184: hw/arm/smmuv3: Check 31st bit to see if CD is valid
Date: Tue, 27 Jul 2021 07:37:41 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 1b41847afbe9974356848a61b203445e4ca645f3
      
https://github.com/qemu/qemu/commit/1b41847afbe9974356848a61b203445e4ca645f3
  Author: Joe Komlodi <joe.komlodi@xilinx.com>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/arm/smmuv3-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Check 31st bit to see if CD is valid

The bit to see if a CD is valid is the last bit of the first word of the CD.

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 953558291ec319476355900655fa53aa84ab99f0
      
https://github.com/qemu/qemu/commit/953558291ec319476355900655fa53aa84ab99f0
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M qemu-options.hx

  Log Message:
  -----------
  qemu-options.hx: Fix formatting of -machine memory-backend option

The documentation of the -machine memory-backend has some minor
formatting errors:
 * Misindentation of the initial line meant that the whole option
   section is incorrectly indented in the HTML output compared to
   the other -machine options
 * The examples weren't indented, which meant that they were formatted
   as plain run-on text including outputting the "::" as text.
 * The a) b) list has no rst-format markup so it is rendered as
   a single run-on paragraph

Fix the formatting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20210719105257.3599-1-peter.maydell@linaro.org


  Commit: 888f470f123521b4fc9974d2dd1cc48629d73adc
      
https://github.com/qemu/qemu/commit/888f470f123521b4fc9974d2dd1cc48629d73adc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M target/arm/gdbstub.c
    M target/arm/m_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Enforce that M-profile SP low 2 bits are always zero

For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
RES0H, which is to say that they must be hardwired to zero so that
guest attempts to write non-zero values to them are ignored.

Implement this behaviour by masking out the low bits:
 * for writes to r13 by the gdbstub
 * for writes to any of the various flavours of SP via MSR
 * for writes to r13 via store_reg() in generated code

Note that all the direct uses of cpu_R[] in translate.c are in places
where the register is definitely not r13 (usually because that has
been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
UNDEF).

All the other writes to regs[13] in C code are either:
 * A-profile only code
 * writes of values we can guarantee to be aligned, such as
   - writes of previous-SP-value plus or minus a 4-aligned constant
   - writes of the value in an SP limit register (which we already
     enforce to be aligned)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-2-peter.maydell@linaro.org


  Commit: 0c317eb3dd407f2ec7fcaccec79be6c3987573e2
      
https://github.com/qemu/qemu/commit/0c317eb3dd407f2ec7fcaccec79be6c3987573e2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Add missing 'return's after calling v7m_exception_taken()

In do_v7m_exception_exit(), we perform various checks as part of
performing the exception return.  If one of these checks fails, the
architecture requires that we take an appropriate exception on the
existing stackframe.  We implement this by calling
v7m_exception_taken() to set up to take the new exception, and then
immediately returning from do_v7m_exception_exit() without proceeding
any further with the unstack-and-exception-return process.

In a couple of checks that are new in v8.1M, we forgot the "return"
statement, with the effect that if bad code in the guest tripped over
these checks we would set up to take a UsageFault exception but then
blunder on trying to also unstack and return from the original
exception, with the probable result that the guest would crash.

Add the missing return statements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-3-peter.maydell@linaro.org


  Commit: d4f6883912dba8a710274e2364c440c210e4ec65
      
https://github.com/qemu/qemu/commit/d4f6883912dba8a710274e2364c440c210e4ec65
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Report M-profile alignment faults correctly to the guest

For M-profile, we weren't reporting alignment faults triggered by the
generic TCG code correctly to the guest.  These get passed into
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
style exception.fsr value of 1.  We didn't check for this, and so
they fell through into the default of "assume this is an MPU fault"
and were reported to the guest as a data access violation MPU fault.

Report these alignment faults as UsageFaults which set the UNALIGNED
bit in the UFSR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org


  Commit: 41487794f5af977e992870e18521bed88daa68d5
      
https://github.com/qemu/qemu/commit/41487794f5af977e992870e18521bed88daa68d5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts

The ISCR.ISRPENDING bit is set when an external interrupt is pending.
This is true whether that external interrupt is enabled or not.
This means that we can't use 's->vectpending == 0' as a shortcut to
"ISRPENDING is zero", because s->vectpending indicates only the
highest priority pending enabled interrupt.

Remove the incorrect optimization so that if there is no pending
enabled interrupt we fall through to scanning through the whole
interrupt array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org


  Commit: 7caad65756c0afaf4b238b068ab61481eb68a1dc
      
https://github.com/qemu/qemu/commit/7caad65756c0afaf4b238b068ab61481eb68a1dc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING

The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
the register.  We were incorrectly masking it to 8 bits, so it would
report the wrong value if the pending exception was greater than 256.
Fix the bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-6-peter.maydell@linaro.org


  Commit: 845d27a91315bc1e3a0000339c5ee46ef63598a5
      
https://github.com/qemu/qemu/commit/845d27a91315bc1e3a0000339c5ee46ef63598a5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS

In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
the register is accessed NonSecure and the highest priority pending
enabled exception (that would be returned in the VECTPENDING field)
targets Secure, then the VECTPENDING field must read 1 rather than
the exception number of the pending exception. Implement this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org


  Commit: a476b2167296c0f8bfd6a66d1eb54ca39ea0e6f2
      
https://github.com/qemu/qemu/commit/a476b2167296c0f8bfd6a66d1eb54ca39ea0e6f2
  Author: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M MAINTAINERS
    M configure
    M target/i386/cpu.c

  Log Message:
  -----------
  docs: Update path that mentions deprecated.rst

Missed in commit f3478392 "docs: Move deprecation, build
and license info out of system/"

Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dc0bc8e7855643c4c2aaff74409bada9761b390e
      
https://github.com/qemu/qemu/commit/dc0bc8e7855643c4c2aaff74409bada9761b390e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Correctly bound length in sve_zcr_get_valid_len

Currently, our only caller is sve_zcr_len_for_el, which has
already masked the length extracted from ZCR_ELx, so the
masking done here is a nop.  But we will shortly have uses
from other locations, where the length will be unmasked.

Saturate the length to ARM_MAX_VQ instead of truncating to
the low 4 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ce440581c1446e56d911d83c9c3b760ae4f98b3e
      
https://github.com/qemu/qemu/commit/ce440581c1446e56d911d83c9c3b760ae4f98b3e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Export aarch64_sve_zcr_get_valid_len

Rename from sve_zcr_get_valid_len and make accessible
from outside of helper.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b3d52804c591b478ec0620253c2bd71e4ff87bb9
      
https://github.com/qemu/qemu/commit/b3d52804c591b478ec0620253c2bd71e4ff87bb9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M docs/system/arm/cpu-features.rst
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Add sve-default-vector-length cpu property

Mirror the behavour of /proc/sys/abi/sve_default_vector_length
under the real linux kernel.  We have no way of passing along
a real default across exec like the kernel can, but this is a
decent way of adjusting the startup vector length of a process.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
[PMM: tweaked docs formatting, document -1 special-case,
 added fixup patch from RTH mentioning QEMU's maximum veclen.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b1c2a6bd3d035a60bc7c6cbc109996af8cfe2b05
      
https://github.com/qemu/qemu/commit/b1c2a6bd3d035a60bc7c6cbc109996af8cfe2b05
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/arm/nseries.c

  Log Message:
  -----------
  hw/arm/nseries: Display hexadecimal value with '0x' prefix

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210726150953.1218690-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e229a179a503f2aee43a76888cf12fbdfe8a3749
      
https://github.com/qemu/qemu/commit/e229a179a503f2aee43a76888cf12fbdfe8a3749
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M hw/gpio/aspeed_gpio.c

  Log Message:
  -----------
  hw: aspeed_gpio: Fix memory size

The macro used to calculate the maximum memory size of the MMIO region
had a mistake, causing all GPIO models to create a mapping of 0x9D8.
The intent was to have it be 0x9D8 - 0x800.

This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
region set aside for the GPIO controller.

On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
regions would overlap. Worse was the 1.8V controller would map over the
top of the following peripheral, which happens to be the RTC.

The mmio region used by each device is a maximum of 2KB, so avoid the
calculations and hard code this as the maximum.

Fixes: 36d737ee82b2 ("hw/gpio: Add in AST2600 specific implementation")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210713065854.134634-2-joel@jms.id.au
[PMM: fix autocorrect error in commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9ae1246a9b8641a0a152d982d8473a67501422e2
      
https://github.com/qemu/qemu/commit/9ae1246a9b8641a0a152d982d8473a67501422e2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-27 (Tue, 27 Jul 2021)

  Changed paths:
    M MAINTAINERS
    M configure
    M docs/system/arm/cpu-features.rst
    M hw/arm/nseries.c
    M hw/arm/smmuv3-internal.h
    M hw/gpio/aspeed_gpio.c
    M hw/intc/armv7m_nvic.c
    M qemu-options.hx
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/gdbstub.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/m_helper.c
    M target/arm/translate.c
    M target/i386/cpu.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210727' 
into staging

target-arm queue:
 * hw/arm/smmuv3: Check 31st bit to see if CD is valid
 * qemu-options.hx: Fix formatting of -machine memory-backend option
 * hw: aspeed_gpio: Fix memory size
 * hw/arm/nseries: Display hexadecimal value with '0x' prefix
 * Add sve-default-vector-length cpu property
 * docs: Update path that mentions deprecated.rst
 * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
 * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
 * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending 
interrupts
 * target/arm: Report M-profile alignment faults correctly to the guest
 * target/arm: Add missing 'return's after calling v7m_exception_taken()
 * target/arm: Enforce that M-profile SP low 2 bits are always zero

# gpg: Signature made Tue 27 Jul 2021 11:46:17 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210727:
  hw: aspeed_gpio: Fix memory size
  hw/arm/nseries: Display hexadecimal value with '0x' prefix
  target/arm: Add sve-default-vector-length cpu property
  target/arm: Export aarch64_sve_zcr_get_valid_len
  target/arm: Correctly bound length in sve_zcr_get_valid_len
  docs: Update path that mentions deprecated.rst
  hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
  hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
  hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
  target/arm: Report M-profile alignment faults correctly to the guest
  target/arm: Add missing 'return's after calling v7m_exception_taken()
  target/arm: Enforce that M-profile SP low 2 bits are always zero
  qemu-options.hx: Fix formatting of -machine memory-backend option
  hw/arm/smmuv3: Check 31st bit to see if CD is valid

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/202abcd38920...9ae1246a9b86
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