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[Qemu-commits] [qemu/qemu] caf108: hw/i386/acpi-build: Add ACPI PCI hot-


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] caf108: hw/i386/acpi-build: Add ACPI PCI hot-plug methods ...
Date: Fri, 16 Jul 2021 10:49:50 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: caf108bc587908f7608729f39639dccdfa53010b
      
https://github.com/qemu/qemu/commit/caf108bc587908f7608729f39639dccdfa53010b
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/acpi/pcihp.c
    M hw/acpi/piix4.c
    M hw/i386/acpi-build.c
    M hw/i386/acpi-build.h
    M include/hw/acpi/ich9.h
    M include/hw/acpi/pcihp.h

  Log Message:
  -----------
  hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35

Implement notifications and gpe to support q35 ACPI PCI hot-plug.
Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports.

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Message-Id: <20210713004205.775386-2-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: c0e427d6eb5fefc5382ab01e78611740db1b5d06
      
https://github.com/qemu/qemu/commit/c0e427d6eb5fefc5382ab01e78611740db1b5d06
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/acpi/acpi-x86-stub.c
    M hw/acpi/ich9.c
    M hw/acpi/pcihp.c
    M hw/i386/acpi-build.c
    M hw/i386/acpi-build.h
    M include/hw/acpi/ich9.h

  Log Message:
  -----------
  hw/acpi/ich9: Enable ACPI PCI hot-plug

Add acpi_pcihp to ich9_pm as part of
'acpi-pci-hotplug-with-bridge-support' option. Set default to false.

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20210713004205.775386-3-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 3f3cbbb2369ebba67cccf8c60d6a0043b315e17c
      
https://github.com/qemu/qemu/commit/3f3cbbb2369ebba67cccf8c60d6a0043b315e17c
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/acpi/pcihp.c
    M hw/core/machine.c
    M hw/i386/pc_q35.c
    M hw/pci/pcie.c
    M hw/pci/pcie_port.c
    M include/hw/pci/pcie_port.h

  Log Message:
  -----------
  hw/pci/pcie: Do not set HPC flag if acpihp is used

Instead of changing the hot-plug type in _OSC register, do not
set the 'Hot-Plug Capable' flag. This way guest will choose ACPI
hot-plug if it is preferred and leave the option to use SHPC with
pcie-pci-bridge.

The ability to control hot-plug for each downstream port is retained,
while 'hotplug=off' on the port means all hot-plug types are disabled.

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210713004205.775386-4-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 383d11f217feca0f9947f790f2deafc09fe69ec5
      
https://github.com/qemu/qemu/commit/383d11f217feca0f9947f790f2deafc09fe69ec5
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M tests/qtest/bios-tables-test-allowed-diff.h

  Log Message:
  -----------
  bios-tables-test: Allow changes in DSDT ACPI tables

All DSDT Q35 tables will be modified because ACPI hot-plug is enabled
by default.

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Message-Id: <20210713004205.775386-5-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 17858a169508609ca9063c544833e5a1adeb7b52
      
https://github.com/qemu/qemu/commit/17858a169508609ca9063c544833e5a1adeb7b52
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/acpi/ich9.c
    M hw/i386/pc.c

  Log Message:
  -----------
  hw/acpi/ich9: Set ACPI PCI hot-plug as default on Q35

Q35 has three different types of PCI devices hot-plug: PCIe Native,
SHPC Native and ACPI hot-plug. This patch changes the default choice
for cold-plugged bridges from PCIe Native to ACPI Hot-plug with
ability to use SHPC and PCIe Native for hot-plugged bridges.

This is a list of the PCIe Native hot-plug issues that led to this
change:
    * no racy behavior during boot (see 110c477c2ed)
    * no delay during deleting - after the actual power off software
      must wait at least 1 second before indicating about it. This case
      is quite important for users, it even has its own bug:
          https://bugzilla.redhat.com/show_bug.cgi?id=1594168
    * no timer-based behavior - in addition to the previous example,
      the attention button has a 5-second waiting period, during which
      the operation can be canceled with a second press. While this
      looks fine for manual button control, automation will result in
      the need to queue or drop events, and the software receiving
      events in all sort of unspecified combinations of attention/power
      indicator states, which is racy and uppredictable.
    * fixes:
        * https://bugzilla.redhat.com/show_bug.cgi?id=1752465
        * https://bugzilla.redhat.com/show_bug.cgi?id=1690256

To return to PCIe Native hot-plug:
    -global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off

Known issue: older linux guests need the following flag
to allow hotplugged pci express devices to use io:
        -device pcie-root-port,io-reserve=4096.
io is unusual for pci express so this seems minor.
We'll fix this by a follow up patch.

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20210713004205.775386-6-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>


  Commit: 1580b897c7b2f794fff7ba140ab757be1f6efadc
      
https://github.com/qemu/qemu/commit/1580b897c7b2f794fff7ba140ab757be1f6efadc
  Author: Julia Suvorova <jusual@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M tests/data/acpi/q35/DSDT
    M tests/data/acpi/q35/DSDT.acpihmat
    M tests/data/acpi/q35/DSDT.bridge
    M tests/data/acpi/q35/DSDT.cphp
    M tests/data/acpi/q35/DSDT.dimmpxm
    M tests/data/acpi/q35/DSDT.ipmibt
    M tests/data/acpi/q35/DSDT.memhp
    M tests/data/acpi/q35/DSDT.mmio64
    M tests/data/acpi/q35/DSDT.nohpet
    M tests/data/acpi/q35/DSDT.numamem
    M tests/data/acpi/q35/DSDT.tis
    M tests/qtest/bios-tables-test-allowed-diff.h

  Log Message:
  -----------
  bios-tables-test: Update golden binaries

Add ACPI hot-plug registers to DSDT Q35 tables.
Changes in the tables:

+    Scope (_SB.PCI0)
+    {
+        OperationRegion (PCST, SystemIO, 0x0CC4, 0x08)
+        Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+        {
+            PCIU,   32,
+            PCID,   32
+        }
+
+        OperationRegion (SEJ, SystemIO, 0x0CCC, 0x04)
+        Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+        {
+            B0EJ,   32
+        }
+
+        OperationRegion (BNMR, SystemIO, 0x0CD4, 0x08)
+        Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+        {
+            BNUM,   32,
+            PIDX,   32
+        }
+
+        Mutex (BLCK, 0x00)
+        Method (PCEJ, 2, NotSerialized)
+        {
+            Acquire (BLCK, 0xFFFF)
+            BNUM = Arg0
+            B0EJ = (One << Arg1)
+            Release (BLCK)
+            Return (Zero)
+        }
+
+        Method (AIDX, 2, NotSerialized)
+        {
+            Acquire (BLCK, 0xFFFF)
+            BNUM = Arg0
+            PIDX = (One << Arg1)
+            Local0 = PIDX /* \_SB_.PCI0.PIDX */
+            Release (BLCK)
+            Return (Local0)
+        }
+
+        Method (PDSM, 6, Serialized)
+        {
+            If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* 
Device Labeling Interface */))
+            {
+                Local0 = AIDX (Arg4, Arg5)
+                If ((Arg2 == Zero))
+                {
+                    If ((Arg1 == 0x02))
+                    {
+                        If (!((Local0 == Zero) | (Local0 == 0xFFFFFFFF)))
+                        {
+                            Return (Buffer (One)
+                            {
+                                 0x81                                          
   // .
+                            })
+                        }
+                    }
+
+                    Return (Buffer (One)
+                    {
+                         0x00                                             // .
+                    })
+                }
+                ElseIf ((Arg2 == 0x07))
+                {
+                    Local1 = Package (0x02)
+                        {
+                            Zero,
+                            ""
+                        }
+                    Local1 [Zero] = Local0
+                    Return (Local1)
+                }
+            }
+        }
+    }
+
...

     Scope (_GPE)
     {
         Name (_HID, "ACPI0006" /* GPE Block Device */)  // _HID: Hardware ID
+        Method (_E01, 0, NotSerialized)  // _Exx: Edge-Triggered GPE, 
xx=0x00-0xFF
+        {
+            Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+            \_SB.PCI0.PCNT ()
+            Release (\_SB.PCI0.BLCK)
+        }
...

+
+        Device (PHPR)
+        {
+            Name (_HID, "PNP0A06" /* Generic Container Device */)  // _HID: 
Hardware ID
+            Name (_UID, "PCI Hotplug resources")  // _UID: Unique ID
+            Name (_STA, 0x0B)  // _STA: Status
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                IO (Decode16,
+                    0x0CC4,             // Range Minimum
+                    0x0CC4,             // Range Maximum
+                    0x01,               // Alignment
+                    0x18,               // Length
+                    )
+            })
+        }
     }
...

And if there is a port in configuration:

             Device (S10)
             {
                 Name (_ADR, 0x00020000)  // _ADR: Address
+                Name (BSEL, Zero)
+                Device (S00)
+                {
+                    Name (_SUN, Zero)  // _SUN: Slot User Number
+                    Name (_ADR, Zero)  // _ADR: Address
+                    Method (_EJ0, 1, NotSerialized)  // _EJx: Eject Device, 
x=0-9
+                    {
+                        PCEJ (BSEL, _SUN)
+                    }
+
+                    Method (_DSM, 4, Serialized)  // _DSM: Device-Specific 
Method
+                    {
+                        Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))
+                    }
+                }
+
...

+                Method (DVNT, 2, NotSerialized)
+                {
+                    If ((Arg0 & One))
+                    {
+                        Notify (S00, Arg1)
+                    }
...

Signed-off-by: Julia Suvorova <jusual@redhat.com>
Message-Id: <20210713004205.775386-7-jusual@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 7221d3b634d1995a63a91de9b5035abf643c7ebc
      
https://github.com/qemu/qemu/commit/7221d3b634d1995a63a91de9b5035abf643c7ebc
  Author: Viresh Kumar <viresh.kumar@linaro.org>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/virtio/Kconfig
    M hw/virtio/meson.build
    A hw/virtio/vhost-user-i2c.c
    A include/hw/virtio/vhost-user-i2c.h

  Log Message:
  -----------
  hw/virtio: add boilerplate for vhost-user-i2c device

This creates the QEMU side of the vhost-user-i2c device which connects
to the remote daemon. It is based of vhost-user-fs code.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Message-Id: 
<e80591b52fea4b51631818bb92a798a3daf90399.1625806763.git.viresh.kumar@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 538bb6f1219c1711538d73143f005e62c3d20f7b
      
https://github.com/qemu/qemu/commit/538bb6f1219c1711538d73143f005e62c3d20f7b
  Author: Viresh Kumar <viresh.kumar@linaro.org>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/virtio/meson.build
    A hw/virtio/vhost-user-i2c-pci.c

  Log Message:
  -----------
  hw/virtio: add vhost-user-i2c-pci boilerplate

This allows is to instantiate a vhost-user-i2c device as part of a PCI
bus. It is mostly boilerplate which looks pretty similar to the
vhost-user-fs-pci device.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Message-Id: 
<8a083eaa57d93feaab12acd1f94b225879212f20.1625806763.git.viresh.kumar@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 7395b3e3e70031b1efff7941cbef6a1ceb6f2ffd
      
https://github.com/qemu/qemu/commit/7395b3e3e70031b1efff7941cbef6a1ceb6f2ffd
  Author: Peter Xu <peterx@redhat.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M qemu-options.hx

  Log Message:
  -----------
  docs: Add '-device intel-iommu' entry

The parameters of intel-iommu device are non-trivial to understand.  Add an
entry for it so that people can reference to it when using.

There're actually a few more options there, but I hide them explicitly because
they shouldn't be used by normal QEMU users.

Cc: Chao Yang <chayang@redhat.com>
Cc: Lei Yang <leiyang@redhat.com>
Cc: Jing Zhao <jinzhao@redhat.com>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Peter Xu <peterx@redhat.com>
Message-Id: <20210707154114.197580-1-peterx@redhat.com>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 2d64b7bbb2a2e945635633486ef9a060cb2c89bc
      
https://github.com/qemu/qemu/commit/2d64b7bbb2a2e945635633486ef9a060cb2c89bc
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/pci/pci.c
    M hw/pci/pci_host.c
    M include/hw/pci/pci.h
    M include/hw/pci/pci_host.h

  Log Message:
  -----------
  hw/pci/pci_host: Allow PCI host to bypass iommu

Add a new bypass_iommu property for PCI host and use it to check
whether devices attached to the PCI root bus will bypass iommu.
In pci_device_iommu_address_space(), check the property and
avoid getting iommu address space for devices bypass iommu.

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <1625748919-52456-2-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 91528f40ba3dda110927f11b47620bb24f8d601b
      
https://github.com/qemu/qemu/commit/91528f40ba3dda110927f11b47620bb24f8d601b
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/pci-bridge/pci_expander_bridge.c

  Log Message:
  -----------
  hw/pxb: Add a bypass iommu property

Add a bypass_iommu property for pci_expander_bridge, the property
is used to indicate whether pxb root bus will bypass iommu. By
default the bypass_iommu is disabled, and it can be enabled with:
qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <1625748919-52456-3-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 6d7a85483a069b99ad4b018509643437b8f9a4f7
      
https://github.com/qemu/qemu/commit/6d7a85483a069b99ad4b018509643437b8f9a4f7
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Add default_bus_bypass_iommu machine option

Add a default_bus_bypass_iommu machine option to enable/disable
bypass_iommu for default root bus. The option is disabled by
default and can be enabled with:
$QEMU -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-4-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: c9e96b04fc192fb38622694947dae091bbbdf28f
      
https://github.com/qemu/qemu/commit/c9e96b04fc192fb38622694947dae091bbbdf28f
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/i386/pc.c
    M hw/pci-host/q35.c
    M include/hw/i386/pc.h

  Log Message:
  -----------
  hw/i386: Add a default_bus_bypass_iommu pc machine option

Add a default_bus_bypass_iommu pc machine option to enable/disable
bypass_iommu for default root bus. The option is disabled by default
and can be enabled with:
$QEMU -machine q35,default_bus_bypass_iommu=true

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-5-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 500db1daf3079c3d0222bd3963cf4e5bf6175175
      
https://github.com/qemu/qemu/commit/500db1daf3079c3d0222bd3963cf4e5bf6175175
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/pci/pci.c
    M include/hw/pci/pci.h

  Log Message:
  -----------
  hw/pci: Add pci_bus_range() to get PCI bus number range

This helps to get the min and max bus number of a PCI bus hierarchy.

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <1625748919-52456-6-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 42e0f050e3a513f070b1c2e885890ac2095337e8
      
https://github.com/qemu/qemu/commit/42e0f050e3a513f070b1c2e885890ac2095337e8
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/arm/virt-acpi-build.c

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3

When we build IORT table with SMMUv3 and bypass iommu feature enabled,
we can no longer setup one map from RC to SMMUv3 covering the whole RIDs.
We need to walk the PCI bus and check whether the root bus will bypass
iommu, setup RC -> SMMUv3 -> ITS map for RC which will not bypass iommu.

When a SMMUv3 node exist, we setup the idmap from SMMUv3 to ITS
covering the whole RIDs, and only modify the map from RC to SMMUv3.
We build RC -> SMMUv3 -> ITS map for root bus with bypass_iommu
disabled, and build idmap from RC to ITS directly for the rest of
the whole RID space.

For example we run qemu with command line:

qemu/build/aarch64-softmmu/qemu-system-aarch64 \
 -kernel arch/arm64/boot/Image \
 -enable-kvm \
 -cpu host \
 -m 8G \
 -smp 8,sockets=2,cores=4,threads=1 \
 -machine 
virt,kernel_irqchip=on,gic-version=3,iommu=smmuv3,default_bus_bypass_iommu=true 
\
 -drive file=./QEMU_EFI-pflash.raw,if=pflash,format=raw,unit=0,readonly=on \
 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
 -device 
pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
 -device pcie-root-port,port=0x20,chassis=1,id=pci.1,bus=pcie.0,addr=0x2 \
 -device pcie-root-port,port=0x20,chassis=11,id=pci.11,bus=pci.10,addr=0x1 \
 -device pcie-root-port,port=0x20,chassis=21,id=pci.21,bus=pci.20,addr=0x1 \
 -device virtio-scsi-pci,id=scsi0,bus=pci.1,addr=0x1 \
 -device virtio-scsi-pci,id=scsi1,bus=pci.11,addr=0x1 \
 -device virtio-scsi-pci,id=scsi2,bus=pci.21,addr=0x1 \
 -initrd /mnt/davinci/wxg/kill-linux/rootfs/mfs.cpio.gz \
 -nographic \
 -append "rdinit=init console=ttyAMA0 earlycon=pl011,0x9000000 nokaslr" \

And we get guest configuration:

-+-[0000:20]---01.0-[21]--
 +-[0000:10]---01.0-[11]--
 \-[0000:00]-+-00.0  Device 1b36:0008
             +-01.0  Device 1af4:1000
             \-02.0-[01]--

With bypass_iommu enabled, the attached devices will bypass iommu.

/sys/class/iommu/smmu3.0x0000000009050000/
|-- device -> ../../../arm-smmu-v3.0.auto
|-- devices
|   `-- 0000:10:01.0 -> ../../../../../pci0000:10/0000:10:01.0

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-7-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 26863366b29ab638711bbe0fa741dcf355eddb54
      
https://github.com/qemu/qemu/commit/26863366b29ab638711bbe0fa741dcf355eddb54
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/i386/acpi-build.c

  Log Message:
  -----------
  hw/i386/acpi-build: Add DMAR support to bypass iommu

In DMAR table, the drhd is set to cover all PCI devices when intel_iommu
is on. To support bypass iommu feature, we need to walk the PCI bus with
bypass_iommu disabled and add explicit scope data in DMAR drhd structure.

/mnt/sdb/wxg/qemu-next/qemu/build/x86_64-softmmu/qemu-system-x86_64 \
 -machine q35,accel=kvm,default_bus_bypass_iommu=true \
 -cpu host \
 -m 16G \
 -smp 36,sockets=2,cores=18,threads=1 \
 -device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3 \
 -device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x4,bypass_iommu=true \
 -device pcie-root-port,port=0x1,chassis=1,id=pci.11,bus=pci.10,addr=0x0 \
 -device pcie-root-port,port=0x2,chassis=2,id=pci.21,bus=pci.20,addr=0x0 \
 -device virtio-scsi-pci,id=scsi0,bus=pci.11,addr=0x0 \
 -device virtio-scsi-pci,id=scsi1,bus=pci.21,addr=0x0 \
 -drive 
file=/mnt/sdb/wxg/fedora-48g.qcow2,format=qcow2,if=none,id=drive-scsi0-0-0-0,cache=none,aio=native
 \
 -device 
scsi-hd,bus=scsi1.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=1
 \
 -device intel-iommu \
 -nographic \

And we get the guest configuration:

~ lspci -vt
-+-[0000:20]---00.0-[21]----00.0  Red Hat, Inc. Virtio SCSI
 +-[0000:10]---00.0-[11]----00.0  Red Hat, Inc. Virtio SCSI
 \-[0000:00]-+-00.0  Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
             +-01.0  Device 1234:1111
             +-02.0  Intel Corporation 82574L Gigabit Network Connection
             +-03.0  Red Hat, Inc. QEMU PCIe Expander bridge
             +-04.0  Red Hat, Inc. QEMU PCIe Expander bridge
             +-1f.0  Intel Corporation 82801IB (ICH9) LPC Interface Controller
             +-1f.2  Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA 
Controller [AHCI mode]
             \-1f.3  Intel Corporation 82801I (ICH9 Family) SMBus Controller

With bypass_iommu enabled on root bus, the attached devices will bypass iommu:

/sys/class/iommu/dmar0
├── devices
│   ├── 0000:10:00.0 -> ../../../../pci0000:10/0000:10:00.0
│   └── 0000:11:00.0 -> ../../../../pci0000:10/0000:10:00.0/0000:11:00.0

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-8-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: dec2f5636e9b590a5d2d2e20e821e9899f7c63bf
      
https://github.com/qemu/qemu/commit/dec2f5636e9b590a5d2d2e20e821e9899f7c63bf
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/i386/acpi-build.c

  Log Message:
  -----------
  hw/i386/acpi-build: Add IVRS support to bypass iommu

Check bypass_iommu to exclude the devices which will bypass iommu.

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-9-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 732de3e72d8872b34b82afb3a5b063b2e0c1c85b
      
https://github.com/qemu/qemu/commit/732de3e72d8872b34b82afb3a5b063b2e0c1c85b
  Author: Xingang Wang <wangxingang5@huawei.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    A docs/bypass-iommu.txt

  Log Message:
  -----------
  docs: Add documentation for iommu bypass

Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Message-Id: <1625748919-52456-10-git-send-email-wangxingang5@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: 1e08fd0a465d70ad30d2928c66537c816f0af7f8
      
https://github.com/qemu/qemu/commit/1e08fd0a465d70ad30d2928c66537c816f0af7f8
  Author: Arseny Krasnov <arseny.krasnov@kaspersky.com>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M hw/virtio/vhost-vsock.c

  Log Message:
  -----------
  vhost-vsock: SOCK_SEQPACKET feature bit support

This adds processing of VIRTIO_VSOCK_F_SEQPACKET features bit. Guest
negotiates it with vhost, thus both will know that SOCK_SEQPACKET
supported by peer.

Signed-off-by: Arseny Krasnov <arseny.krasnov@kaspersky.com>
Message-Id: <20210622144747.2949134-1-arseny.krasnov@kaspersky.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>


  Commit: a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf
      
https://github.com/qemu/qemu/commit/a97fca4ceb9d9b10aa8b582e817a5ee6c42ffbaf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    A docs/bypass-iommu.txt
    M hw/acpi/acpi-x86-stub.c
    M hw/acpi/ich9.c
    M hw/acpi/pcihp.c
    M hw/acpi/piix4.c
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/core/machine.c
    M hw/i386/acpi-build.c
    M hw/i386/acpi-build.h
    M hw/i386/pc.c
    M hw/i386/pc_q35.c
    M hw/pci-bridge/pci_expander_bridge.c
    M hw/pci-host/q35.c
    M hw/pci/pci.c
    M hw/pci/pci_host.c
    M hw/pci/pcie.c
    M hw/pci/pcie_port.c
    M hw/virtio/Kconfig
    M hw/virtio/meson.build
    A hw/virtio/vhost-user-i2c-pci.c
    A hw/virtio/vhost-user-i2c.c
    M hw/virtio/vhost-vsock.c
    M include/hw/acpi/ich9.h
    M include/hw/acpi/pcihp.h
    M include/hw/arm/virt.h
    M include/hw/i386/pc.h
    M include/hw/pci/pci.h
    M include/hw/pci/pci_host.h
    M include/hw/pci/pcie_port.h
    A include/hw/virtio/vhost-user-i2c.h
    M qemu-options.hx
    M tests/data/acpi/q35/DSDT
    M tests/data/acpi/q35/DSDT.acpihmat
    M tests/data/acpi/q35/DSDT.bridge
    M tests/data/acpi/q35/DSDT.cphp
    M tests/data/acpi/q35/DSDT.dimmpxm
    M tests/data/acpi/q35/DSDT.ipmibt
    M tests/data/acpi/q35/DSDT.memhp
    M tests/data/acpi/q35/DSDT.mmio64
    M tests/data/acpi/q35/DSDT.nohpet
    M tests/data/acpi/q35/DSDT.numamem
    M tests/data/acpi/q35/DSDT.tis

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/mst/tags/for_upstream3' into staging

pc,pci,virtio: lots of new features

Lots of last minute stuff.

vhost-user-i2c.
vhost-vsock SOCK_SEQPACKET support.
IOMMU bypass.
ACPI based pci hotplug.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Fri 16 Jul 2021 16:11:27 BST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream3:
  vhost-vsock: SOCK_SEQPACKET feature bit support
  docs: Add documentation for iommu bypass
  hw/i386/acpi-build: Add IVRS support to bypass iommu
  hw/i386/acpi-build: Add DMAR support to bypass iommu
  hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3
  hw/pci: Add pci_bus_range() to get PCI bus number range
  hw/i386: Add a default_bus_bypass_iommu pc machine option
  hw/arm/virt: Add default_bus_bypass_iommu machine option
  hw/pxb: Add a bypass iommu property
  hw/pci/pci_host: Allow PCI host to bypass iommu
  docs: Add '-device intel-iommu' entry
  hw/virtio: add vhost-user-i2c-pci boilerplate
  hw/virtio: add boilerplate for vhost-user-i2c device
  bios-tables-test: Update golden binaries
  hw/acpi/ich9: Set ACPI PCI hot-plug as default on Q35
  bios-tables-test: Allow changes in DSDT ACPI tables
  hw/pci/pcie: Do not set HPC flag if acpihp is used
  hw/acpi/ich9: Enable ACPI PCI hot-plug
  hw/i386/acpi-build: Add ACPI PCI hot-plug methods to Q35

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/9ad4c7c9b63f...a97fca4ceb9d



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