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[Qemu-commits] [qemu/qemu] b4cb17: target/riscv: pmp: Fix some typos


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] b4cb17: target/riscv: pmp: Fix some typos
Date: Fri, 16 Jul 2021 02:56:01 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b4cb178efbafaff22558c9cad7d2e1b8f351bdc3
      
https://github.com/qemu/qemu/commit/b4cb178efbafaff22558c9cad7d2e1b8f351bdc3
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: pmp: Fix some typos

%s/CSP/CSR
%s/thie/the

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627115716.3552-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 232a2c8c85541e3b491f61b90f151f1edcdb3944
      
https://github.com/qemu/qemu/commit/232a2c8c85541e3b491f61b90f151f1edcdb3944
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: csr: Remove redundant check in fp csr read/write routines

The following check:

    if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
        return -RISCV_EXCP_ILLEGAL_INST;
    }

is redundant in fflags/frm/fcsr read/write routines, as the check was
already done in fs().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627120604.11116-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d3745751009bc7c56741ea04c4d3ca5619f845f2
      
https://github.com/qemu/qemu/commit/d3745751009bc7c56741ea04c4d3ca5619f845f2
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M docs/system/riscv/sifive_u.rst

  Log Message:
  -----------
  docs/system: riscv: Fix CLINT name in the sifive_u doc

It's Core *Local* Interruptor, not 'Level'.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 85198f189e41c9d9ebe340d2feecf7d668499bc4
      
https://github.com/qemu/qemu/commit/85198f189e41c9d9ebe340d2feecf7d668499bc4
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    A docs/system/riscv/virt.rst
    M docs/system/target-riscv.rst

  Log Message:
  -----------
  docs/system: riscv: Add documentation for virt machine

This adds detailed documentation for RISC-V `virt` machine,
including the following information:

  - Supported devices
  - Hardware configuration information
  - Boot options
  - Running Linux kernel
  - Running U-Boot

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bc083a51cafff73ad6113fcc81f2f40639d7c8c6
      
https://github.com/qemu/qemu/commit/bc083a51cafff73ad6113fcc81f2f40639d7c8c6
  Author: Jose Martins <josemartins90@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: hardwire bits in hideleg and hedeleg

The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
 - Improve indentation
 - Convert delegable_excps to a #define to avoid failures with GCC 8
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6165dcb55f0ab4b2a241e49859ce6262157887e7
      
https://github.com/qemu/qemu/commit/6165dcb55f0ab4b2a241e49859ce6262157887e7
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M docs/system/riscv/microchip-icicle-kit.rst

  Log Message:
  -----------
  docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot

This adds a new section in the documentation to demonstrate how to
use the new direct kernel boot feature for Microchip Icicle Kit,
other than the HSS bootflow, using an upstream U-Boot v2021.07 image
as an example.

It also updates the truth table to have a new '-dtb' column which is
required by direct kernel boot.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706095045.1917913-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 074ca702e64dcea15c9c3b2c1931351cf397debe
      
https://github.com/qemu/qemu/commit/074ca702e64dcea15c9c3b2c1931351cf397debe
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Correct the CLINT timebase frequency

At present the CLINT timebase frequency is set to 10MHz on sifive_u,
but on the real hardware the timebase frequency is 1Mhz.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 623d53cb017fc1506eed71dd01792bef1062a877
      
https://github.com/qemu/qemu/commit/623d53cb017fc1506eed71dd01792bef1062a877
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned

Currently the firmware dynamic info (fw_dyn) is put right after
the reset vector, which is not 8-byte aligned on RV64. OpenSBI
fw_dynamic uses ld to read contents from 'struct fw_dynamic_info',
which expects fw_dyn to be on the 8-byte boundary, otherwise the
misaligned load exception may happen. Fortunately this does not
cause any issue on QEMU, as QEMU does support misaligned load.

RV32 does not have any issue as it is 4-byte aligned already.
Change to make sure it is 8-byte aligned which works for both
RV32 and RV64.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210708143319.10441-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 24bfb98d0642aa7c5e8564750de34448f2f39ec5
      
https://github.com/qemu/qemu/commit/24bfb98d0642aa7c5e8564750de34448f2f39ec5
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/char/ibex_uart.c

  Log Message:
  -----------
  char: ibex_uart: Update the register layout

Update the register layout to match the latest OpenTitan bitstream.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
25c8377d32f3e0f0a1a862c8a5092f8a9e3f9928.1625801868.git.alistair.francis@wdc.com


  Commit: 5ee257649f1a69d952c56f0a7084653e51971ce5
      
https://github.com/qemu/qemu/commit/5ee257649f1a69d952c56f0a7084653e51971ce5
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com


  Commit: bb7e0cde3cbd59e8b7d6e0e9c67e11f76cbe64d4
      
https://github.com/qemu/qemu/commit/bb7e0cde3cbd59e8b7d6e0e9c67e11f76cbe64d4
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: opentitan: Add the flash alias

OpenTitan has an alias of flash avaliable which is called virtual flash.
Add support for that in the QEMU model.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com


  Commit: b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc
      
https://github.com/qemu/qemu/commit/b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-07-15 (Thu, 15 Jul 2021)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  hw/riscv/boot: Check the error of fdt_pack()

Coverity reports that we don't check the error result of fdt_pack(), so
let's save the result and assert that it is 0.

Fixes: Coverity CID 1458136
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
07325315b49d5555269f76094e4bc5296e0643b9.1626303527.git.alistair.francis@wdc.com


  Commit: 65388f404492daac86e02980d10ae84c694870b3
      
https://github.com/qemu/qemu/commit/65388f404492daac86e02980d10ae84c694870b3
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-16 (Fri, 16 Jul 2021)

  Changed paths:
    M docs/system/riscv/microchip-icicle-kit.rst
    M docs/system/riscv/sifive_u.rst
    A docs/system/riscv/virt.rst
    M docs/system/target-riscv.rst
    M hw/char/ibex_uart.c
    M hw/riscv/boot.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_u.c
    M include/hw/riscv/opentitan.h
    M target/riscv/csr.c
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210715' into staging

Fourth RISC-V PR for 6.1 release

 - Code cleanups
 - Documentation improvements
 - Hypervisor extension improvements with hideleg and hedeleg
 - sifive_u fixes
 - OpenTitan register layout updates
 - Fix coverity issue

# gpg: Signature made Thu 15 Jul 2021 08:14:00 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210715:
  hw/riscv/boot: Check the error of fdt_pack()
  hw/riscv: opentitan: Add the flash alias
  hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
  char: ibex_uart: Update the register layout
  hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned
  hw/riscv: sifive_u: Correct the CLINT timebase frequency
  docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot
  target/riscv: hardwire bits in hideleg and hedeleg
  docs/system: riscv: Add documentation for virt machine
  docs/system: riscv: Fix CLINT name in the sifive_u doc
  target/riscv: csr: Remove redundant check in fp csr read/write routines
  target/riscv: pmp: Fix some typos

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/bd306cfeeece...65388f404492



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