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[Qemu-commits] [qemu/qemu] 080ac3: target/i386: Tidy hw_breakpoint_remov

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 080ac3: target/i386: Tidy hw_breakpoint_remove
Date: Wed, 14 Jul 2021 08:25:12 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 080ac33542d7ee042710f05c023fe5e3a70b9ebf
      
https://github.com/qemu/qemu/commit/080ac33542d7ee042710f05c023fe5e3a70b9ebf
  Author: Dmitry Voronetskiy <davoronetskiy@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/i386/tcg/sysemu/bpt_helper.c

  Log Message:
  -----------
  target/i386: Tidy hw_breakpoint_remove

Since cpu_breakpoint and cpu_watchpoint are in a union,
the code should access only one of them.

Signed-off-by: Dmitry Voronetskiy <davoronetskiy@gmail.com>
Message-Id: <20210613180838.21349-1-davoronetskiy@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 505910a6e2d5ca374cbbed874251952d113c7919
      
https://github.com/qemu/qemu/commit/505910a6e2d5ca374cbbed874251952d113c7919
  Author: Ziqiao Kong <ziqiaokong@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/i386/tcg/translate.c

  Log Message:
  -----------
  target/i386: Trivial code motion and code style fix

A new pair of braces has to be added to declare variables in the case block.
The code style is also fixed according to the transalte.c itself during the
code motion.

Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: bbdda9b74f289328e9ee7be28bb472350dc84028
      
https://github.com/qemu/qemu/commit/bbdda9b74f289328e9ee7be28bb472350dc84028
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/i386/tcg/fpu_helper.c

  Log Message:
  -----------
  target/i386: Split out do_fninit

Do not call helper_fninit directly from helper_xrstor.
Do call the new helper from do_fsave.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 84abdd7d271c2df69a9d394be093efd885da7a4c
      
https://github.com/qemu/qemu/commit/84abdd7d271c2df69a9d394be093efd885da7a4c
  Author: Ziqiao Kong <ziqiaokong@gmail.com>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/i386/cpu.h
    M target/i386/tcg/fpu_helper.c
    M target/i386/tcg/translate.c

  Log Message:
  -----------
  target/i386: Correct implementation for FCS, FIP, FDS and FDP

Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8.
Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by
design in this patch and will be added along with TCG features flag
in a separate patch later.

Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com>
[rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 492f85b92adf4e6fbe15b9cd4a36d5e0c3f2c44a
      
https://github.com/qemu/qemu/commit/492f85b92adf4e6fbe15b9cd4a36d5e0c3f2c44a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/alpha/translate.c

  Log Message:
  -----------
  target/alpha: Store set into rx flag

A paste-o meant that we wrote back the existing value
of the RX flag rather than changing it to TMP.

Use tcg_constant_i64 while we're at it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3e646c3a3cfb1ce9522c230c2cbbafaf42f0a9c5
      
https://github.com/qemu/qemu/commit/3e646c3a3cfb1ce9522c230c2cbbafaf42f0a9c5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/alpha/translate.c

  Log Message:
  -----------
  target/alpha: Use dest_sink for HW_RET temporary

This temp is automatically freed, just like ctx->lit.
But we're about to remove ctx->lit, so use sink instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 212c88c0c78b1b2027b91d0669b92c49d921e91c
      
https://github.com/qemu/qemu/commit/212c88c0c78b1b2027b91d0669b92c49d921e91c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/alpha/translate.c

  Log Message:
  -----------
  target/alpha: Use tcg_constant_i64 for zero and lit

These constant temps do not need to be freed, and
therefore need less bookkeeping from tcg producers.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 904bd855d38f8deb3f85a63d19475bb4a0c0d1a4
      
https://github.com/qemu/qemu/commit/904bd855d38f8deb3f85a63d19475bb4a0c0d1a4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/alpha/translate.c

  Log Message:
  -----------
  target/alpha: Use tcg_constant_* elsewhere

Replace the remaining uses of tcg_const_*.  These uses are
all local, with the allocate and free close together.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: af42d3540179d48ee31bd421d00100c26bfb63e3
      
https://github.com/qemu/qemu/commit/af42d3540179d48ee31bd421d00100c26bfb63e3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Use tcg_constant_*

Replace uses of tcg_const_* allocate and free close together
with tcg_constant_*.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4d10fa0ff901b055ca75f6986974609bc99820dd
      
https://github.com/qemu/qemu/commit/4d10fa0ff901b055ca75f6986974609bc99820dd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Use tcg_constant_tl for dc->R0

The temp allocated for tcg_const_tl is auto-freed at branches,
but pure constants are not.  So we can remove the extra hoop
jumping in trans_l_swa.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 118671f02faf4d67f283731eafc96bb72b125431
      
https://github.com/qemu/qemu/commit/118671f02faf4d67f283731eafc96bb72b125431
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Cache constant 0 in DisasContext

We are virtually certain to have fetched constant 0 once, at the
beginning of the TB, so we might as well use it elsewhere.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e0efc48fbc6ed9f308fbbff394c5c1044067909f
      
https://github.com/qemu/qemu/commit/e0efc48fbc6ed9f308fbbff394c5c1044067909f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Use dc->zero in gen_add, gen_addc

We still need the t0 temporary for computing overflow,
but we do not need to initialize it to zero first.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 29dd6f644a7b8a5a9a8bc249a25d50bc0e266da9
      
https://github.com/qemu/qemu/commit/29dd6f644a7b8a5a9a8bc249a25d50bc0e266da9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Use tcg_constant_*

Replace uses of tcg_const_* with the allocate and free close together.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6e94937a54c6ef80c3f523d8560c8b6521e6c79c
      
https://github.com/qemu/qemu/commit/6e94937a54c6ef80c3f523d8560c8b6521e6c79c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-07-13 (Tue, 13 Jul 2021)

  Changed paths:
    M target/hppa/translate.c

  Log Message:
  -----------
  target/hppa: Clean up DisasCond

The a0_is_n flag is redundant with comparing a0 to cpu_psw_n.
The a1_is_0 flag can be removed by initializing a1 to $0,
which also means that cond_prep can be removed entirely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 20a96761793ffbc078811c755096403ea9792119
      
https://github.com/qemu/qemu/commit/20a96761793ffbc078811c755096403ea9792119
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-14 (Wed, 14 Jul 2021)

  Changed paths:
    M target/alpha/translate.c
    M target/hppa/translate.c
    M target/i386/cpu.h
    M target/i386/tcg/fpu_helper.c
    M target/i386/tcg/sysemu/bpt_helper.c
    M target/i386/tcg/translate.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-misc-20210713' 
into staging

Cleanup alpha, hppa, or1k wrt tcg_constant_tl.
Implement x86 fcs:fip, fds:fdp.
Trivial x86 watchpoint cleanup.

# gpg: Signature made Tue 13 Jul 2021 17:36:29 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-misc-20210713:
  target/hppa: Clean up DisasCond
  target/hppa: Use tcg_constant_*
  target/openrisc: Use dc->zero in gen_add, gen_addc
  target/openrisc: Cache constant 0 in DisasContext
  target/openrisc: Use tcg_constant_tl for dc->R0
  target/openrisc: Use tcg_constant_*
  target/alpha: Use tcg_constant_* elsewhere
  target/alpha: Use tcg_constant_i64 for zero and lit
  target/alpha: Use dest_sink for HW_RET temporary
  target/alpha: Store set into rx flag
  target/i386: Correct implementation for FCS, FIP, FDS and FDP
  target/i386: Split out do_fninit
  target/i386: Trivial code motion and code style fix
  target/i386: Tidy hw_breakpoint_remove

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/4aa2454d94cc...20a96761793f
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