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[Qemu-commits] [qemu/qemu] 46fd32: hw/pci-host: Rename Raven ASIC PCI br


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 46fd32: hw/pci-host: Rename Raven ASIC PCI bridge as raven.c
Date: Mon, 12 Jul 2021 11:56:39 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 46fd3201cb02d95f42f659121b13cf5e2633db1c
      
https://github.com/qemu/qemu/commit/46fd3201cb02d95f42f659121b13cf5e2633db1c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M MAINTAINERS
    M hw/pci-host/Kconfig
    M hw/pci-host/meson.build
    R hw/pci-host/prep.c
    A hw/pci-host/raven.c
    M hw/ppc/Kconfig

  Log Message:
  -----------
  hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

The ASIC PCI bridge chipset from Motorola is named 'Raven'.
This chipset is used in the PowerPC Reference Platform (PReP),
but not restricted to it. Rename it accordingly.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210417103028.601124-5-f4bug@amsat.org>


  Commit: 64e73920470f3ab848458cd965af3590430d321c
      
https://github.com/qemu/qemu/commit/64e73920470f3ab848458cd965af3590430d321c
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/pci-host/raven.c

  Log Message:
  -----------
  hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition

Rather than using the magic 0x80000000 number for the PCI I/O BAR
physical address on the main system bus, use a definition.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210417103028.601124-6-f4bug@amsat.org>


  Commit: 2d4ab117bebb90ad7e7e65629f99f9e82ba32053
      
https://github.com/qemu/qemu/commit/2d4ab117bebb90ad7e7e65629f99f9e82ba32053
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)

Introduce the parallel logic opcodes:

 - PAND (Parallel AND)
 - POR  (Parallel OR)
 - PXOR (Parallel XOR)
 - PNOR (Parallel NOR)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-16-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 709324dc05a17755d43c315e43a8ec9da04fc37b
      
https://github.com/qemu/qemu/commit/709324dc05a17755d43c315e43a8ec9da04fc37b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)

Introduce the 'Parallel Subtract' opcodes:

 - PSUBB (Parallel Subtract Byte)
 - PSUBH (Parallel Subtract Halfword)
 - PSUBW (Parallel Subtract Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <820210309145653.743937-11-f4bug@amsat.org>


  Commit: 0bc6937296c39659f6d8f031a62748e815708b06
      
https://github.com/qemu/qemu/commit/0bc6937296c39659f6d8f031a62748e815708b06
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)

Introduce the PEXTUW opcode (Parallel Extend Upper from Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-12-f4bug@amsat.org>


  Commit: a9ea77f2dc5ee516adb7757e266e0d1790ddbf1a
      
https://github.com/qemu/qemu/commit/a9ea77f2dc5ee516adb7757e266e0d1790ddbf1a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)

Introduce the 'Parallel Extend Lower' opcodes:

 - PEXTLB (Parallel Extend Upper from Byte)
 - PEXTLH (Parallel Extend Upper from Halfword)
 - PEXTLW (Parallel Extend Upper from Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-13-f4bug@amsat.org>


  Commit: 82fbf9fc808b94dd8c5a1aafb19818620c5c4801
      
https://github.com/qemu/qemu/commit/82fbf9fc808b94dd8c5a1aafb19818620c5c4801
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)

Introduce the 'Parallel Compare for Equal' opcodes:

 - PCEQB (Parallel Compare for Equal Byte)
 - PCEQH (Parallel Compare for Equal Halfword)
 - PCEQW (Parallel Compare for Equal Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-14-f4bug@amsat.org>


  Commit: 8bd42c00f28447a84a4be5fffd39a2f9a92b5ac9
      
https://github.com/qemu/qemu/commit/8bd42c00f28447a84a4be5fffd39a2f9a92b5ac9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)

Introduce the 'Parallel Compare for Greater Than' opcodes:

 - PCGTB (Parallel Compare for Greater Than Byte)
 - PCGTH (Parallel Compare for Greater Than Halfword)
 - PCGTW (Parallel Compare for Greater Than Word)

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210309145653.743937-15-f4bug@amsat.org>


  Commit: 71c49f39b9965506fa32483f80980a4a0199d4f8
      
https://github.com/qemu/qemu/commit/71c49f39b9965506fa32483f80980a4a0199d4f8
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)

Introduce the PPACW opcode (Parallel Pack to Word).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-22-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: dce4808f74869577db21ef90a28061f9dc65c5d8
      
https://github.com/qemu/qemu/commit/dce4808f74869577db21ef90a28061f9dc65c5d8
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)

Introduce the PROT3W opcode (Parallel Rotate 3 Words).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-25-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: aaaa82a9f9975c59b72debb22bc92b8e1ab4ab10
      
https://github.com/qemu/qemu/commit/aaaa82a9f9975c59b72debb22bc92b8e1ab4ab10
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/translate.c
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce LQ opcode (Load Quadword)

Introduce the LQ opcode (Load Quadword) and remove unreachable code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-26-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 80ad6303577612451d56c84d079a8c5b7f21412d
      
https://github.com/qemu/qemu/commit/80ad6303577612451d56c84d079a8c5b7f21412d
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  target/mips/tx79: Introduce SQ opcode (Store Quadword)

Introduce the SQ opcode (Store Quadword).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-27-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: d859a77dbdeca288bd6679e33bf2a83a635349a0
      
https://github.com/qemu/qemu/commit/d859a77dbdeca288bd6679e33bf2a83a635349a0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M target/mips/tcg/sysemu/mips-semi.c

  Log Message:
  -----------
  target/mips: Rewrite UHI errno_mips() using switch statement

Linking on Haiku OS fails:

  
/boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld:
  error: 
libqemu-mips-softmmu.fa.p/target_mips_tcg_sysemu_mips-semi.c.o(.rodata) is too 
large (0xffff405a bytes)
  
/boot/system/develop/tools/bin/../lib/gcc/x86_64-unknown-haiku/8.3.0/../../../../x86_64-unknown-haiku/bin/ld:
  final link failed: memory exhausted
  collect2: error: ld returned 1 exit status

This is because the host_to_mips_errno[] uses errno as index,
for example:

  static const uint16_t host_to_mips_errno[] = {
      [ENAMETOOLONG] = 91,
      ...

and Haiku defines [*] ENAMETOOLONG as:

   12 /* Error baselines */
   13 #define B_GENERAL_ERROR_BASE              INT_MIN
   ..
   22 #define B_STORAGE_ERROR_BASE              (B_GENERAL_ERROR_BASE + 0x6000)
  ...
  106 #define B_NAME_TOO_LONG                   (B_STORAGE_ERROR_BASE + 4)
  ...
  211 #define ENAMETOOLONG                      
B_TO_POSIX_ERROR(B_NAME_TOO_LONG)

so the array ends up beeing indeed too big.

Since POSIX errno can't be use as indexes on Haiku,
rewrite errno_mips() using a switch statement.

[*] https://github.com/haiku/haiku/blob/r1beta3/headers/os/support/Errors.h#L130

Reported-by: Richard Zak <richard.j.zak@gmail.com>
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210706130723.1178961-1-f4bug@amsat.org>


  Commit: 85e411d7ff7d62a084f318f3956d48a644632d6c
      
https://github.com/qemu/qemu/commit/85e411d7ff7d62a084f318f3956d48a644632d6c
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: fix CAM descriptor entry index

Currently when a LOAD CAM command is executed the entries are loaded into the
CAM from memory in order which is incorrect. According to the datasheet the
first entry in the CAM descriptor is the entry index which means that each
descriptor may update any single entry in the CAM rather than the Nth entry.

Decode the CAM entry index and use it store the descriptor in the appropriate
slot in the CAM. This fixes the issue where the MacOS toolbox loads a single
CAM descriptor into the final slot in order to perform a loopback test which
must succeed before the Ethernet port is enabled.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210625065401.30170-10-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


  Commit: 197ade0d110deeef58a05c11adec100926813560
      
https://github.com/qemu/qemu/commit/197ade0d110deeef58a05c11adec100926813560
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: Replace address_space_rw(is_write=1) by address_space_write()

Replace address_space_rw(is_write=1) by address_space_write()
and remove pointless cast.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-2-f4bug@amsat.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 67b38ddfe58cbfb7c9c4a8d8b7efdc3fe7def41f
      
https://github.com/qemu/qemu/commit/67b38ddfe58cbfb7c9c4a8d8b7efdc3fe7def41f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-3-f4bug@amsat.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 8ac2ffb584590b0398ae4e1a08a0b5d209b6f250
      
https://github.com/qemu/qemu/commit/8ac2ffb584590b0398ae4e1a08a0b5d209b6f250
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: Store CAM registers as 16-bit

Per the DP83932C datasheet from July 1995:

  4.0 SONIC Registers
  4.1 THE CAM UNIT

    The Content Addressable Memory (CAM) consists of sixteen
    48-bit entries for complete address filtering of network
    packets. Each entry corresponds to a 48-bit destination
    address that is user programmable and can contain any
    combination of Multicast or Physical addresses. Each entry
    is partitioned into three 16-bit CAM cells accessible
    through CAM Address Ports (CAP 2, CAP 1 and CAP 0) with
    CAP0 corresponding to the least significant 16 bits of
    the Destination Address and CAP2 corresponding to the
    most significant bits.

Store the CAM registers as 16-bit as it simplifies the code.

Having now the CAM registers as arrays of 3 uint16_t, we can avoid
using the VMSTATE_BUFFER_UNSAFE macro by using VMSTATE_UINT16_2DARRAY
which is more appropriate. This breaks the migration stream however.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-5-f4bug@amsat.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 82adabf7e533a29fe5a122090c2bee523624330a
      
https://github.com/qemu/qemu/commit/82adabf7e533a29fe5a122090c2bee523624330a
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: Rewrite dp8393x_get() / dp8393x_put()

Instead of accessing N registers via a single address_space API
call using a temporary buffer (stored in the device state) and
updating each register, move the address_space call in the
register put/get. The load/store and word size checks are moved
to put/get too. This simplifies a bit, making the code easier
to read.

Co-developed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Co-developed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Message-Id: <20210710174954.2577195-8-f4bug@amsat.org>


  Commit: 39d9919f4b4c3e7f230efd7d845439d6d732dc89
      
https://github.com/qemu/qemu/commit/39d9919f4b4c3e7f230efd7d845439d6d732dc89
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-07-11 (Sun, 11 Jul 2021)

  Changed paths:
    M hw/net/dp8393x.c

  Log Message:
  -----------
  dp8393x: don't force 32-bit register access

Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set 
.impl.min_access_size
and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver which 
uses
32-bit accesses.

The problem with forcing the register access to 32-bit in this way is that 
since the
dp8393x uses 16-bit registers, a manual endian swap is required for devices on 
big
endian machines with 32-bit accesses.

For both access sizes and machine endians the QEMU memory API can do the right 
thing
automatically: all that is needed is to set .impl.min_access_size to 2 to 
declare that
the dp8393x implements 16-bit registers.

Normally .impl.max_access_size should also be set to 2, however that doesn't 
quite
work in this case since the register stride is specified using a (dynamic) 
it_shift
property which is applied during the MMIO access itself. The effect of this is 
that
for a 32-bit access the memory API performs 2 x 16-bit accesses, but the use of
it_shift within the MMIO access itself causes the register value to be repeated 
in both
the top 16-bits and bottom 16-bits. The Linux jazzsonic driver expects the 
stride to be
zero-extended up to access size and therefore fails to correctly detect the 
dp8393x
device due to the extra data in the top 16-bits.

The solution here is to remove .impl.max_access_size so that the memory API will
correctly zero-extend the 16-bit registers to the access size up to and 
including
it_shift. Since it_shift is never greater than 2 than this will always do the 
right
thing for both 16-bit and 32-bit accesses regardless of the machine endian, 
allowing
the manual endian swap code to be removed.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses")
Message-Id: <20210705214929.17222-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Finn Thain <fthain@linux-m68k.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


  Commit: 552fda48e095c16a14c9d275b4fdc5c392c386cf
      
https://github.com/qemu/qemu/commit/552fda48e095c16a14c9d275b4fdc5c392c386cf
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-07-12 (Mon, 12 Jul 2021)

  Changed paths:
    M MAINTAINERS
    M hw/net/dp8393x.c
    M hw/pci-host/Kconfig
    M hw/pci-host/meson.build
    R hw/pci-host/prep.c
    A hw/pci-host/raven.c
    M hw/ppc/Kconfig
    M target/mips/tcg/sysemu/mips-semi.c
    M target/mips/tcg/translate.c
    M target/mips/tcg/tx79.decode
    M target/mips/tcg/tx79_translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/philmd/tags/mips-20210711' into staging

MIPS patches queue

- Rename Raven ASIC PCI bridge, add PCI_IO_BASE_ADDR definition
- Various Toshiba TX79 opcodes implemented
- Rewrite UHI errno_mips() using switch statement
- Few fixes and improvements in the SONIC model (dp8393x)

# gpg: Signature made Sun 11 Jul 2021 22:12:49 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210711:
  dp8393x: don't force 32-bit register access
  dp8393x: Rewrite dp8393x_get() / dp8393x_put()
  dp8393x: Store CAM registers as 16-bit
  dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition
  dp8393x: Replace address_space_rw(is_write=1) by address_space_write()
  dp8393x: fix CAM descriptor entry index
  target/mips: Rewrite UHI errno_mips() using switch statement
  target/mips/tx79: Introduce SQ opcode (Store Quadword)
  target/mips/tx79: Introduce LQ opcode (Load Quadword)
  target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words)
  target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word)
  target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than)
  target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal)
  target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower)
  target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word)
  target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract)
  target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic)
  hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition
  hw/pci-host: Rename Raven ASIC PCI bridge as raven.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/bd38ae26cea0...552fda48e095



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