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[Qemu-commits] [qemu/qemu] c11dc1: target/ppc: Introduce ppc_interrupts_
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] c11dc1: target/ppc: Introduce ppc_interrupts_little_endian() |
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Date: |
Sat, 10 Jul 2021 08:11:57 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: c11dc15d3aabb9dab04d9d2767e1b227d2b9085d
https://github.com/qemu/qemu/commit/c11dc15d3aabb9dab04d9d2767e1b227d2b9085d
Author: Greg Kurz <groug@kaod.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/arch_dump.c
M target/ppc/cpu.h
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Introduce ppc_interrupts_little_endian()
PowerPC CPUs use big endian by default but starting with POWER7,
server grade CPUs use the ILE bit of the LPCR special purpose
register to decide on the endianness to use when handling
interrupts. This gives a clue to QEMU on the endianness the
guest kernel is running, which is needed when generating an
ELF dump of the guest or when delivering an FWNMI machine
check interrupt.
Commit 382d2db62bcb ("target-ppc: Introduce callback for interrupt
endianness") added a class method to PowerPCCPUClass to modelize
this : default implementation returns a fixed "big endian" value,
while POWER7 and newer do the LPCR_ILE check. This is suboptimal
as it forces to implement the method for every new CPU family, and
it is very unlikely that this will ever be different than what we
have today.
We basically only have three cases to consider:
a) CPU doesn't have an LPCR => big endian
b) CPU has an LPCR but doesn't support the ILE bit => big endian
c) CPU has an LPCR and supports the ILE bit => little or big endian
Instead of class methods, introduce an inline helper that checks the
ILE bit in the LPCR_MASK to decide on the outcome. The new helper
words little endian instead of big endian. This allows to drop a !
operator in ppc_cpu_do_fwnmi_machine_check().
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20210622140926.677618-2-groug@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 642f6f59cda39a1f67276f4a5f74876975b6ee34
https://github.com/qemu/qemu/commit/642f6f59cda39a1f67276f4a5f74876975b6ee34
Author: Greg Kurz <groug@kaod.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Drop PowerPCCPUClass::interrupts_big_endian()
This isn't used anymore.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <20210622140926.677618-3-groug@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 7381c5d11fe9a03ad3bf2e5700e96acc5cafe218
https://github.com/qemu/qemu/commit/7381c5d11fe9a03ad3bf2e5700e96acc5cafe218
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: tune rtas-size
QEMU reserves space for RTAS via /rtas/rtas-size which tells the client
how much space the RTAS requires to work which includes the RTAS binary
blob implementing RTAS runtime. Because pseries supports FWNMI which
requires plenty of space, QEMU reserves more than 2KB which is
enough for the RTAS blob as it is just 20 bytes (under QEMU).
Since FWNMI reset delivery was added, RTAS_SIZE macro is not used anymore.
This replaces RTAS_SIZE with RTAS_MIN_SIZE and uses it in
the /rtas/rtas-size calculation to account for the RTAS blob.
Fixes: 0e236d347790 ("ppc/spapr: Implement FWNMI System Reset delivery")
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20210622070336.1463250-1-aik@ozlabs.ru>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: db20cc2c563bfa259f7574a064190cf6456861f6
https://github.com/qemu/qemu/commit/db20cc2c563bfa259f7574a064190cf6456861f6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/cpu-qom.h
M target/ppc/cpu_init.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Remove PowerPCCPUClass.handle_mmu_fault
Instead, use a switch on env->mmu_model. This avoids some
replicated information in cpu setup.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-2-bruno.larsen@eldorado.org.br>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 1b4d1cb31a886418635e288f89b2da24fd091c55
https://github.com/qemu/qemu/commit/1b4d1cb31a886418635e288f89b2da24fd091c55
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
Log Message:
-----------
target/ppc: Use MMUAccessType with *_handle_mmu_fault
These changes were waiting until we didn't need to match
the function type of PowerPCCPUClass.handle_mmu_fault.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-3-bruno.larsen@eldorado.org.br>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 42a611240e110c126dab318d52d9ca760b9ff01c
https://github.com/qemu/qemu/commit/42a611240e110c126dab318d52d9ca760b9ff01c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Push real-mode handling into ppc_radix64_xlate
This removes some incomplete duplication between
ppc_radix64_handle_mmu_fault and ppc_radix64_get_phys_page_debug.
The former was correct wrt SPR_HRMOR and the latter was not.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-4-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 077a370499bb100237e291da9a06e6adbcd89335
https://github.com/qemu/qemu/commit/077a370499bb100237e291da9a06e6adbcd89335
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-radix64.c
Log Message:
-----------
target/ppc: Use bool success for ppc_radix64_xlate
Instead of returning non-zero for failure, return true for success.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-5-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 1a8c647bbd72f70c2cd8d369b3aa3e71a57ac3d8
https://github.com/qemu/qemu/commit/1a8c647bbd72f70c2cd8d369b3aa3e71a57ac3d8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash64.c
Log Message:
-----------
target/ppc: Split out ppc_hash64_xlate
Mirror the interface of ppc_radix64_xlate, putting all of
the logic for hash64 translation into a single function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-6-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 6c3c873c63830eb89a5776486af0f32858f62938
https://github.com/qemu/qemu/commit/6c3c873c63830eb89a5776486af0f32858f62938
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash32.c
Log Message:
-----------
target/ppc: Split out ppc_hash32_xlate
Mirror the interface of ppc_radix64_xlate, putting all of
the logic for hash32 translation into a single entry point.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-7-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: af44a1423691b6c93327fccfef20a5c5cbf8e517
https://github.com/qemu/qemu/commit/af44a1423691b6c93327fccfef20a5c5cbf8e517
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Split out ppc_jumbo_xlate
Mirror the interface of ppc_radix64_xlate (mostly), putting all
of the logic for older mmu translation into a single entry point.
For booke, we need to add mmu_idx to the xlate-style interface.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-8-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 51806b545834e0902dd2d17d1f66c7a2d83422f3
https://github.com/qemu/qemu/commit/51806b545834e0902dd2d17d1f66c7a2d83422f3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Introduce ppc_xlate
Create one common dispatch for all of the ppc_*_xlate functions.
Use ppc64_v3_radix to directly dispatch between ppc_radix64_xlate
and ppc_hash64_xlate.
Remove the separate *_handle_mmu_fault and *_get_phys_page_debug
functions, using common code for ppc_cpu_tlb_fill and
ppc_cpu_get_phys_page_debug.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-9-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: cbf35bac39265f278863f9452ceb9ad69cc311ef
https://github.com/qemu/qemu/commit/cbf35bac39265f278863f9452ceb9ad69cc311ef
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Restrict ppc_cpu_tlb_fill to TCG
This function is used by TCGCPUOps, and is thus TCG specific.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210621125115.67717-10-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 26ba91db6c0fea5ff6a696e32fc532af32f6629b
https://github.com/qemu/qemu/commit/26ba91db6c0fea5ff6a696e32fc532af32f6629b
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Fix compilation with DUMP_PAGE_TABLES debug option
../target/ppc/mmu_helper.c: In function 'get_segment_6xx_tlb':
../target/ppc/mmu_helper.c:514:46: error: passing argument 1 of
'ppc_hash32_hpt_mask' from incompatible pointer type
[-Werror=incompatible-pointer-types]
514 | ppc_hash32_hpt_mask(env) + 0x80);
| ^~~
| |
| CPUPPCState *
Fixes: 36778660d7 ("target/ppc: Eliminate htab_base and htab_mask variables")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210702215235.1941771-2-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: d3841fce0d5cf474a5f03eec07226bb300d75a9b
https://github.com/qemu/qemu/commit/d3841fce0d5cf474a5f03eec07226bb300d75a9b
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Fix compilation with FLUSH_ALL_TLBS debug option
../target/ppc/mmu_helper.c: In function 'helper_store_ibatu':
../target/ppc/mmu_helper.c:1802:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1802 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function 'helper_store_dbatu':
../target/ppc/mmu_helper.c:1838:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1838 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function 'helper_store_601_batu':
../target/ppc/mmu_helper.c:1874:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1874 | PowerPCCPU *cpu = env_archcpu(env);
| ^~~
../target/ppc/mmu_helper.c: In function 'helper_store_601_batl':
../target/ppc/mmu_helper.c:1919:17: error: unused variable 'cpu'
[-Werror=unused-variable]
1919 | PowerPCCPU *cpu = env_archcpu(env);
Fixes: db70b31144 ("target/ppc: Use env_cpu, env_archcpu")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210702215235.1941771-3-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: ba1b5df070bb4cf1632aaefa4e17d42881d49988
https://github.com/qemu/qemu/commit/ba1b5df070bb4cf1632aaefa4e17d42881d49988
Author: Fabiano Rosas <farosas@linux.ibm.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
Log Message:
-----------
target/ppc: Fix compilation with DEBUG_BATS debug option
../target/ppc/mmu-hash32.c: In function 'ppc_hash32_bat_lookup':
../target/ppc/mmu-hash32.c:204:13: error: 'BATu' undeclared (first use in this
function);
204 | BATu = &BATut[i];
| ^~~~
| BATut
../target/ppc/mmu-hash32.c:205:13: error: 'BATl' undeclared (first use in this
function);
205 | BATl = &BATlt[i];
| ^~~~
| BATlt
../target/ppc/mmu-hash32.c:206:13: error: 'BEPIu' undeclared (first use in this
function)
206 | BEPIu = *BATu & BATU32_BEPIU;
| ^~~~~
../target/ppc/mmu-hash32.c:206:29: error: 'BATU32_BEPIU' undeclared (first use
in this function);
206 | BEPIu = *BATu & BATU32_BEPIU;
| ^~~~~~~~~~~~
| BATU32_BEPI
../target/ppc/mmu-hash32.c:207:13: error: 'BEPIl' undeclared (first use in this
function)
207 | BEPIl = *BATu & BATU32_BEPIL;
| ^~~~~
../target/ppc/mmu-hash32.c:207:29: error: 'BATU32_BEPIL' undeclared (first use
in this function);
207 | BEPIl = *BATu & BATU32_BEPIL;
| ^~~~~~~~~~~~
| BATU32_BEPI
../target/ppc/mmu-hash32.c:208:13: error: 'bl' undeclared (first use in this
function)
208 | bl = (*BATu & 0x00001FFC) << 15;
| ^~
Fixes: 9813279664 ("target-ppc: Disentangle BAT code for 32-bit hash MMUs")
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210702215235.1941771-4-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 3f9f76d5bb27c3700ae1d5336e8921f842caad2e
https://github.com/qemu/qemu/commit/3f9f76d5bb27c3700ae1d5336e8921f842caad2e
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-book3s-v3.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: fix address translation bug for radix mmus
This commit attempts to fix a technical hiccup first mentioned by Richard
Henderson in
https://lists.nongnu.org/archive/html/qemu-devel/2021-05/msg06247.html
To sumarize the hiccup here, when radix-style mmus are translating an
address, they might need to call a second level of translation, with
hypervisor privileges. However, the way it was being done up until
this point meant that the second level translation had the same
privileges as the first level. It could lead to a bug in address
translation when running KVM inside a TCG guest, but this bug was never
experienced by users, so this isn't as much a bug fix as it is a
correctness cleanup.
This patch attempts that cleanup by making radix64_*_xlate functions
receive the mmu_idx, and passing one with the correct permission for the
second level translation.
The mmuidx macros added by this patch are only correct for non-bookE
mmus, because BookE style set the IS and DS bits inverted and there
might be other subtle differences. However, there doesn't seem to be
BookE cpus that have radix-style mmus, so we left a comment there to
document the issue, in case a machine does have that and was missed.
As part of this cleanup, we now need to send the correct mmmu_idx
when calling get_phys_page_debug, otherwise we might not be able to see the
memory that the CPU could
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210628133610.1143-2-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 03695a9870662ddaeef2e4f2129df31beb6e73bd
https://github.com/qemu/qemu/commit/03695a9870662ddaeef2e4f2129df31beb6e73bd
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: changed ppc_hash64_xlate to use mmu_idx
Changed hash64 address translation to use the supplied mmu_idx instead
of using the one stored in the msr, for parity purposes (other book3s
MMUs already use it).
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210628133610.1143-4-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: a97c4d3c1e55f3098549bc4481f58a91a5834620
https://github.com/qemu/qemu/commit/a97c4d3c1e55f3098549bc4481f58a91a5834620
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-book3s-v3.h
A target/ppc/mmu-books.h
Log Message:
-----------
target/ppc: introduce mmu-books.h
Intrudoce a header common to all BookS MMUs, that can hold code that is
common to hash32 and book3s-v3 MMUs.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210706150316.21005-2-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: d423baf9b48cc4749e5f7d77214a089651bc3325
https://github.com/qemu/qemu/commit/d423baf9b48cc4749e5f7d77214a089651bc3325
Author: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: change ppc_hash32_xlate to use mmu_idx
Changed hash32 address translation to use the supplied mmu_idx, instead
of using what was stored in the msr, for parity purposes (radix64
already uses that) and for conceptual correctness, all the relevant
functions should always use the supplied mmu_idx, as there are no
guarantees that the mmu_idx stored in the CPU variable will not desync.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20210706150316.21005-3-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: a0c3747e14689583b84a6c15b80e7bc2209111be
https://github.com/qemu/qemu/commit/a0c3747e14689583b84a6c15b80e7bc2209111be
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M pc-bios/u-boot.e500
M roms/u-boot
Log Message:
-----------
roms/u-boot: Bump ppce500 u-boot to v2021.07 to add eTSEC support
Update the QEMU shipped u-boot.e500 image built from U-Boot mainline
v2021.07 release, which added eTSEC support to the QEMU ppce500 target,
via the following U-Boot series:
http://patchwork.ozlabs.org/project/uboot/list/?series=233875&state=*
The cross-compilation toolchain used to build the U-Boot image is:
https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/10.1.0/x86_64-gcc-10.1.0-nolibc-powerpc-linux.tar.xz
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: ea41397055f6dec68d3357df412f9f5fb3d89f84
https://github.com/qemu/qemu/commit/ea41397055f6dec68d3357df412f9f5fb3d89f84
Author: Bin Meng <bmeng.cn@gmail.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M docs/system/ppc/ppce500.rst
Log Message:
-----------
docs/system: ppc: Update ppce500 documentation with eTSEC support
This adds eTSEC support to the PowerPC `ppce500` machine documentation.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: fc8c745d50150a63f6c5ba2cd0b83b430963b7e8
https://github.com/qemu/qemu/commit/fc8c745d50150a63f6c5ba2cd0b83b430963b7e8
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M MAINTAINERS
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_vof.c
M hw/ppc/trace-events
A hw/ppc/vof.c
M include/hw/ppc/spapr.h
A include/hw/ppc/vof.h
M pc-bios/README
A pc-bios/vof-nvram.bin
A pc-bios/vof.bin
A pc-bios/vof/Makefile
A pc-bios/vof/bootmem.c
A pc-bios/vof/ci.c
A pc-bios/vof/entry.S
A pc-bios/vof/libc.c
A pc-bios/vof/main.c
A pc-bios/vof/vof.h
A pc-bios/vof/vof.lds
M tests/qtest/rtas-test.c
Log Message:
-----------
spapr: Implement Open Firmware client interface
The PAPR platform describes an OS environment that's presented by
a combination of a hypervisor and firmware. The features it specifies
require collaboration between the firmware and the hypervisor.
Since the beginning, the runtime component of the firmware (RTAS) has
been implemented as a 20 byte shim which simply forwards it to
a hypercall implemented in qemu. The boot time firmware component is
SLOF - but a build that's specific to qemu, and has always needed to be
updated in sync with it. Even though we've managed to limit the amount
of runtime communication we need between qemu and SLOF, there's some,
and it has become increasingly awkward to handle as we've implemented
new features.
This implements a boot time OF client interface (CI) which is
enabled by a new "x-vof" pseries machine option (stands for "Virtual Open
Firmware). When enabled, QEMU implements the custom H_OF_CLIENT hcall
which implements Open Firmware Client Interface (OF CI). This allows
using a smaller stateless firmware which does not have to manage
the device tree.
The new "vof.bin" firmware image is included with source code under
pc-bios/. It also includes RTAS blob.
This implements a handful of CI methods just to get -kernel/-initrd
working. In particular, this implements the device tree fetching and
simple memory allocator - "claim" (an OF CI memory allocator) and updates
"/memory@0/available" to report the client about available memory.
This implements changing some device tree properties which we know how
to deal with, the rest is ignored. To allow changes, this skips
fdt_pack() when x-vof=on as not packing the blob leaves some room for
appending.
In absence of SLOF, this assigns phandles to device tree nodes to make
device tree traversing work.
When x-vof=on, this adds "/chosen" every time QEMU (re)builds a tree.
This adds basic instances support which are managed by a hash map
ihandle -> [phandle].
Before the guest started, the used memory is:
0..e60 - the initial firmware
8000..10000 - stack
400000.. - kernel
3ea0000.. - initramdisk
This OF CI does not implement "interpret".
Unlike SLOF, this does not format uninitialized nvram. Instead, this
includes a disk image with pre-formatted nvram.
With this basic support, this can only boot into kernel directly.
However this is just enough for the petitboot kernel and initradmdisk to
boot from any possible source. Note this requires reasonably recent guest
kernel with:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=df5be5be8735
The immediate benefit is much faster booting time which especially
crucial with fully emulated early CPU bring up environments. Also this
may come handy when/if GRUB-in-the-userspace sees light of the day.
This separates VOF and sPAPR in a hope that VOF bits may be reused by
other POWERPC boards which do not support pSeries.
This assumes potential support for booting from QEMU backends
such as blockdev or netdev without devices/drivers used.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20210625055155.2252896-1-aik@ozlabs.ru>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
[dwg: Adjusted some includes which broke compile in some more obscure
compilation setups]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: caf590ddc9f514f88cc409319c06550f1f2b4014
https://github.com/qemu/qemu/commit/caf590ddc9f514f88cc409319c06550f1f2b4014
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: mtmsrd is an illegal instruction on BookE
MSR is a 32-bit register in BookE and there is no mtmsrd instruction.
Cc: Christian Zigotzky <chzigotzky@xenosoft.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210706051321.609046-1-npiggin@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: a8eda5ed3db61d7de6fda4a5216ae126a6bb5eb6
https://github.com/qemu/qemu/commit/a8eda5ed3db61d7de6fda4a5216ae126a6bb5eb6
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
ppc/pegasos2: Introduce Pegasos2MachineState structure
Add own machine state structure which will be used to store state
needed for firmware emulation.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<7f6d5fbf4f70c64dba001483174a2921dd616ecd.1624811233.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 5e994fc019862e77ee8fd2c8808c5fdcf2d249de
https://github.com/qemu/qemu/commit/5e994fc019862e77ee8fd2c8808c5fdcf2d249de
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/cpu.c
Log Message:
-----------
target/ppc: Allow virtual hypervisor on CPU without HV
Change the assert in ppc_store_sdr1() to allow vhyp to be set on CPUs
without HV bit. This allows using the vhyp interface for firmware
emulation on pegasos2.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<21c7745aabbb68fcc50bb2ffaf16b939ba21261c.1624811233.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 17fd09c0212b1595377fd62ade033dcd4147f8b6
https://github.com/qemu/qemu/commit/17fd09c0212b1595377fd62ade033dcd4147f8b6
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
target/ppc/spapr: Update H_GET_CPU_CHARACTERISTICS L1D cache flush bits
There are several new L1D cache flush bits added to the hcall which reflect
hardware security features for speculative cache access issues.
These behaviours are now being specified as negative in order to simplify
patched kernel compatibility with older firmware (a new problem found in
existing systems would automatically be vulnerable).
[dwg: Technically this changes behaviour for existing machine types.
After discussion with Nick, we've determined this is safe, because
the worst that will happen if a guest gets the wrong information due
to a migration is that it will perform some unnecessary workarounds,
but will remain correct and secure (well, as secure as it was going
to be anyway). In addition the change only affects cap-cfpc=safe
which is not enabled by default, and in fact is not possible to set
on any current hardware (though it's expected it will be possible on
POWER10)]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210615044107.1481608-1-npiggin@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: a6c9808a689764cba980280fc4581e2deb5023a4
https://github.com/qemu/qemu/commit/a6c9808a689764cba980280fc4581e2deb5023a4
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/Kconfig
M hw/ppc/pegasos2.c
Log Message:
-----------
ppc/pegasos2: Use Virtual Open Firmware as firmware replacement
The pegasos2 board comes with an Open Firmware compliant ROM based on
SmartFirmware but it has some changes that are not open source
therefore the ROM binary cannot be included in QEMU. Guests running on
the board however depend on services provided by the firmware. The
Virtual Open Firmware recently added to QEMU implements a minimal set
of these services to allow some guests to boot without the original
firmware. This patch adds VOF as the default firmware for pegasos2
which allows booting Linux and MorphOS via -kernel option while a ROM
image can still be used with -bios for guests that don't run with VOF.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<1d6ed6f290c5c1f0b5a1e1c51cf1151452d70d9a.1624811233.git.balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: e7dfb29e5a757de09b890df42fbeb5b70c6f2a9f
https://github.com/qemu/qemu/commit/e7dfb29e5a757de09b890df42fbeb5b70c6f2a9f
Author: David Gibson <david@gibson.dropbear.id.au>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/pegasos2.c
Log Message:
-----------
ppc/pegasos2: Fix use of && instead of &
This is obviously intended to be a mask, not a logical operation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 5f2eb04961011de0ed15160ee17c8f85c8c30b73
https://github.com/qemu/qemu/commit/5f2eb04961011de0ed15160ee17c8f85c8c30b73
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M default-configs/devices/ppc-softmmu.mak
M hw/ppc/pegasos2.c
Log Message:
-----------
ppc/pegasos2: Implement some RTAS functions with VOF
Linux uses RTAS functions to access PCI devices so we need to provide
these with VOF. Implement some of the most important functions to
allow booting Linux with VOF. With this the board is now usable
without a binary ROM image and we can enable it by default as other
boards.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210708215113.B3F747456E3@zero.eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 89bb5a4dfdef8316e840ab090ef04a5b7117731b
https://github.com/qemu/qemu/commit/89bb5a4dfdef8316e840ab090ef04a5b7117731b
Author: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/mmu_helper.c
Log Message:
-----------
target/ppc: Don't compile ppc_tlb_invalid_all without TCG
The function ppc_tlb_invalid_all is not compiled anymore in a TCG-less
environment, and the call to that function has been disabled in this
situation
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Message-Id: <20210708164957.28096-2-lucas.araujo@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 21bde1ecb6cecba1d2f0219a1b79c240bed78749
https://github.com/qemu/qemu/commit/21bde1ecb6cecba1d2f0219a1b79c240bed78749
Author: Alexey Kardashevskiy <aik@ozlabs.ru>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M MAINTAINERS
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_vof.c
M hw/ppc/vof.c
M include/hw/ppc/spapr.h
M pc-bios/vof.bin
M pc-bios/vof/ci.c
M pc-bios/vof/libc.c
M pc-bios/vof/main.c
M pc-bios/vof/vof.h
Log Message:
-----------
spapr: Fix implementation of Open Firmware client interface
This addresses the comments from v22.
The functional changes are (the VOF ones need retesting with Pegasos2):
(VOF) setprop will start failing if the machine class callback
did not handle it;
(VOF) unit addresses are lowered in path_offset();
(SPAPR) /chosen/bootargs is initialized from kernel_cmdline if
the client did not change it.
Fixes: 5c991e5d4378 ("spapr: Implement Open Firmware client interface")
Cc: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Message-Id: <20210708065625.548396-1-aik@ozlabs.ru>
Tested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 327d4b7f3f26eb19b8bc2b1b54afa6874612efdd
https://github.com/qemu/qemu/commit/327d4b7f3f26eb19b8bc2b1b54afa6874612efdd
Author: Bharata B Rao <bharata@linux.ibm.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M include/standard-headers/asm-x86/kvm_para.h
M include/standard-headers/drm/drm_fourcc.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/input-event-codes.h
M include/standard-headers/linux/virtio_ids.h
M include/standard-headers/linux/virtio_vsock.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-generic/mman-common.h
M linux-headers/asm-generic/unistd.h
M linux-headers/asm-mips/mman.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/unistd_32.h
M linux-headers/asm-powerpc/unistd_64.h
M linux-headers/asm-s390/unistd_32.h
M linux-headers/asm-s390/unistd_64.h
M linux-headers/asm-x86/kvm.h
M linux-headers/asm-x86/unistd_32.h
M linux-headers/asm-x86/unistd_64.h
M linux-headers/asm-x86/unistd_x32.h
M linux-headers/linux/kvm.h
M linux-headers/linux/userfaultfd.h
Log Message:
-----------
linux-headers: Update
Update to mainline commit: 79160a603bdb ("Merge tag 'usb-5.14-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb"
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20210706112440.1449562-2-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: 82123b756a1a2f1965350e5794aaa7b5c6a15282
https://github.com/qemu/qemu/commit/82123b756a1a2f1965350e5794aaa7b5c6a15282
Author: Bharata B Rao <bharata@linux.ibm.com>
Date: 2021-07-09 (Fri, 09 Jul 2021)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Support for H_RPT_INVALIDATE hcall
If KVM_CAP_RPT_INVALIDATE KVM capability is enabled, then
- indicate the availability of H_RPT_INVALIDATE hcall to the guest via
ibm,hypertas-functions property.
- Enable the hcall
Both the above are done only if the new sPAPR machine capability
cap-rpt-invalidate is set.
Signed-off-by: Bharata B Rao <bharata@linux.ibm.com>
Message-Id: <20210706112440.1449562-3-bharata@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Commit: fc32b91a88cc9cd560da5488bdca4d69f2bac620
https://github.com/qemu/qemu/commit/fc32b91a88cc9cd560da5488bdca4d69f2bac620
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-10 (Sat, 10 Jul 2021)
Changed paths:
M MAINTAINERS
M default-configs/devices/ppc-softmmu.mak
M docs/system/ppc/ppce500.rst
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/pegasos2.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_hcall.c
A hw/ppc/spapr_vof.c
M hw/ppc/trace-events
A hw/ppc/vof.c
M include/hw/ppc/spapr.h
A include/hw/ppc/vof.h
M include/standard-headers/asm-x86/kvm_para.h
M include/standard-headers/drm/drm_fourcc.h
M include/standard-headers/linux/ethtool.h
M include/standard-headers/linux/input-event-codes.h
M include/standard-headers/linux/virtio_ids.h
M include/standard-headers/linux/virtio_vsock.h
M linux-headers/asm-arm64/kvm.h
M linux-headers/asm-generic/mman-common.h
M linux-headers/asm-generic/unistd.h
M linux-headers/asm-mips/mman.h
M linux-headers/asm-mips/unistd_n32.h
M linux-headers/asm-mips/unistd_n64.h
M linux-headers/asm-mips/unistd_o32.h
M linux-headers/asm-powerpc/unistd_32.h
M linux-headers/asm-powerpc/unistd_64.h
M linux-headers/asm-s390/unistd_32.h
M linux-headers/asm-s390/unistd_64.h
M linux-headers/asm-x86/kvm.h
M linux-headers/asm-x86/unistd_32.h
M linux-headers/asm-x86/unistd_64.h
M linux-headers/asm-x86/unistd_x32.h
M linux-headers/linux/kvm.h
M linux-headers/linux/userfaultfd.h
M pc-bios/README
M pc-bios/u-boot.e500
A pc-bios/vof-nvram.bin
A pc-bios/vof.bin
A pc-bios/vof/Makefile
A pc-bios/vof/bootmem.c
A pc-bios/vof/ci.c
A pc-bios/vof/entry.S
A pc-bios/vof/libc.c
A pc-bios/vof/main.c
A pc-bios/vof/vof.h
A pc-bios/vof/vof.lds
M roms/u-boot
M target/ppc/arch_dump.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/mmu-book3s-v3.c
M target/ppc/mmu-book3s-v3.h
A target/ppc/mmu-books.h
M target/ppc/mmu-hash32.c
M target/ppc/mmu-hash32.h
M target/ppc/mmu-hash64.c
M target/ppc/mmu-hash64.h
M target/ppc/mmu-radix64.c
M target/ppc/mmu-radix64.h
M target/ppc/mmu_helper.c
M target/ppc/translate.c
M tests/qtest/rtas-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.1-20210709'
into staging
ppc patch queue 2021-07-09
Here's a (probably) final pull request before the qemu-6.1 soft
freeze. Includes:
* Implementation of the new H_RPT_INVALIDATE hypercall
* Virtual Open Firmware for pSeries and pegasos2 machine types.
This is an experimental minimal Open Firmware implementation which
works by delegating nearly everything to qemu itself via a special
hypercall.
* A number of cleanups to the ppc soft MMU code
* Fix to handling of two-level radix mode translations for the
powernv machine type
* Update the H_GET_CPU_CHARACTERISTICS call with newly defined bits.
This will allow more flexible handling of possible future CPU
Spectre-like flaws
* Correctly treat mtmsrd as an illegal instruction on BookE cpus
* Firmware update for the ppce500 machine type
# gpg: Signature made Fri 09 Jul 2021 06:16:42 BST
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
[full]
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dg-gitlab/tags/ppc-for-6.1-20210709: (33 commits)
target/ppc: Support for H_RPT_INVALIDATE hcall
linux-headers: Update
spapr: Fix implementation of Open Firmware client interface
target/ppc: Don't compile ppc_tlb_invalid_all without TCG
ppc/pegasos2: Implement some RTAS functions with VOF
ppc/pegasos2: Fix use of && instead of &
ppc/pegasos2: Use Virtual Open Firmware as firmware replacement
target/ppc/spapr: Update H_GET_CPU_CHARACTERISTICS L1D cache flush bits
target/ppc: Allow virtual hypervisor on CPU without HV
ppc/pegasos2: Introduce Pegasos2MachineState structure
target/ppc: mtmsrd is an illegal instruction on BookE
spapr: Implement Open Firmware client interface
docs/system: ppc: Update ppce500 documentation with eTSEC support
roms/u-boot: Bump ppce500 u-boot to v2021.07 to add eTSEC support
target/ppc: change ppc_hash32_xlate to use mmu_idx
target/ppc: introduce mmu-books.h
target/ppc: changed ppc_hash64_xlate to use mmu_idx
target/ppc: fix address translation bug for radix mmus
target/ppc: Fix compilation with DEBUG_BATS debug option
target/ppc: Fix compilation with FLUSH_ALL_TLBS debug option
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/ebd1f710029e...fc32b91a88cc
- [Qemu-commits] [qemu/qemu] c11dc1: target/ppc: Introduce ppc_interrupts_little_endian(),
Peter Maydell <=