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[Qemu-commits] [qemu/qemu] 71f502: docs/system/arm: Add quanta-q7l1-bmc
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 71f502: docs/system/arm: Add quanta-q7l1-bmc reference |
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Date: |
Sun, 04 Jul 2021 06:03:59 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 71f5027f34111da7bb769e8d5872294d728a7025
https://github.com/qemu/qemu/commit/71f5027f34111da7bb769e8d5872294d728a7025
Author: Patrick Venture <venture@google.com>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs/system/arm: Add quanta-q7l1-bmc reference
Adds a line-item reference to the supported quanta-q71l-bmc aspeed
entry.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-2-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fd17995c07ec1bc33f71b4ccb6c1b8721b6b368c
https://github.com/qemu/qemu/commit/fd17995c07ec1bc33f71b4ccb6c1b8721b6b368c
Author: Patrick Venture <venture@google.com>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M docs/system/arm/nuvoton.rst
Log Message:
-----------
docs/system/arm: Add quanta-gbs-bmc reference
Add line item reference to quanta-gbs-bmc machine.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210615192848.1065297-3-venture@google.com
[PMM: fixed underline Sphinx warning]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 38f2cfbbc3f2958cba542b1e264a8027eeca4835
https://github.com/qemu/qemu/commit/38f2cfbbc3f2958cba542b1e264a8027eeca4835
Author: Nolan Leake <nolan@sigbus.net>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M hw/arm/bcm2835_peripherals.c
A hw/misc/bcm2835_powermgt.c
M hw/misc/meson.build
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_powermgt.h
Log Message:
-----------
hw/arm: Add basic power management to raspi.
This is just enough to make reboot and poweroff work. Works for
linux, u-boot, and the arm trusted firmware. Not tested, but should
work for plan9, and bare-metal/hobby OSes, since they seem to generally
do what linux does for reset.
The watchdog timer functionality is not yet implemented.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/64
Signed-off-by: Nolan Leake <nolan@sigbus.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210625210209.1870217-1-nolan@sigbus.net
[PMM: tweaked commit title; fixed region size to 0x200;
moved header file to include/]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 95079d5c79a315426fef19b0245db06b71e6c863
https://github.com/qemu/qemu/commit/95079d5c79a315426fef19b0245db06b71e6c863
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
Add a test booting and quickly shutdown a raspi2 machine,
to test the power management model:
(1/1)
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:
console: [ 0.000000] Booting Linux on physical CPU 0xf00
console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc
version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb
12 20:27:48 GMT 2019
console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7),
cr=10c5387d
console: [ 0.000000] CPU: div instructions available: patching division
code
console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT
aliasing instruction cache
console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B
...
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
...
console: processor : 3
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4
idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
console: Hardware : BCM2835
console: Revision : 0000
console: Serial : 0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console: 00000000-3bffffff : System RAM
console: 00008000-00afffff : Kernel code
console: 00c00000-00d468ef : Kernel data
console: 3f006000-3f006fff : dwc_otg
console: 3f007000-3f007eff : /soc/dma@7e007000
console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880
console: 3f100000-3f100027 : /soc/watchdog@7e100000
console: 3f101000-3f102fff : /soc/cprman@7e101000
console: 3f200000-3f2000b3 : /soc/gpio@7e200000
PASS (24.59 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 |
CANCEL 0
JOB TIME : 25.02 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20210531113837.1689775-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 103e7579ddbd539fbe38e150da78264d0496023a
https://github.com/qemu/qemu/commit/103e7579ddbd539fbe38e150da78264d0496023a
Author: Joe Komlodi <joe.komlodi@xilinx.com>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-a64.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Check NaN mode before silencing NaN
If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute
FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will
assert due to fpst->default_nan_mode being set.
To avoid this, we check to see what NaN mode we're running in before we call
floatxx_silence_nan().
Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e3bcf57c1a3c498fe7bd1f18744614a802d8859a
https://github.com/qemu/qemu/commit/e3bcf57c1a3c498fe7bd1f18744614a802d8859a
Author: Maxim Uvarov <maxim.uvarov@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M hw/gpio/gpio_pwr.c
Log Message:
-----------
hw/gpio/gpio_pwr: use shutdown function for reboot
qemu has 2 type of functions: shutdown and reboot. Shutdown
function has to be used for machine shutdown. Otherwise we cause
a reset with a bogus "cause" value, when we intended a shutdown.
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d59ccc30f64249d5727bc084e0f3cf4b2483117b
https://github.com/qemu/qemu/commit/d59ccc30f64249d5727bc084e0f3cf4b2483117b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
In do_ldst(), the calculation of the offset needs to be based on the
size of the memory access, not the size of the elements in the
vector. This meant we were getting it wrong for the widening and
narrowing variants of the various VLDR and VSTR insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-2-peter.maydell@linaro.org
Commit: 303db86fc73c68d8774203d4796b9995cc122886
https://github.com/qemu/qemu/commit/303db86fc73c68d8774203d4796b9995cc122886
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/mve_helper.c
Log Message:
-----------
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
The initial implementation of the MVE VRMLALDAVH and VRMLSLDAVH
insns had some bugs:
* the 32x32 multiply of elements was being done as 32x32->32,
not 32x32->64
* we were incorrectly maintaining the accumulator in its full
72-bit form across all 4 beats of the insn; in the pseudocode
it is squashed back into the 64 bits of the RdaHi:RdaLo
registers after each beat
In particular, fixing the second of these allows us to recast
the implementation to avoid 128-bit arithmetic entirely.
Since the element size here is always 4, we can also drop the
parameterization of ESIZE to make the code a little more readable.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-3-peter.maydell@linaro.org
Commit: dfd66bc0f37dde37b8b2d7bad3a7075332e75fb4
https://github.com/qemu/qemu/commit/dfd66bc0f37dde37b8b2d7bad3a7075332e75fb4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/translate-neon.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Make asimd_imm_const() public
The function asimd_imm_const() in translate-neon.c is an
implementation of the pseudocode AdvSIMDExpandImm(), which we will
also want for MVE. Move the implementation to translate.c, with a
prototype in translate.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-4-peter.maydell@linaro.org
Commit: 2c0286dba46526ee6c23b1f28af62a857dace704
https://github.com/qemu/qemu/commit/2c0286dba46526ee6c23b1f28af62a857dace704
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Use asimd_imm_const for A64 decode
The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
Commit: e4667a5b5e71d83e3e2af70e7dba4bfab8892829
https://github.com/qemu/qemu/commit/e4667a5b5e71d83e3e2af70e7dba4bfab8892829
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use dup_const() instead of bitfield_replicate()
Use dup_const() instead of bitfield_replicate() in
disas_simd_mod_imm().
(We can't replace the other use of bitfield_replicate() in this file,
in logic_imm_decode_wmask(), because that location needs to handle 2
and 4 bit elements, which dup_const() cannot.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-6-peter.maydell@linaro.org
Commit: eab84139855dac258c8d89ad736f6649e3edc76a
https://github.com/qemu/qemu/commit/eab84139855dac258c8d89ad736f6649e3edc76a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE logical immediate insns
Implement the MVE logical-immediate insns (VMOV, VMVN,
VORR and VBIC). These have essentially the same encoding
as their Neon equivalents, and we implement the decode
in the same way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-7-peter.maydell@linaro.org
Commit: f9ed61741e5f26ee1bb933a87669697901d9327d
https://github.com/qemu/qemu/commit/f9ed61741e5f26ee1bb933a87669697901d9327d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE vector shift left by immediate insns
Implement the MVE shift-vector-left-by-immediate insns VSHL, VQSHL
and VQSHLU.
The size-and-immediate encoding here is the same as Neon, and we
handle it the same way neon-dp.decode does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-8-peter.maydell@linaro.org
Commit: 3394116f47d12bb577ee44493d3d61a30ec9dd68
https://github.com/qemu/qemu/commit/3394116f47d12bb577ee44493d3d61a30ec9dd68
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
M target/arm/translate-neon.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE vector shift right by immediate insns
Implement the MVE vector shift right by immediate insns VSHRI and
VRSHRI. As with Neon, we implement these by using helper functions
which perform left shifts but allow negative shift counts to indicate
right shifts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-9-peter.maydell@linaro.org
Commit: c2262707034c2b596db41fbc682150948e939772
https://github.com/qemu/qemu/commit/c2262707034c2b596db41fbc682150948e939772
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSHLL
Implement the MVE VHLL (vector shift left long) insn. This has two
encodings: the T1 encoding is the usual shift-by-immediate format,
and the T2 encoding is a special case where the shift count is always
equal to the element size.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-10-peter.maydell@linaro.org
Commit: a78b25fa71f1d2d9bcfdf2026743784e12efeeac
https://github.com/qemu/qemu/commit/a78b25fa71f1d2d9bcfdf2026743784e12efeeac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSRI, VSLI
Implement the MVE VSRI and VSLI insns, which perform a
shift-and-insert operation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-11-peter.maydell@linaro.org
Commit: 162e2655000689e44ac4c8e9e8dc413821e0adda
https://github.com/qemu/qemu/commit/162e2655000689e44ac4c8e9e8dc413821e0adda
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSHRN, VRSHRN
Implement the MVE shift-right-and-narrow insn VSHRN and VRSHRN.
do_urshr() is borrowed from sve_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-12-peter.maydell@linaro.org
Commit: d6f9e011e8643fb00303e3fec24dd1e424f3f5b3
https://github.com/qemu/qemu/commit/d6f9e011e8643fb00303e3fec24dd1e424f3f5b3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE saturating narrowing shifts
Implement the MVE saturating shift-right-and-narrow insns
VQSHRN, VQSHRUN, VQRSHRN and VQRSHRUN.
do_srshr() is borrowed from sve_helper.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-13-peter.maydell@linaro.org
Commit: 2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664
https://github.com/qemu/qemu/commit/2e6a4ce0f61d4be3d85a5a9e75d1fb39faa23664
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VSHLC
Implement the MVE VSHLC insn, which performs a shift left of the
entire vector with carry in bits provided from a general purpose
register and carry out bits written back to that register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-14-peter.maydell@linaro.org
Commit: d43ebd9dc8a268195dcc8219ced96f9e3bdc4050
https://github.com/qemu/qemu/commit/d43ebd9dc8a268195dcc8219ced96f9e3bdc4050
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/translate-mve.c
Log Message:
-----------
target/arm: Implement MVE VADDLV
Implement the MVE VADDLV insn; this is similar to VADDV, except
that it accumulates 32-bit elements into a 64-bit accumulator
stored in a pair of general-purpose registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-15-peter.maydell@linaro.org
Commit: f4ae6c8cbda8d9b21290e9b8ae21b785ca24aace
https://github.com/qemu/qemu/commit/f4ae6c8cbda8d9b21290e9b8ae21b785ca24aace
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve_helper.c
M target/arm/t32.decode
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE long shifts by immediate
The MVE extension to v8.1M includes some new shift instructions which
sit entirely within the non-coprocessor part of the encoding space
and which operate only on general-purpose registers. They take up
the space which was previously UNPREDICTABLE MOVS and ORRS encodings
with Rm == 13 or 15.
Implement the long shifts by immediate, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
an immediate shift count between 1 and 32.
Awkwardly, because the MOVS and ORRS trans functions do not UNDEF for
the Rm==13,15 case, we need to explicitly emit code to UNDEF for the
cases where v8.1M now requires that. (Trying to change MOVS and ORRS
is too difficult, because the functions that generate the code are
shared between a dozen different kinds of arithmetic or logical
instruction for all A32, T16 and T32 encodings, and for some insns
and some encodings Rm==13,15 are valid.)
We make the helper functions we need for UQSHLL and SQSHLL take
a 32-bit value which the helper casts to int8_t because we'll need
these helpers also for the shift-by-register insns, where the shift
count might be < 0 or > 32.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-16-peter.maydell@linaro.org
Commit: 0aa4b4c358bfced42306de697e6408cabf922cf5
https://github.com/qemu/qemu/commit/0aa4b4c358bfced42306de697e6408cabf922cf5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve_helper.c
M target/arm/t32.decode
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE long shifts by register
Implement the MVE long shifts by register, which perform shifts on a
pair of general-purpose registers treated as a 64-bit quantity, with
the shift count in another general-purpose register, which might be
either positive or negative.
Like the long-shifts-by-immediate, these encodings sit in the space
that was previously the UNPREDICTABLE MOVS/ORRS with Rm==13,15.
Because LSLL_rr and ASRL_rr overlap with both MOV_rxri/ORR_rrri and
also with CSEL (as one of the previously-UNPREDICTABLE Rm==13 cases),
we have to move the CSEL pattern into the same decodetree group.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-17-peter.maydell@linaro.org
Commit: 46321d47a91499897bd032361dc24013d70f21a5
https://github.com/qemu/qemu/commit/46321d47a91499897bd032361dc24013d70f21a5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve_helper.c
M target/arm/t32.decode
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE shifts by immediate
Implement the MVE shifts by immediate, which perform shifts
on a single general-purpose register.
These patterns overlap with the long-shift-by-immediates,
so we have to rearrange the grouping a little here.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-18-peter.maydell@linaro.org
Commit: 04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8
https://github.com/qemu/qemu/commit/04ea4d3cfd0a21b248ece8eb7a9436a3d9898dd8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-02 (Fri, 02 Jul 2021)
Changed paths:
M target/arm/helper-mve.h
M target/arm/mve_helper.c
M target/arm/t32.decode
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement MVE shifts by register
Implement the MVE shifts by register, which perform
shifts on a single general-purpose register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-19-peter.maydell@linaro.org
Commit: 73c8bf4ccff8951d228b8a0d49968c56e32da4de
https://github.com/qemu/qemu/commit/73c8bf4ccff8951d228b8a0d49968c56e32da4de
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-07-03 (Sat, 03 Jul 2021)
Changed paths:
M docs/system/arm/aspeed.rst
M docs/system/arm/nuvoton.rst
M hw/arm/bcm2835_peripherals.c
M hw/gpio/gpio_pwr.c
A hw/misc/bcm2835_powermgt.c
M hw/misc/meson.build
M include/hw/arm/bcm2835_peripherals.h
A include/hw/misc/bcm2835_powermgt.h
M target/arm/helper-a64.c
M target/arm/helper-mve.h
M target/arm/mve.decode
M target/arm/mve_helper.c
M target/arm/t32.decode
M target/arm/translate-a64.c
M target/arm/translate-mve.c
M target/arm/translate-neon.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vfp_helper.c
M tests/acceptance/boot_linux_console.py
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210702'
into staging
target-arm queue:
* more MVE instructions
* hw/gpio/gpio_pwr: use shutdown function for reboot
* target/arm: Check NaN mode before silencing NaN
* tests: Boot and halt a Linux guest on the Raspberry Pi 2 machine
* hw/arm: Add basic power management to raspi.
* docs/system/arm: Add quanta-gbs-bmc, quanta-q7l1-bmc
# gpg: Signature made Fri 02 Jul 2021 13:59:19 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210702: (24 commits)
target/arm: Implement MVE shifts by register
target/arm: Implement MVE shifts by immediate
target/arm: Implement MVE long shifts by register
target/arm: Implement MVE long shifts by immediate
target/arm: Implement MVE VADDLV
target/arm: Implement MVE VSHLC
target/arm: Implement MVE saturating narrowing shifts
target/arm: Implement MVE VSHRN, VRSHRN
target/arm: Implement MVE VSRI, VSLI
target/arm: Implement MVE VSHLL
target/arm: Implement MVE vector shift right by immediate insns
target/arm: Implement MVE vector shift left by immediate insns
target/arm: Implement MVE logical immediate insns
target/arm: Use dup_const() instead of bitfield_replicate()
target/arm: Use asimd_imm_const for A64 decode
target/arm: Make asimd_imm_const() public
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
hw/gpio/gpio_pwr: use shutdown function for reboot
target/arm: Check NaN mode before silencing NaN
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9c2647f75004...73c8bf4ccff8