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[Qemu-commits] [qemu/qemu] 65d1a2: target/riscv: Use target_ulong for th

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 65d1a2: target/riscv: Use target_ulong for the DisasContex...
Date: Fri, 25 Jun 2021 09:10:59 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 65d1a2bd3ec272bccdac29d4dc31c528a760cc3d
      
https://github.com/qemu/qemu/commit/65d1a2bd3ec272bccdac29d4dc31c528a760cc3d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use target_ulong for the DisasContext misa

The is_32bit() check in translate.c expects a 64-bit guest to have a
64-bit misa value otherwise the macro check won't work. This patches
fixes that and fixes a Coverity issue at the same time.

Fixes: CID 1453107
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
c00176c7518c2a7b4de3eec320b6a683ab56f705.1622435221.git.alistair.francis@wdc.com


  Commit: 79a412891f0cb6bbffd8fd9e13608066234e56c1
      
https://github.com/qemu/qemu/commit/79a412891f0cb6bbffd8fd9e13608066234e56c1
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: gdbstub: Fix dynamic CSR XML generation

Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR 
operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.

Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR 
operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 244a9fcb31c0f2b599caa7370c8e9d064497a920
      
https://github.com/qemu/qemu/commit/244a9fcb31c0f2b599caa7370c8e9d064497a920
  Author: Lukas Jünger <lukas.juenger@greensocs.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M hw/char/sifive_uart.c

  Log Message:
  -----------
  hw/char: Consistent function names for sifive_uart

This cleans up function names in the SiFive UART model.

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6ee7ba1b8a10bd8eb1d3b918eaaf9f832a51adb4
      
https://github.com/qemu/qemu/commit/6ee7ba1b8a10bd8eb1d3b918eaaf9f832a51adb4
  Author: Lukas Jünger <lukas.juenger@greensocs.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M hw/char/sifive_uart.c
    M include/hw/char/sifive_uart.h

  Log Message:
  -----------
  hw/char: QOMify sifive_uart

This QOMifies the SiFive UART model. Migration and reset have been
implemented.

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210616092326.59639-3-lukas.juenger@greensocs.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: bdc36ce649e2985225fcf9ab4958698fcafb04e9
      
https://github.com/qemu/qemu/commit/bdc36ce649e2985225fcf9ab4958698fcafb04e9
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M hw/char/ibex_uart.c
    M include/hw/char/ibex_uart.h

  Log Message:
  -----------
  hw/char/ibex_uart: Make the register layout private

We don't need to expose the register layout in the public header, so
don't.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
c437f570b2b30ab4170387a3ba2fad7d116a4986.1624001156.git.alistair.francis@wdc.com


  Commit: df41cbd6bfa55dc3e69834f4402dbf776062c26e
      
https://github.com/qemu/qemu/commit/df41cbd6bfa55dc3e69834f4402dbf776062c26e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M MAINTAINERS
    A hw/timer/ibex_timer.c
    M hw/timer/meson.build
    A include/hw/timer/ibex_timer.h

  Log Message:
  -----------
  hw/timer: Initial commit of Ibex Timer

Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.

We currently don't support changing the prescale or the timervalue.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com


  Commit: 3ef6434409c575e11faf537ce50ca05426c78940
      
https://github.com/qemu/qemu/commit/3ef6434409c575e11faf537ce50ca05426c78940
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-06-24 (Thu, 24 Jun 2021)

  Changed paths:
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer

Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com


  Commit: e3955ae93f5151ad2e982440b7c8d3776a9afee2
      
https://github.com/qemu/qemu/commit/e3955ae93f5151ad2e982440b7c8d3776a9afee2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-06-25 (Fri, 25 Jun 2021)

  Changed paths:
    M MAINTAINERS
    M hw/char/ibex_uart.c
    M hw/char/sifive_uart.c
    M hw/riscv/opentitan.c
    A hw/timer/ibex_timer.c
    M hw/timer/meson.build
    M include/hw/char/ibex_uart.h
    M include/hw/char/sifive_uart.h
    M include/hw/riscv/opentitan.h
    A include/hw/timer/ibex_timer.h
    M target/riscv/gdbstub.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging

Third RISC-V PR for 6.1 release

 - Fix MISA in the DisasContext
 - Fix GDB CSR XML generation
 - QOMify the SiFive UART
 - Add support for the OpenTitan timer

# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210624-2:
  hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
  hw/timer: Initial commit of Ibex Timer
  hw/char/ibex_uart: Make the register layout private
  hw/char: QOMify sifive_uart
  hw/char: Consistent function names for sifive_uart
  target/riscv: gdbstub: Fix dynamic CSR XML generation
  target/riscv: Use target_ulong for the DisasContext misa

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/3593b8e0a214...e3955ae93f51
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