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[Qemu-commits] [qemu/qemu] 3fb3b1: s390x/kvm: remove unused gs handling
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 3fb3b1: s390x/kvm: remove unused gs handling |
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Date: |
Tue, 22 Jun 2021 06:42:46 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 3fb3b122ac061859c20cdb14567313f137dbc152
https://github.com/qemu/qemu/commit/3fb3b122ac061859c20cdb14567313f137dbc152
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/kvm-stub.c
M target/s390x/kvm.c
M target/s390x/kvm_s390x.h
Log Message:
-----------
s390x/kvm: remove unused gs handling
With commit 0280b3eb7c05 ("s390x/kvm: use cpu model for gscb on
compat machines"), we removed any calls to kvm_s390_get_gs()
in favour of a different mechanism.
Let's remove the unused kvm_s390_get_gs(), and with it the now
unneeded cap_gs as well.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210602125050.492500-1-cohuck@redhat.com>
Commit: 0a3be7be73e594388ae2a91017b7ffafab15a7d9
https://github.com/qemu/qemu/commit/0a3be7be73e594388ae2a91017b7ffafab15a7d9
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/fpu_helper.c
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Fix FP CONVERT TO (LOGICAL) FIXED NaN handling
In case we encounter a NaN, we have to return the smallest possible
number, corresponding to either 0 or the maximum negative number. This
seems to differ from IEEE handling as implemented in softfloat, whereby
we return the biggest possible number.
While at it, use float32_to_uint64() in the CLGEB handler.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-2-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 0bd3c286562e363fd5725209c0b475af9b8465d1
https://github.com/qemu/qemu/commit/0bd3c286562e363fd5725209c0b475af9b8465d1
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/insn-data.def
Log Message:
-----------
s390x/tcg: Fix instruction name for VECTOR FP LOAD (LENGTHENED|ROUNDED)
Let's use the correct name.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-3-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 863b9507a61bb4f5707de0dadca829945c149e6e
https://github.com/qemu/qemu/commit/863b9507a61bb4f5707de0dadca829945c149e6e
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vop64_3() handling
Let's simplify, reworking our handler generation, passing the whole "m5"
register content and not providing specialized handlers for "se", and
reading/writing proper float64 values using new helpers.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-4-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 21bd6ea2b3b0f8c55eb31199bbb3de0eb8827b8e
https://github.com/qemu/qemu/commit/21bd6ea2b3b0f8c55eb31199bbb3de0eb8827b8e
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vop64_2() handling
Let's rework our macros and simplify. We still need helper functions in
most cases due to the different parameters types.
Next, we'll only have 32/128bit variants for vfi and vfsq, so special
case the others.
Note that for vfsq, the XxC and erm passed in the simd_data() will never be
set, resulting in the same behavior.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-5-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 64deb65afe028c85fb413285046c2e81a8d25b4f
https://github.com/qemu/qemu/commit/64deb65afe028c85fb413285046c2e81a8d25b4f
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vfc64() handling
Pass the m5 field via simd_data() and don't provide specialized handlers
for single-element variants.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-6-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 622ebe64ada4bf1bb3ce6bbfd7ea107ed166023c
https://github.com/qemu/qemu/commit/622ebe64ada4bf1bb3ce6bbfd7ea107ed166023c
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vftci64() handling
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-7-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 34142ffdee57f3fbd5eba1788ebc8e5d50a60022
https://github.com/qemu/qemu/commit/34142ffdee57f3fbd5eba1788ebc8e5d50a60022
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vfma64() handling
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-8-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 860b707bbb1957d710d3469dbdc3b9f72576a7ef
https://github.com/qemu/qemu/commit/860b707bbb1957d710d3469dbdc3b9f72576a7ef
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vfll32() handling
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-9-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 977e43d977c0b64a1b582cb4cc1c5711b5bc01a7
https://github.com/qemu/qemu/commit/977e43d977c0b64a1b582cb4cc1c5711b5bc01a7
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify vflr64() handling
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-10-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 4da79375c2a368bb548266e90e3d600afc05d165
https://github.com/qemu/qemu/commit/4da79375c2a368bb548266e90e3d600afc05d165
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Simplify wfc64() handling
... and prepare for 32/128 bit support.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-11-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 2a785dfb5071fdb269c77aeb7fa3930e93d413ef
https://github.com/qemu/qemu/commit/2a785dfb5071fdb269c77aeb7fa3930e93d413ef
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/translate_vx.c.inc
M target/s390x/vec_helper.c
Log Message:
-----------
s390x/tcg: Implement VECTOR BIT PERMUTE
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-12-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 8c18fa5b3eba2b5c4d1285714682db066ea711fa
https://github.com/qemu/qemu/commit/8c18fa5b3eba2b5c4d1285714682db066ea711fa
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/insn-data.def
M target/s390x/translate_vx.c.inc
Log Message:
-----------
s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL
Fortunately, we only need the Doubleword implementation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-13-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 0987961da96a5f62de5f0519ceaa022c394207c1
https://github.com/qemu/qemu/commit/0987961da96a5f62de5f0519ceaa022c394207c1
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT)
In case of 128bit, we always have a single element. Add new helpers for
reading/writing 32/128 bit floats.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-14-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: acb269a4cdeeafb027c350348f3137916e580746
https://github.com/qemu/qemu/commit/acb269a4cdeeafb027c350348f3137916e580746
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-15-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: e384332cb53bd5b4d813cc38b5d19b3648047e14
https://github.com/qemu/qemu/commit/e384332cb53bd5b4d813cc38b5d19b3648047e14
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *
In addition to 32/128bit variants, we also have to support the
"Signal-on-QNaN (SQ)" bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-16-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 1c6b5b47da8d9c8797cdf866fa180466b56a9204
https://github.com/qemu/qemu/commit/1c6b5b47da8d9c8797cdf866fa180466b56a9204
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-17-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 2e96005ed8509275f7396adacc3353e9189ce518
https://github.com/qemu/qemu/commit/2e96005ed8509275f7396adacc3353e9189ce518
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED
64 bit -> 128 bit, there is only a single final element.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-18-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 9cbc8be05aebc339546ed36334cb9e7b01e74b99
https://github.com/qemu/qemu/commit/9cbc8be05aebc339546ed36334cb9e7b01e74b99
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED
128 bit -> 64 bit, there is only a single element to process.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-19-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 390eeb35757ffeeed6811370625e11a1c6b1d565
https://github.com/qemu/qemu/commit/390eeb35757ffeeed6811370625e11a1c6b1d565
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/translate_vx.c.inc
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-20-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: a38b5a0eab9538543a241582d80cf0eb6ce97f1f
https://github.com/qemu/qemu/commit/a38b5a0eab9538543a241582d80cf0eb6ce97f1f
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-21-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: e257abc8de8011160fec3e85fcf54db9bc7ae2c6
https://github.com/qemu/qemu/commit/e257abc8de8011160fec3e85fcf54db9bc7ae2c6
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-22-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: f02497306ec2efb8315f604597ddf8142f00336d
https://github.com/qemu/qemu/commit/f02497306ec2efb8315f604597ddf8142f00336d
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-23-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: da4807527f3bda115606b4647fdc2f87928d0f15
https://github.com/qemu/qemu/commit/da4807527f3bda115606b4647fdc2f87928d0f15
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/internal.h
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
Log Message:
-----------
s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)
For IEEE functions, we can reuse the softfloat implementations. For the
other functions, implement it generically for 32bit/64bit/128bit -
carefully taking care of all weird special cases according to the tables
defined in the PoP.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-24-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: da215c239439539ffcbc0f79fba7b867eb3d8030
https://github.com/qemu/qemu/commit/da215c239439539ffcbc0f79fba7b867eb3d8030
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M include/elf.h
M linux-user/elfload.c
Log Message:
-----------
linux-user: elf: s390x: Prepare for Vector enhancements facility
Let's check for S390_FEAT_VECTOR_ENH and set HWCAP_S390_VXRS_EXT
accordingly. Add all missing HWCAP defined in upstream Linux.
Cc: Laurent Vivier <laurent@vivier.eu>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-25-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 8a9b7ed32d491693ed57d025d8a7d26f7a6a7d14
https://github.com/qemu/qemu/commit/8a9b7ed32d491693ed57d025d8a7d26f7a6a7d14
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/gen-features.c
Log Message:
-----------
s390x/tcg: We support Vector enhancements facility
Everything is wired up and all new instructions are implemented.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-26-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 463e50da8bf81bb3eff108e4bdd8fa7aadb12f4c
https://github.com/qemu/qemu/commit/463e50da8bf81bb3eff108e4bdd8fa7aadb12f4c
Author: David Hildenbrand <david@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/s390x/s390-virtio-ccw.c
M target/s390x/cpu_models.c
M target/s390x/gen-features.c
Log Message:
-----------
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2
TCG implements everything we need to run basic z14 OS+software.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-27-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 3af448b38677e7be5ccda6a65e06150abd1005b6
https://github.com/qemu/qemu/commit/3af448b38677e7be5ccda6a65e06150abd1005b6
Author: Thomas Huth <thuth@redhat.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M configure
Log Message:
-----------
configure: Check whether we can compile the s390-ccw bios with -msoft-float
The -msoft-float switch is not available in older versions of Clang.
Since we rely on the compiler to not generate floating point instructions
unexpectedly, we block those old compilers now via a test in the configure
script. Note that for some weird reasons, the Clang compiler only complains
about the missing soft-float support if no other flags are passed via
"-Wl,..." to the linker. So we have to use "compile_object" instead of
"compile_prog" for this check.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210525142032.156989-1-thuth@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: e2b2a8649bcd4769f453497b2abffbe44c7f86ad
https://github.com/qemu/qemu/commit/e2b2a8649bcd4769f453497b2abffbe44c7f86ad
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/cc_helper.c
M target/s390x/cpu.h
M target/s390x/excp_helper.c
M target/s390x/helper.c
M target/s390x/internal.h
M target/s390x/sigp.c
Log Message:
-----------
target/s390x: Expose load_psw and get_psw_mask to cpu.h
Rename to s390_cpu_set_psw and s390_cpu_get_psw_mask at the
same time. Adjust so that they compile for user-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com>
Tested-by: <ruixin.bao@ibm.com>
Message-Id: <20210615030744.1252385-2-richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 3c11c2ebb062ffb5d7dcad44ab0fb60505ad5cac
https://github.com/qemu/qemu/commit/3c11c2ebb062ffb5d7dcad44ab0fb60505ad5cac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
target/s390x: Do not modify cpu state in s390_cpu_get_psw_mask
We want to use this function for debugging, and debug should
not modify cpu state (even non-architectural cpu state) lest
we introduce heisenbugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com>
Tested-by: <ruixin.bao@ibm.com>
Message-Id: <20210615030744.1252385-3-richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: d09e6c921301d4377c73e0bc9010b52f201862dd
https://github.com/qemu/qemu/commit/d09e6c921301d4377c73e0bc9010b52f201862dd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
target/s390x: Improve s390_cpu_dump_state vs cc_op
Use s390_cpu_get_psw_mask so that we print the correct
architectural value of psw.mask. Do not print cc_op
unless tcg_enabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com>
Tested-by: <ruixin.bao@ibm.com>
Message-Id: <20210615030744.1252385-4-richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: deb60cc77b6743b65d1e830300b6d56ba538b103
https://github.com/qemu/qemu/commit/deb60cc77b6743b65d1e830300b6d56ba538b103
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M target/s390x/gdbstub.c
Log Message:
-----------
target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub
No change in behaviour, as gdbstub was correctly written to
install and extract the cc value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com>
Tested-by: <ruixin.bao@ibm.com>
Message-Id: <20210615030744.1252385-5-richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 10b81272b305da375c3c3e9ec86f2e35df702f2e
https://github.com/qemu/qemu/commit/10b81272b305da375c3c3e9ec86f2e35df702f2e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M linux-user/s390x/signal.c
Log Message:
-----------
linux-user/s390x: Save and restore psw.mask properly
At present, we're referencing env->psw.mask directly, which
fails to ensure that env->cc_op is incorporated or updated.
Use s390_cpu_{set_psw,get_psw_mask} to fix this.
Mirror the kernel's cleaning of the psw.mask in save_sigregs
and restore_sigregs. Ignore PSW_MASK_RI for now, as qemu does
not support that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Tested-by: jonathan.albrecht <jonathan.albrecht@linux.vnet.ibm.com>
Tested-by: <ruixin.bao@ibm.com>
Message-Id: <20210615030744.1252385-6-richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 3fdc622ad79636f3d7f8bed50a53bc28af1850e1
https://github.com/qemu/qemu/commit/3fdc622ad79636f3d7f8bed50a53bc28af1850e1
Author: Eric Farman <farman@linux.ibm.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/s390x/css.c
M include/hw/s390x/ioinst.h
Log Message:
-----------
s390x/css: Introduce an ESW struct
The Interrupt Response Block is comprised of several other
structures concatenated together, but only the 12-byte
Subchannel-Status Word (SCSW) is defined as a proper struct.
Everything else is a simple array of 32-bit words.
Let's define a proper struct for the 20-byte Extended-Status
Word (ESW) so that we can make good decisions about the sense
data that would go into the ECW area for virtual vs
passthrough devices.
[CH: adapted ESW definition to build with mingw, as discussed]
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Message-Id: <20210617232537.1337506-2-farman@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 1b01dedaed41c2ca6129475c22b7b778b109fae8
https://github.com/qemu/qemu/commit/1b01dedaed41c2ca6129475c22b7b778b109fae8
Author: Eric Farman <farman@linux.ibm.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/s390x/css.c
Log Message:
-----------
s390x/css: Split out the IRB sense data
Let's move this logic into its own routine,
so it can be reused later.
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20210617232537.1337506-3-farman@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: 0599a046acf1b625e97cef0aa702b5d86528c642
https://github.com/qemu/qemu/commit/0599a046acf1b625e97cef0aa702b5d86528c642
Author: Eric Farman <farman@linux.ibm.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/s390x/3270-ccw.c
M hw/s390x/css.c
M hw/s390x/virtio-ccw.c
M include/hw/s390x/css.h
Log Message:
-----------
s390x/css: Refactor IRB construction
Currently, all subchannel types have "sense data" copied into
the IRB.ECW space, and a couple flags enabled in the IRB.SCSW
and IRB.ESW. But for passthrough (vfio-ccw) subchannels,
this data isn't populated in the first place, so enabling
those flags leads to unexpected behavior if the guest tries to
process the sense data (zeros) in the IRB.ECW.
Let's add a subchannel callback that builds these portions of
the IRB, and move the existing code into a routine for those
virtual subchannels. The passthrough subchannels will be able
to piggy-back onto this later.
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Message-Id: <20210617232537.1337506-4-farman@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: c626710fc755628d0d6b88aab0514c9238a84522
https://github.com/qemu/qemu/commit/c626710fc755628d0d6b88aab0514c9238a84522
Author: Eric Farman <farman@linux.ibm.com>
Date: 2021-06-21 (Mon, 21 Jun 2021)
Changed paths:
M hw/s390x/css.c
M hw/s390x/s390-ccw.c
M hw/vfio/ccw.c
M include/hw/s390x/css.h
Log Message:
-----------
s390x/css: Add passthrough IRB
Wire in the subchannel callback for building the IRB
ESW and ECW space for passthrough devices, and copy
the hardware's ESW into the IRB we are building.
If the hardware presented concurrent sense, then copy
that sense data into the IRB's ECW space.
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Message-Id: <20210617232537.1337506-5-farman@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Commit: bf7942e406cb5e96d2490909d2cb31c7625b087b
https://github.com/qemu/qemu/commit/bf7942e406cb5e96d2490909d2cb31c7625b087b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-22 (Tue, 22 Jun 2021)
Changed paths:
M configure
M hw/s390x/3270-ccw.c
M hw/s390x/css.c
M hw/s390x/s390-ccw.c
M hw/s390x/s390-virtio-ccw.c
M hw/s390x/virtio-ccw.c
M hw/vfio/ccw.c
M include/elf.h
M include/hw/s390x/css.h
M include/hw/s390x/ioinst.h
M linux-user/elfload.c
M linux-user/s390x/signal.c
M target/s390x/cc_helper.c
M target/s390x/cpu.h
M target/s390x/cpu_models.c
M target/s390x/excp_helper.c
M target/s390x/fpu_helper.c
M target/s390x/gdbstub.c
M target/s390x/gen-features.c
M target/s390x/helper.c
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/internal.h
M target/s390x/kvm-stub.c
M target/s390x/kvm.c
M target/s390x/kvm_s390x.h
M target/s390x/sigp.c
M target/s390x/translate_vx.c.inc
M target/s390x/vec_fpu_helper.c
M target/s390x/vec_helper.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210621' into
staging
s390x update:
- tcg: implement the vector enhancements facility and bump the
'qemu' cpu model to a stripped-down z14 GA2
- fix psw.mask handling in signals
- fix vfio-ccw sense data handling
# gpg: Signature made Mon 21 Jun 2021 10:53:00 BST
# gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg: issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF
* remotes/cohuck-gitlab/tags/s390x-20210621: (37 commits)
s390x/css: Add passthrough IRB
s390x/css: Refactor IRB construction
s390x/css: Split out the IRB sense data
s390x/css: Introduce an ESW struct
linux-user/s390x: Save and restore psw.mask properly
target/s390x: Use s390_cpu_{set_psw, get_psw_mask} in gdbstub
target/s390x: Improve s390_cpu_dump_state vs cc_op
target/s390x: Do not modify cpu state in s390_cpu_get_psw_mask
target/s390x: Expose load_psw and get_psw_mask to cpu.h
configure: Check whether we can compile the s390-ccw bios with -msoft-float
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2
s390x/tcg: We support Vector enhancements facility
linux-user: elf: s390x: Prepare for Vector enhancements facility
s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM)
s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT)
s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE
s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION
s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED
s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/b733163e057a...bf7942e406cb
- [Qemu-commits] [qemu/qemu] 3fb3b1: s390x/kvm: remove unused gs handling,
Peter Maydell <=