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[Qemu-commits] [qemu/qemu] 96a664: hw/intc/arm_gicv3_cpuif: Tolerate spu
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 96a664: hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR wr... |
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Date: |
Wed, 16 Jun 2021 09:08:19 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 96a664d05c238ea1b64af2394b58e956fe0afe26
https://github.com/qemu/qemu/commit/96a664d05c238ea1b64af2394b58e956fe0afe26
Author: Jean-Philippe Brucker <jean-philippe@linaro.org>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
Commit 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access
check logic") added an assert_not_reached() if the guest writes the EOIR
register while no interrupt is active.
It turns out some software does this: EDK2, in
GicV3ExitBootServicesEvent(), unconditionally write EOIR for all
interrupts that it manages. This now causes QEMU to abort when running
UEFI on a VM with GICv3. Although it is UNPREDICTABLE behavior and EDK2
does need fixing, the punishment seems a little harsh, especially since
icc_eoir_write() already tolerates writes of nonexistent interrupt
numbers. Display a guest error and tolerate spurious EOIR writes.
Fixes: 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check
logic")
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210604130352.1887560-1-jean-philippe@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: cd39e773e00bf98ab41e2ffaaeab7a00a3f68bd1
https://github.com/qemu/qemu/commit/cd39e773e00bf98ab41e2ffaaeab7a00a3f68bd1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16
This fprintf+assert has been in place since the beginning.
It is prior to the fp_access_check, so we're still good to
raise sigill here.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210604183506.916654-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0af4d13b3114a87e53cb9e2ee0c5588c513f4b1a
https://github.com/qemu/qemu/commit/0af4d13b3114a87e53cb9e2ee0c5588c513f4b1a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Remove fprintf from disas_simd_mod_imm
The default of this switch is truly unreachable.
The switch selector is 3 bits, and all 8 cases are present.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210604183506.916654-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 475d696af7edd74779a2ac2245496b20d4625fdf
https://github.com/qemu/qemu/commit/475d696af7edd74779a2ac2245496b20d4625fdf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16
This fprintf+assert has been in place since the beginning.
It is after to the fp_access_check, so we need to move the
check up. Fold that in to the pairwise filter.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210604183506.916654-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 75228f0522be9708c227c4572b8a1851c39300a7
https://github.com/qemu/qemu/commit/75228f0522be9708c227c4572b8a1851c39300a7
Author: Heinrich Schuchardt <xypron.glpk@gmx.de>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw: virt: consider hw_compat_6_0
virt-6.0 must consider hw_compat_6_0.
Fixes: da7e13c00b59 ("hw: add compat machines for 6.1")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-id: 20210610183500.54207-1-xypron.glpk@gmx.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a8b3ddde6c756059c00663224c1ad9835d30eae5
https://github.com/qemu/qemu/commit/a8b3ddde6c756059c00663224c1ad9835d30eae5
Author: Patrick Venture <venture@google.com>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: add quanta-gbs-bmc machine
Adds initial quanta-gbs-bmc machine support.
Tested: Boots to userspace.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Brandon Kim <brandonkim@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210608193605.2611114-2-venture@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 1c7f3e248e0ac8fc53d1d40d7ef8c9852fefed8c
https://github.com/qemu/qemu/commit/1c7f3e248e0ac8fc53d1d40d7ef8c9852fefed8c
Author: Patrick Venture <venture@google.com>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: quanta-gbs-bmc add i2c comments
Add a comment and i2c method that describes the board layout.
Tested: firmware booted to userspace.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Brandon Kim <brandonkim@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210608193605.2611114-3-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a25c84c7e0ac00c026afa28fbbfa044e12fe0b1a
https://github.com/qemu/qemu/commit/a25c84c7e0ac00c026afa28fbbfa044e12fe0b1a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-15 (Tue, 15 Jun 2021)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Remove stale comment
In commit da6d674e509f0939b we split the NVIC code out from the GIC.
This allowed us to specify the NVIC's default value for the num-irq
property (64) in the usual way in its property list, and we deleted
the previous hack where we updated the value in the state struct in
the instance init function. Remove a stale comment about that hack
which we forgot to delete at that time.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614161243.14211-1-peter.maydell@linaro.org
Commit: d3327a38cda104dd292105b6b9d140f2158209f9
https://github.com/qemu/qemu/commit/d3327a38cda104dd292105b6b9d140f2158209f9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/mte_helper.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-7.c
Log Message:
-----------
target/arm: Fix mte page crossing test
The test was off-by-one, because tag_last points to the
last byte of the tag to check, thus tag_last - prev_page
will equal TARGET_PAGE_SIZE when we use the first byte
of the next page.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403
Reported-by: Peter Collingbourne <pcc@google.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210612195707.840217-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 319466876b33dc98aa2b9e59deab126c2236bd3e
https://github.com/qemu/qemu/commit/319466876b33dc98aa2b9e59deab126c2236bd3e
Author: Patrick Venture <venture@google.com>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: gsj add i2c comments
Adds comments to the board init to identify missing i2c devices.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20210608202522.2677850-2-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6229659ec83e979545194c296dd1afc5cd7b7310
https://github.com/qemu/qemu/commit/6229659ec83e979545194c296dd1afc5cd7b7310
Author: Patrick Venture <venture@google.com>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/npcm7xx_boards.c
Log Message:
-----------
hw/arm: gsj add pca9548
Tested: Quanta-gsj firmware booted.
i2c /dev entries driver
I2C init bus 1 freq 100000
I2C init bus 2 freq 100000
I2C init bus 3 freq 100000
I2C init bus 4 freq 100000
I2C init bus 8 freq 100000
I2C init bus 9 freq 100000
at24 9-0055: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
I2C init bus 10 freq 100000
at24 10-0055: 8192 byte 24c64 EEPROM, writable, 1 bytes/write
I2C init bus 12 freq 100000
I2C init bus 15 freq 100000
i2c i2c-15: Added multiplexed i2c bus 16
i2c i2c-15: Added multiplexed i2c bus 17
i2c i2c-15: Added multiplexed i2c bus 18
i2c i2c-15: Added multiplexed i2c bus 19
i2c i2c-15: Added multiplexed i2c bus 20
i2c i2c-15: Added multiplexed i2c bus 21
i2c i2c-15: Added multiplexed i2c bus 22
i2c i2c-15: Added multiplexed i2c bus 23
pca954x 15-0075: registered 8 multiplexed busses for I2C switch pca9548
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20210608202522.2677850-3-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3ec75e39e67d69fe56731606c0c03921889a3019
https://github.com/qemu/qemu/commit/3ec75e39e67d69fe56731606c0c03921889a3019
Author: Patrick Venture <venture@google.com>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm: quanta-q71l add pca954x muxes
Adds the pca954x muxes expected.
Tested: Booted quanta-q71l image to userspace.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20210608202522.2677850-4-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6e802db3c418e522b25a16fd74ea6d98fc2a1480
https://github.com/qemu/qemu/commit/6e802db3c418e522b25a16fd74ea6d98fc2a1480
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/sve_helper.c
M target/arm/vec_helper.c
M target/arm/vec_internal.h
Log Message:
-----------
target/arm: Provide and use H8 and H1_8 macros
Currently we provide Hn and H1_n macros for accessing the correct
data within arrays of vector elements of size 1, 2 and 4, accounting
for host endianness. We don't provide any macros for elements of
size 8 because there the host endianness doesn't matter. However,
this does result in awkwardness where we need to pass empty arguments
to macros, because checkpatch complains about them. The empty
argument is a little confusing for humans to read as well.
Add H8() and H1_8() macros and use them where we were previously
passing empty arguments to macros.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-2-peter.maydell@linaro.org
Message-id: 20210610132505.5827-1-peter.maydell@linaro.org
Commit: c485ce2c491a6e5d66da1d1555ecd474b450db98
https://github.com/qemu/qemu/commit/c485ce2c491a6e5d66da1d1555ecd474b450db98
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Enable FPSCR.QC bit for MVE
MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE
is implemented make the bit writeable, both in the generic "load and
store FPSCR" helper functions and in the code for handling the NZCVQC
sysreg which we had previously left as "TODO when we implement MVE".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-3-peter.maydell@linaro.org
Commit: 375256a8460ae7310b053b52fe579c8832e73d10
https://github.com/qemu/qemu/commit/375256a8460ae7310b053b52fe579c8832e73d10
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/m_helper.c
M target/arm/translate-m-nocp.c
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Handle VPR semantics in existing code
When MVE is supported, the VPR register has a place on the exception
stack frame in a previously reserved slot just above the FPSCR.
It must also be zeroed in various situations when we invalidate
FPU context.
Update the code which handles the stack frames (exception entry and
exit code, VLLDM, and VLSTM) to save/restore VPR.
Update code which invalidates FP registers (mostly also exception
entry and exit code, but also VSCCLRM and the code in
full_vfp_access_check() that corresponds to the ExecuteFPCheck()
pseudocode) to zero VPR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-4-peter.maydell@linaro.org
Commit: 5138bd0143cc87c91e41f26fab2a5ba96e62ce49
https://github.com/qemu/qemu/commit/5138bd0143cc87c91e41f26fab2a5ba96e62ce49
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/translate-a32.h
M target/arm/translate-m-nocp.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Add handling for PSR.ECI/ICI
On A-profile, PSR bits [15:10][26:25] are always the IT state bits.
On M-profile, some of the reserved encodings of the IT state are used
to instead indicate partial progress through instructions that were
interrupted partway through by an exception and can be resumed.
These resumable instructions fall into two categories:
(1) load/store multiple instructions, where these bits are called
"ICI" and specify the register in the ldm/stm list where execution
should resume. (Specifically: LDM, STM, VLDM, VSTM, VLLDM, VLSTM,
CLRM, VSCCLRM.)
(2) MVE instructions subject to beatwise execution, where these bits
are called "ECI" and specify which beats in this and possibly also
the following MVE insn have been executed.
There are also a few insns (LE, LETP, and BKPT) which do not use the
ICI/ECI bits but must leave them alone.
Otherwise, we should raise an INVSTATE UsageFault for any attempt to
execute an insn with non-zero ICI/ECI bits.
So far we have been able to ignore ECI/ICI, because the architecture
allows the IMPDEF choice of "always restart load/store multiple from
the beginning regardless of ICI state", so the only thing we have
been missing is that we don't raise the INVSTATE fault for bad guest
code. However, MVE requires that we honour ECI bits and do not
rexecute beats of an insn that have already been executed.
Add the support in the decoder for handling ECI/ICI:
* identify the ECI/ICI case in the CONDEXEC TB flags
* when a load/store multiple insn succeeds, it updates the ECI/ICI
state (both in DisasContext and in the CPU state), and sets a flag
to say that the ECI/ICI state was handled
* if we find that the insn we just decoded did not handle the
ECI/ICI state, we delete all the code that we just generated for
it and instead emit the code to raise the INVFAULT. This allows
us to avoid having to update every non-MVE non-LDM/STM insn to
make it check for "is ECI/ICI set?".
We continue with our existing IMPDEF choice of not caring about the
ICI state for the load/store multiples and simply restarting them
from the beginning. Because we don't allow interrupts in the middle
of an insn, the only way we would see this state is if the guest set
ICI manually on return from an exception handler, so it's a corner
case which doesn't merit optimisation.
ICI update for LDM/STM is simple -- it always zeroes the state. ECI
update for MVE beatwise insns will be a little more complex, since
the ECI state may include information for the following insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-5-peter.maydell@linaro.org
Commit: 9a486856e9173af190eaefdf1080db82bd04b536
https://github.com/qemu/qemu/commit/9a486856e9173af190eaefdf1080db82bd04b536
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/translate-vfp.c
Log Message:
-----------
target/arm: Let vfp_access_check() handle late NOCP checks
In commit a3494d4671797c we reworked the M-profile handling of its
checks for when the NOCP exception should be raised because the FPU
is disabled, so that (in line with the architecture) the NOCP check
is done early over a large range of the encoding space, and takes
precedence over UNDEF exceptions. As part of this, we removed the
code from full_vfp_access_check() which raised an exception there for
M-profile with the FPU disabled, because it was no longer reachable.
For MVE, some instructions which are outside the "coprocessor space"
region of the encoding space must nonetheless do "is the FPU enabled"
checks and possibly raise a NOCP exception. (In particular this
covers the MVE-specific low-overhead branch insns LCTP, DLSTP and
WLSTP.) To support these insns, reinstate the code in
full_vfp_access_check(), so that their trans functions can call
vfp_access_check() and get the correct behaviour.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-6-peter.maydell@linaro.org
Commit: 76c32d721da1a69999eb2d3cd5f1d272ca26f98e
https://github.com/qemu/qemu/commit/76c32d721da1a69999eb2d3cd5f1d272ca26f98e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement MVE LCTP
Implement the MVE LCTP instruction.
We put its decode and implementation with the other
low-overhead-branch insns because although it is only present if MVE
is implemented it is logically in the same group as the other LOB
insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-7-peter.maydell@linaro.org
Commit: 6822abfdf8b382be4fc84066fa1087e5fef81360
https://github.com/qemu/qemu/commit/6822abfdf8b382be4fc84066fa1087e5fef81360
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement MVE WLSTP insn
Implement the MVE WLSTP insn; this is like the existing WLS insn,
except that it specifies a size value which is used to set
FPSCR.LTPSIZE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-8-peter.maydell@linaro.org
Commit: 40a36f003c0375bb9d347eeb3f60bac7bbeb82c3
https://github.com/qemu/qemu/commit/40a36f003c0375bb9d347eeb3f60bac7bbeb82c3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement MVE DLSTP
Implement the MVE DLSTP insn; this is like the existing DLS
insn, except that it must do an FPU access check and it
sets LTPSIZE to the value specified in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-9-peter.maydell@linaro.org
Commit: a454ea1e6d40bbd4632e4e66de90e802ae47a68e
https://github.com/qemu/qemu/commit/a454ea1e6d40bbd4632e4e66de90e802ae47a68e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/t32.decode
M target/arm/translate.c
Log Message:
-----------
target/arm: Implement MVE LETP insn
Implement the MVE LETP insn. This is like the existing LE loop-end
insn, but it must perform an FPU-enabled check, and on loop-exit it
resets LTPSIZE to 4.
To accommodate the requirement to do something on loop-exit, we drop
the use of condlabel and instead manage both the TB exits manually,
in the same way we already do in trans_WLS().
The other MVE-specific change to the LE insn is that we must raise an
INVSTATE UsageFault insn if LTPSIZE is not 4.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-10-peter.maydell@linaro.org
Commit: 6390eed45cab462320ceb4cbfc2cbd1c1552ed00
https://github.com/qemu/qemu/commit/6390eed45cab462320ceb4cbfc2cbd1c1552ed00
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/meson.build
A target/arm/mve.decode
M target/arm/translate-a32.h
A target/arm/translate-mve.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Add framework for MVE decode
Add the framework for decoding MVE insns, with the necessary new
files and the meson.build rules, but no actual content yet.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-11-peter.maydell@linaro.org
Commit: 77f96148f3f6c4106a2a3cee8146690f954fd6cd
https://github.com/qemu/qemu/commit/77f96148f3f6c4106a2a3cee8146690f954fd6cd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M target/arm/sve_helper.c
M target/arm/vec_helper.c
M target/arm/vec_internal.h
Log Message:
-----------
target/arm: Move expand_pred_b() data to vec_helper.c
For MVE, we want to re-use the large data table from expand_pred_b().
Move the data table to vec_helper.c so it is no longer in an SVE
specific source file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-14-peter.maydell@linaro.org
Commit: dbcf6f9367a6a4af05b18cf0d7badf7677f403c4
https://github.com/qemu/qemu/commit/dbcf6f9367a6a4af05b18cf0d7badf7677f403c4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M include/qemu/bitops.h
M target/arm/sve_helper.c
Log Message:
-----------
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
Currently the ARM SVE helper code defines locally some utility
functions for swapping 16-bit halfwords within 32-bit or 64-bit
values and for swapping 32-bit words within 64-bit values,
parallel to the byte-swapping bswap16/32/64 functions.
We want these also for the ARM MVE code, and they're potentially
generally useful for other targets, so move them to bitops.h.
(We don't put them in bswap.h with the bswap* functions because
they are implemented in terms of the rotate operations also
defined in bitops.h, and including bitops.h from bswap.h seems
better avoided.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210614151007.4545-17-peter.maydell@linaro.org
Commit: 703235a303d6862a7e3f5c6aa9eff7471cb138b2
https://github.com/qemu/qemu/commit/703235a303d6862a7e3f5c6aa9eff7471cb138b2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M include/qemu/int128.h
Log Message:
-----------
include/qemu/int128.h: Add function to create Int128 from int64_t
int128_make64() creates an Int128 from an unsigned 64 bit value; add
a function int128_makes64() creating an Int128 from a signed 64 bit
value.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210614151007.4545-34-peter.maydell@linaro.org
Commit: 38848ce565849e5b867a5e08022b3c755039c11a
https://github.com/qemu/qemu/commit/38848ce565849e5b867a5e08022b3c755039c11a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-06-16 (Wed, 16 Jun 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/npcm7xx_boards.c
M hw/arm/virt.c
M hw/intc/arm_gicv3_cpuif.c
M hw/intc/armv7m_nvic.c
M include/qemu/bitops.h
M include/qemu/int128.h
M target/arm/m_helper.c
M target/arm/meson.build
M target/arm/mte_helper.c
A target/arm/mve.decode
M target/arm/sve_helper.c
M target/arm/t32.decode
M target/arm/translate-a32.h
M target/arm/translate-a64.c
M target/arm/translate-m-nocp.c
A target/arm/translate-mve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
M target/arm/vec_internal.h
M target/arm/vfp_helper.c
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-7.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616'
into staging
target-arm queue:
* hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes
* handle some UNALLOCATED decode cases correctly rather
than asserting
* hw: virt: consider hw_compat_6_0
* hw/arm: add quanta-gbs-bmc machine
* hw/intc/armv7m_nvic: Remove stale comment
* target/arm: Fix mte page crossing test
* hw/arm: quanta-q71l add pca954x muxes
* target/arm: First few parts of MVE support
# gpg: Signature made Wed 16 Jun 2021 14:34:49 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits)
include/qemu/int128.h: Add function to create Int128 from int64_t
bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations
target/arm: Move expand_pred_b() data to vec_helper.c
target/arm: Add framework for MVE decode
target/arm: Implement MVE LETP insn
target/arm: Implement MVE DLSTP
target/arm: Implement MVE WLSTP insn
target/arm: Implement MVE LCTP
target/arm: Let vfp_access_check() handle late NOCP checks
target/arm: Add handling for PSR.ECI/ICI
target/arm: Handle VPR semantics in existing code
target/arm: Enable FPSCR.QC bit for MVE
target/arm: Provide and use H8 and H1_8 macros
hw/arm: quanta-q71l add pca954x muxes
hw/arm: gsj add pca9548
hw/arm: gsj add i2c comments
target/arm: Fix mte page crossing test
hw/intc/armv7m_nvic: Remove stale comment
hw/arm: quanta-gbs-bmc add i2c comments
hw/arm: add quanta-gbs-bmc machine
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/e3897b75fd2a...38848ce56584