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[Qemu-commits] [qemu/qemu] 0a73d7: exec/memory_ldst_cached: Sort declara


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 0a73d7: exec/memory_ldst_cached: Sort declarations
Date: Fri, 28 May 2021 14:56:27 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0a73d7ac9a200cdf17562d0a893c1578f3ffa4a4
      
https://github.com/qemu/qemu/commit/0a73d7ac9a200cdf17562d0a893c1578f3ffa4a4
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory_ldst_cached.h.inc

  Log Message:
  -----------
  exec/memory_ldst_cached: Sort declarations

To ease the file review, sort the declarations by the size of
the access (8, 16, 32). Simple code movement, no logical change.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-2-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e1d2dbee5704e4db5dda6cda3da1bbbb4f950f90
      
https://github.com/qemu/qemu/commit/e1d2dbee5704e4db5dda6cda3da1bbbb4f950f90
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory_ldst_phys.h.inc

  Log Message:
  -----------
  exec/memory_ldst_phys: Sort declarations

To ease the file review, sort the declarations by the size of
the access (8, 16, 32). Simple code movement, no logical change.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-3-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f933b02b59f07c17c312185a9ceaefbf9dfbb36e
      
https://github.com/qemu/qemu/commit/f933b02b59f07c17c312185a9ceaefbf9dfbb36e
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory_ldst.h.inc
    M memory_ldst.c.inc

  Log Message:
  -----------
  exec/memory_ldst: Use correct type sizes

Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
16-bit word.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-4-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c6fe45b3a66d05d74f919da4226d4737fc3f75c9
      
https://github.com/qemu/qemu/commit/c6fe45b3a66d05d74f919da4226d4737fc3f75c9
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory_ldst_phys.h.inc

  Log Message:
  -----------
  exec/memory_ldst_phys: Use correct type sizes

Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
16-bit word.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-5-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4045f49cd4bba9c7e1d531cb805177deb5079147
      
https://github.com/qemu/qemu/commit/4045f49cd4bba9c7e1d531cb805177deb5079147
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory_ldst_cached.h.inc

  Log Message:
  -----------
  exec/memory_ldst_cached: Use correct type size

Use uint16_t for (unsigned) 16-bit word.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-6-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4121f4b38e976641ee66ad52567f6f178a8f2048
      
https://github.com/qemu/qemu/commit/4121f4b38e976641ee66ad52567f6f178a8f2048
  Author: Philippe Mathieu-Daudé <philmd@redhat.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/exec/memory.h

  Log Message:
  -----------
  exec/memory: Use correct type size

Use uint8_t for (unsigned) byte.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210518183655.1711377-7-philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 824f4bac9ffa2757293290c7edd065dc84a6521e
      
https://github.com/qemu/qemu/commit/824f4bac9ffa2757293290c7edd065dc84a6521e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M accel/tcg/cpu-exec.c
    M accel/tcg/translate-all.c
    M include/exec/exec-all.h
    M include/tcg/tcg.h
    M plugins/plugin.h

  Log Message:
  -----------
  accel/tcg: Reduce 'exec/tb-context.h' inclusion

Only 2 headers require "exec/tb-context.h". Instead of having
all files including "exec/exec-all.h" also including it, directly
include it where it is required:
- accel/tcg/cpu-exec.c
- accel/tcg/translate-all.c

For plugins/plugin.h, we were implicitly relying on
  exec/exec-all.h -> exec/tb-context.h -> qemu/qht.h
which is now included directly.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210524170453.3791436-2-f4bug@amsat.org>
[rth: Fix plugins/plugin.h compilation]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e5ceadff47ddec1513a56f96d9df246f62c90875
      
https://github.com/qemu/qemu/commit/e5ceadff47ddec1513a56f96d9df246f62c90875
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cpu-exec.c
    M accel/tcg/cputlb.c
    A accel/tcg/tb-context.h
    A accel/tcg/tb-hash.h
    A accel/tcg/tb-lookup.h
    M accel/tcg/tcg-runtime.c
    M accel/tcg/translate-all.c
    R include/exec/tb-context.h
    R include/exec/tb-hash.h
    R include/exec/tb-lookup.h

  Log Message:
  -----------
  accel/tcg: Keep TranslationBlock headers local to TCG

Only the TCG accelerator uses the TranslationBlock API.
Move the tb-context.h / tb-hash.h / tb-lookup.h from the
global namespace to the TCG one (in accel/tcg).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210524170453.3791436-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 57dcb643d79731b08a863444d6591d22552bc2e5
      
https://github.com/qemu/qemu/commit/57dcb643d79731b08a863444d6591d22552bc2e5
  Author: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M softmmu/physmem.c

  Log Message:
  -----------
  replay: fix watchpoint processing for reverse debugging

This patch enables reverse debugging with watchpoints.
Reverse continue scans the execution to find the breakpoints
and watchpoints that should fire. It uses helper function
replay_breakpoint() for that. But this function needs to access
icount, which can't be correct in the middle of TB.
Therefore, in case of watchpoint, we have to retranslate the block
to allow this access.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Message-Id: <162072430303.827403.7379783546934958566.stgit@pasha-ThinkPad-X280>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 26b1248f66c20f9d7fa384acecfdac03a0c8393d
      
https://github.com/qemu/qemu/commit/26b1248f66c20f9d7fa384acecfdac03a0c8393d
  Author: Yasuo Kuwahara <kwhr00@gmail.com>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Fix tcg_out_rotl

The last argument of tcg_out_extr() must be in the range 0-31 if ext==0.
Before the fix, when m==0 it becomes 32 and it crashes with an Illegal
instruction on Apple Silicon.  After the fix, it will be 0.  If m is in
the range 1-31, it is the same as before.

Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com>
Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 046943acf4f1d2aeec6f42f1cd4f37096d0b2c98
      
https://github.com/qemu/qemu/commit/046943acf4f1d2aeec6f42f1cd4f37096d0b2c98
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu.c

  Log Message:
  -----------
  cpu: Remove duplicated 'sysemu/hw_accel.h' header

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: df4fd7d5c8a334fc4305b35e92ce44479a7be656
      
https://github.com/qemu/qemu/commit/df4fd7d5c8a334fc4305b35e92ce44479a7be656
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    A hw/core/cpu-common.c
    A hw/core/cpu-sysemu.c
    R hw/core/cpu.c
    M hw/core/meson.build

  Log Message:
  -----------
  cpu: Split as cpu-common / cpu-sysemu

The current cpu.c contains sysemu-specific methods.
To avoid building them in user-mode builds, split the
current cpu.c as cpu-common.c / cpu-sysemu.c.

Start by moving cpu_get_crash_info().

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a41d3aae52c6b1657f665fcd26d122b0646cd330
      
https://github.com/qemu/qemu/commit/a41d3aae52c6b1657f665fcd26d122b0646cd330
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h

  Log Message:
  -----------
  cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs

To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-7-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: cdba7e2f497d3922a6934b7504925483b32c0a74
      
https://github.com/qemu/qemu/commit/cdba7e2f497d3922a6934b7504925483b32c0a74
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-common.c
    M hw/core/cpu-sysemu.c
    M hw/virtio/virtio.c
    M include/hw/core/cpu.h

  Log Message:
  -----------
  cpu: Introduce cpu_virtio_is_big_endian()

Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.

Similarly to commit bf7663c4bd8 ("cpu: introduce
CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method
name to hint this handler shouldn't be called anywhere but from the
virtio code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-8-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5ef2d5a48c98bcaca86b33755e175104802b44c3
      
https://github.com/qemu/qemu/commit/5ef2d5a48c98bcaca86b33755e175104802b44c3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-common.c
    M hw/core/cpu-sysemu.c

  Log Message:
  -----------
  cpu: Directly use cpu_write_elf*() fallback handlers in place

No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):

  $ git grep -F -- '->write_elf'
  hw/core/cpu.c:157:    return (*cc->write_elf32_qemunote)(f, cpu, opaque);
  hw/core/cpu.c:171:    return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
  hw/core/cpu.c:186:    return (*cc->write_elf64_qemunote)(f, cpu, opaque);
  hw/core/cpu.c:200:    return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
  hw/core/cpu.c:440:    k->write_elf32_qemunote = 
cpu_common_write_elf32_qemunote;
  hw/core/cpu.c:441:    k->write_elf32_note = cpu_common_write_elf32_note;
  hw/core/cpu.c:442:    k->write_elf64_qemunote = 
cpu_common_write_elf64_qemunote;
  hw/core/cpu.c:443:    k->write_elf64_note = cpu_common_write_elf64_note;
  target/arm/cpu.c:2304:    cc->write_elf64_note = arm_cpu_write_elf64_note;
  target/arm/cpu.c:2305:    cc->write_elf32_note = arm_cpu_write_elf32_note;
  target/i386/cpu.c:7425:    cc->write_elf64_note = x86_cpu_write_elf64_note;
  target/i386/cpu.c:7426:    cc->write_elf64_qemunote = 
x86_cpu_write_elf64_qemunote;
  target/i386/cpu.c:7427:    cc->write_elf32_note = x86_cpu_write_elf32_note;
  target/i386/cpu.c:7428:    cc->write_elf32_qemunote = 
x86_cpu_write_elf32_qemunote;
  target/ppc/translate_init.c.inc:10891:    cc->write_elf64_note = 
ppc64_cpu_write_elf64_note;
  target/ppc/translate_init.c.inc:10892:    cc->write_elf32_note = 
ppc32_cpu_write_elf32_note;
  target/s390x/cpu.c:522:    cc->write_elf64_note = s390_cpu_write_elf64_note;

Check the handler presence in place and remove the common fallback code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 77ba5d50bad66d56dde93e6f1c0b7a76b58ca290
      
https://github.com/qemu/qemu/commit/77ba5d50bad66d56dde93e6f1c0b7a76b58ca290
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-common.c
    M hw/core/cpu-sysemu.c

  Log Message:
  -----------
  cpu: Directly use get_paging_enabled() fallback handlers in place

No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:

  $ git grep -F -- '->get_paging_enabled'
  hw/core/cpu.c:74:    return cc->get_paging_enabled(cpu);
  hw/core/cpu.c:438:    k->get_paging_enabled = cpu_common_get_paging_enabled;
  target/i386/cpu.c:7418:    cc->get_paging_enabled = 
x86_cpu_get_paging_enabled;

Check the handler presence in place and remove the common fallback code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 65c57115dfeef8d344052a0e2b9d156b652be478
      
https://github.com/qemu/qemu/commit/65c57115dfeef8d344052a0e2b9d156b652be478
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-common.c
    M hw/core/cpu-sysemu.c

  Log Message:
  -----------
  cpu: Directly use get_memory_mapping() fallback handlers in place

No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:

  $ git grep -F -- '->get_memory_mapping'
  hw/core/cpu.c:87:    cc->get_memory_mapping(cpu, list, errp);
  hw/core/cpu.c:439:    k->get_memory_mapping = cpu_common_get_memory_mapping;
  target/i386/cpu.c:7422:    cc->get_memory_mapping = 
x86_cpu_get_memory_mapping;

Check the handler presence in place and remove the common fallback code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4336073b9b13943e050edfe9aebb99974c3b6ee1
      
https://github.com/qemu/qemu/commit/4336073b9b13943e050edfe9aebb99974c3b6ee1
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M cpu.c
    M target/sh4/cpu.c
    M target/xtensa/cpu.c

  Log Message:
  -----------
  cpu: Assert DeviceClass::vmsd is NULL on user emulation

Migration is specific to system emulation.

Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry,
and assert in cpu_exec_realizefn() that dc->vmsd not set under
user emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-12-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 744c72a837a0428f2d5373793e42aba963bf47c6
      
https://github.com/qemu/qemu/commit/744c72a837a0428f2d5373793e42aba963bf47c6
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M cpu.c
    M include/hw/core/cpu.h
    M target/arm/cpu.c
    M target/avr/cpu.c
    M target/i386/cpu.c
    M target/mips/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/s390x/cpu.c
    M target/sparc/cpu.c

  Log Message:
  -----------
  cpu: Rename CPUClass vmsd -> legacy_vmsd

Quoting Peter Maydell [*]:

  There are two ways to handle migration for
  a CPU object:

  (1) like any other device, so it has a dc->vmsd that covers
  migration for the whole object. As usual for objects that are a
  subclass of a parent that has state, the first entry in the
  VMStateDescription field list is VMSTATE_CPU(), which migrates
  the cpu_common fields, followed by whatever the CPU's own migration
  fields are.

  (2) a backwards-compatible mechanism for CPUs that were
  originally migrated using manual "write fields to the migration
  stream structures". The on-the-wire migration format
  for those is based on the 'env' pointer (which isn't a QOM object),
  and the cpu_common part of the migration data is elsewhere.

  cpu_exec_realizefn() handles both possibilities:

  * for type 1, dc->vmsd is set and cc->vmsd is not,
    so cpu_exec_realizefn() does nothing, and the standard
    "register dc->vmsd for a device" code does everything needed

  * for type 2, dc->vmsd is NULL and so we register the
    vmstate_cpu_common directly to handle the cpu-common fields,
    and the cc->vmsd to handle the per-CPU stuff

  You can't change a CPU from one type to the other without breaking
  migration compatibility, which is why some guest architectures
  are stuck on the cc->vmsd form. New targets should use dc->vmsd.

To avoid new targets to start using type (2), rename cc->vmsd as
cc->legacy_vmsd. The correct field to implement is dc->vmsd (the
DeviceClass one).

See also commit b170fce3dd0 ("cpu: Register VMStateDescription
through CPUState") for historic background.

[*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210517105140.1062037-13-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c2cf139d9c2f8f8b86686fe0e94a9daba27195a6
      
https://github.com/qemu/qemu/commit/c2cf139d9c2f8f8b86686fe0e94a9daba27195a6
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M target/avr/cpu.c
    M target/avr/machine.c

  Log Message:
  -----------
  cpu: Move AVR target vmsd field from CPUClass to DeviceClass

See rationale in previous commit. Targets should use the vmsd field
of DeviceClass, not CPUClass. As migration is not important on the
AVR target, break the migration compatibility and set the DeviceClass
vmsd field. To feel safer, increment the vmstate version.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210517105140.1062037-14-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3
      
https://github.com/qemu/qemu/commit/8b80bd28a5cf8d8af7d38abcf1c7d81a1b226ec3
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M cpu.c
    M include/hw/core/cpu.h
    A include/hw/core/sysemu-cpu-ops.h
    M target/alpha/cpu.c
    M target/arm/cpu.c
    M target/avr/cpu.c
    M target/cris/cpu.c
    M target/hppa/cpu.c
    M target/i386/cpu.c
    M target/m68k/cpu.c
    M target/microblaze/cpu.c
    M target/mips/cpu.c
    M target/nios2/cpu.c
    M target/openrisc/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/rx/cpu.c
    M target/s390x/cpu.c
    M target/sh4/cpu.c
    M target/sparc/cpu.c
    M target/tricore/cpu.c
    M target/xtensa/cpu.c

  Log Message:
  -----------
  cpu: Introduce SysemuCPUOps structure

Introduce a structure to hold handler specific to sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-15-f4bug@amsat.org>
[rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: feece4d07021576a6037adfd597598851cf32bf0
      
https://github.com/qemu/qemu/commit/feece4d07021576a6037adfd597598851cf32bf0
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M cpu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M include/migration/vmstate.h
    M stubs/vmstate.c
    M target/arm/cpu.c
    M target/i386/cpu.c
    M target/mips/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/s390x/cpu.c
    M target/sparc/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::vmsd to SysemuCPUOps

Migration is specific to system emulation.

- Move the CPUClass::vmsd field to SysemuCPUOps,
- restrict VMSTATE_CPU() macro to sysemu,
- vmstate_dummy is now unused, remove it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-16-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: da383e0263f7d711eddd4f050ca95fd5ab8d2a87
      
https://github.com/qemu/qemu/commit/da383e0263f7d711eddd4f050ca95fd5ab8d2a87
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/arm/cpu.c
    M target/ppc/cpu_init.c

  Log Message:
  -----------
  cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps

VirtIO devices are only meaningful with system emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-17-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 83ec01b675a731910b3b2183091302ad31b3482b
      
https://github.com/qemu/qemu/commit/83ec01b675a731910b3b2183091302ad31b3482b
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/i386/cpu.c
    M target/s390x/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::get_crash_info to SysemuCPUOps

cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-18-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 715e3c1afb0022fb2e0f60a198ed2c740e3c48f4
      
https://github.com/qemu/qemu/commit/715e3c1afb0022fb2e0f60a198ed2c740e3c48f4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/arm/cpu.c
    M target/i386/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/s390x/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::write_elf* to SysemuCPUOps

The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-19-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: faf39e828374d83ca82b02c0c25cdeca9ce9581e
      
https://github.com/qemu/qemu/commit/faf39e828374d83ca82b02c0c25cdeca9ce9581e
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/arm/cpu.c
    M target/i386/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-20-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 08928c6d0db7d554ef041256e52330bb257bc70f
      
https://github.com/qemu/qemu/commit/08928c6d0db7d554ef041256e52330bb257bc70f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/alpha/cpu.c
    M target/arm/cpu.c
    M target/avr/cpu.c
    M target/cris/cpu.c
    M target/hppa/cpu.c
    M target/i386/cpu.c
    M target/m68k/cpu.c
    M target/microblaze/cpu.c
    M target/mips/cpu.c
    M target/nios2/cpu.c
    M target/openrisc/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/rx/cpu.c
    M target/s390x/cpu.c
    M target/sh4/cpu.c
    M target/sparc/cpu.c
    M target/tricore/cpu.c
    M target/xtensa/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-21-f4bug@amsat.org>
[rth: Drop declaration movement from target/*/cpu.h]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2b60b62e05893de9698aa4a2c27de244870f0a50
      
https://github.com/qemu/qemu/commit/2b60b62e05893de9698aa4a2c27de244870f0a50
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/i386/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-22-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6bc0d6a04733cb39d2d2bf3380a857709113242f
      
https://github.com/qemu/qemu/commit/6bc0d6a04733cb39d2d2bf3380a857709113242f
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/core/cpu-sysemu.c
    M include/hw/core/cpu.h
    M include/hw/core/sysemu-cpu-ops.h
    M target/i386/cpu.c

  Log Message:
  -----------
  cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210517105140.1062037-23-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3803b6b4273afd50021c39a8e34ca706aeadb684
      
https://github.com/qemu/qemu/commit/3803b6b4273afd50021c39a8e34ca706aeadb684
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M hw/mips/jazz.c
    M target/mips/cpu-qom.h
    M target/mips/tcg/op_helper.c

  Log Message:
  -----------
  target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed

Add a flag to MIPSCPUClass in order to avoid needing to
replace mips_tcg_ops.do_transaction_failed.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>


  Commit: 119065574d02deffc28fe5b6a864db9b467c6ffd
      
https://github.com/qemu/qemu/commit/119065574d02deffc28fe5b6a864db9b467c6ffd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M include/hw/core/cpu.h
    M target/alpha/cpu.c
    M target/arm/cpu.c
    M target/arm/cpu_tcg.c
    M target/avr/cpu.c
    M target/cris/cpu.c
    M target/hexagon/cpu.c
    M target/hppa/cpu.c
    M target/i386/tcg/tcg-cpu.c
    M target/m68k/cpu.c
    M target/microblaze/cpu.c
    M target/mips/cpu.c
    M target/nios2/cpu.c
    M target/openrisc/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/rx/cpu.c
    M target/s390x/cpu.c
    M target/sh4/cpu.c
    M target/sparc/cpu.c
    M target/tricore/cpu.c
    M target/xtensa/cpu.c

  Log Message:
  -----------
  hw/core: Constify TCGCPUOps

We no longer have any runtime modifications to this struct,
so declare them all const.

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-3-richard.henderson@linaro.org>


  Commit: 62c0ac5041e9130b041adfa13a41583d3c3ddd24
      
https://github.com/qemu/qemu/commit/62c0ac5041e9130b041adfa13a41583d3c3ddd24
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-28 (Fri, 28 May 2021)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cpu-exec.c
    M accel/tcg/cputlb.c
    A accel/tcg/tb-context.h
    A accel/tcg/tb-hash.h
    A accel/tcg/tb-lookup.h
    M accel/tcg/tcg-runtime.c
    M accel/tcg/translate-all.c
    M cpu.c
    A hw/core/cpu-common.c
    A hw/core/cpu-sysemu.c
    R hw/core/cpu.c
    M hw/core/meson.build
    M hw/mips/jazz.c
    M hw/virtio/virtio.c
    M include/exec/exec-all.h
    M include/exec/memory.h
    M include/exec/memory_ldst.h.inc
    M include/exec/memory_ldst_cached.h.inc
    M include/exec/memory_ldst_phys.h.inc
    R include/exec/tb-context.h
    R include/exec/tb-hash.h
    R include/exec/tb-lookup.h
    M include/hw/core/cpu.h
    A include/hw/core/sysemu-cpu-ops.h
    M include/migration/vmstate.h
    M include/tcg/tcg.h
    M memory_ldst.c.inc
    M plugins/plugin.h
    M softmmu/physmem.c
    M stubs/vmstate.c
    M target/alpha/cpu.c
    M target/arm/cpu.c
    M target/arm/cpu_tcg.c
    M target/avr/cpu.c
    M target/avr/machine.c
    M target/cris/cpu.c
    M target/hexagon/cpu.c
    M target/hppa/cpu.c
    M target/i386/cpu.c
    M target/i386/tcg/tcg-cpu.c
    M target/m68k/cpu.c
    M target/microblaze/cpu.c
    M target/mips/cpu-qom.h
    M target/mips/cpu.c
    M target/mips/tcg/op_helper.c
    M target/nios2/cpu.c
    M target/openrisc/cpu.c
    M target/ppc/cpu_init.c
    M target/riscv/cpu.c
    M target/rx/cpu.c
    M target/s390x/cpu.c
    M target/sh4/cpu.c
    M target/sparc/cpu.c
    M target/tricore/cpu.c
    M target/xtensa/cpu.c
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into 
staging

Adjust types for some memory access functions.
Reduce inclusion of tcg headers.
Fix watchpoints vs replay.
Fix tcg/aarch64 roli expansion.
Introduce SysemuCPUOps structure.

# gpg: Signature made Thu 27 May 2021 00:43:54 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210526: (31 commits)
  hw/core: Constify TCGCPUOps
  target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
  cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
  cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
  cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
  cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
  cpu: Move CPUClass::write_elf* to SysemuCPUOps
  cpu: Move CPUClass::get_crash_info to SysemuCPUOps
  cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
  cpu: Move CPUClass::vmsd to SysemuCPUOps
  cpu: Introduce SysemuCPUOps structure
  cpu: Move AVR target vmsd field from CPUClass to DeviceClass
  cpu: Rename CPUClass vmsd -> legacy_vmsd
  cpu: Assert DeviceClass::vmsd is NULL on user emulation
  cpu: Directly use get_memory_mapping() fallback handlers in place
  cpu: Directly use get_paging_enabled() fallback handlers in place
  cpu: Directly use cpu_write_elf*() fallback handlers in place
  cpu: Introduce cpu_virtio_is_big_endian()
  cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
  cpu: Split as cpu-common / cpu-sysemu
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/7258034ab40e...62c0ac5041e9



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