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[Qemu-commits] [qemu/qemu] f334bb: target/m68k: introduce is_singlestepp


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] f334bb: target/m68k: introduce is_singlestepping() function
Date: Thu, 27 May 2021 11:23:20 -0700

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: f334bb2562dafbdc4ce673e5811bc9880758b147
      
https://github.com/qemu/qemu/commit/f334bb2562dafbdc4ce673e5811bc9880758b147
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: introduce is_singlestepping() function

The m68k translator currently checks the DisasContextBase singlestep_enabled
boolean directly to determine whether to single-step execution. Soon
single-stepping may also be triggered by setting the appropriate bits in the
SR register so centralise the check into a single is_singlestepping()
function.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 4f2b21efb398e93293e0fcd97b203563ff53e228
      
https://github.com/qemu/qemu/commit/4f2b21efb398e93293e0fcd97b203563ff53e228
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: call gen_raise_exception() directly if single-stepping in 
gen_jmp_tb()

In order to consolidate the single-step exception handling into a single
helper, change gen_jmp_tb() so that it calls gen_raise_exception() directly
instead of gen_exception(). This ensures that all single-step exceptions are
now handled directly by gen_raise_exception().

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 456a0e3b3c723d1d599d73920e98474ca9073386
      
https://github.com/qemu/qemu/commit/456a0e3b3c723d1d599d73920e98474ca9073386
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: introduce gen_singlestep_exception() function

Introduce a new gen_singlestep_exception() function to be called when generating
the EXCP_DEBUG exception in single-step mode rather than calling
gen_raise_exception(EXCP_DEBUG) directly. This allows for the single-step
exception behaviour for all callers to be managed in a single place.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 5e50c6c72bf8575f124ec9397411f4a2ff0d0206
      
https://github.com/qemu/qemu/commit/5e50c6c72bf8575f124ec9397411f4a2ff0d0206
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-05-26 (Wed, 26 May 2021)

  Changed paths:
    M target/m68k/cpu.h
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: implement m68k "any instruction" trace mode

The m68k trace mode is controlled by the top 2 bits in the SR register. 
Implement
the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the 
CPU
generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each
instruction.

This functionality is used by the NetBSD kernel debugger to allow 
single-stepping
on m68k architectures.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 7258034ab40e6927acbd005feb295eb3acf972bb
      
https://github.com/qemu/qemu/commit/7258034ab40e6927acbd005feb295eb3acf972bb
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-27 (Thu, 27 May 2021)

  Changed paths:
    M target/m68k/cpu.h
    M target/m68k/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.1-pull-request' 
into staging

m68k pull request 20210526

implement m68k "any instruction" trace mode

# gpg: Signature made Wed 26 May 2021 20:56:58 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" 
[full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-6.1-pull-request:
  target/m68k: implement m68k "any instruction" trace mode
  target/m68k: introduce gen_singlestep_exception() function
  target/m68k: call gen_raise_exception() directly if single-stepping in 
gen_jmp_tb()
  target/m68k: introduce is_singlestepping() function

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/c8616fc7670b...7258034ab40e



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