[Qemu-commits] [qemu/qemu] 219729: hw/arm/smmuv3: Another range invalida

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[Qemu-commits] [qemu/qemu] 219729: hw/arm/smmuv3: Another range invalida

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 219729: hw/arm/smmuv3: Another range invalidation fix
Date:	Tue, 25 May 2021 08:17:49 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 219729cfbf9e979020bffedac6a790144173ec62
      
https://github.com/qemu/qemu/commit/219729cfbf9e979020bffedac6a790144173ec62
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Another range invalidation fix

6d9cd115b9 ("hw/arm/smmuv3: Enforce invalidation on a power of two range")
failed to completely fix misalignment issues with range
invalidation. For instance invalidations patterns like "invalidate 32
4kB pages starting from 0xff395000 are not correctly handled" due
to the fact the previous fix only made sure the number of invalidated
pages were a power of 2 but did not properly handle the start
address was not aligned with the range. This can be noticed when
boothing a fedora 33 with protected virtio-blk-pci.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Fixes: 6d9cd115b9 ("hw/arm/smmuv3: Enforce invalidation on a power of two 
range")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 382c7160d1cd9e815fb94d3889a5ddcf0e1845ab
      
https://github.com/qemu/qemu/commit/382c7160d1cd9e815fb94d3889a5ddcf0e1845ab
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/intc/arm_gicv3_cpuif.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic

In icc_eoir_write() we assume that we can identify the group of the
IRQ being completed based purely on which register is being written
to and the current CPU state, and that "CPU state matches group
indicated by register" is the only necessary access check.

This isn't correct: if the CPU is not in Secure state then EOIR1 will
only complete Group 1 NS IRQs, but if the CPU is in EL3 it can
complete both Group 1 S and Group 1 NS IRQs.  (The pseudocode
ICC_EOIR1_EL1 makes this clear.) We were also missing the logic to
prevent EOIR0 writes completing G0 IRQs when they should not.

Rearrange the logic to first identify the group of the current
highest priority interrupt and then look at whether we should
complete it or ignore the access based on which register was accessed
and the state of the CPU.  The resulting behavioural change is:
 * EL3 can now complete G1NS interrupts
 * G0 interrupt completion is now ignored if the GIC
   and the CPU have the security extension enabled and
   the CPU is not secure

Reported-by: Chan Kim <ckim@etri.re.kr>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510150016.24910-1-peter.maydell@linaro.org


  Commit: b6889c5ae3895cf5a4322adb32b2133e9b91d158
      
https://github.com/qemu/qemu/commit/b6889c5ae3895cf5a4322adb32b2133e9b91d158
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Don't duplicate modelling of SRAM in AN524

The SRAM at 0x2000_0000 is part of the SSE-200 itself, and we model
it that way in hw/arm/armsse.c (along with the associated MPCs).  We
incorrectly also added an entry to the RAMInfo array for the AN524 in
hw/arm/mps2-tz.c, which was pointless because the CPU would never see
it.  Delete it.

The bug had no guest-visible effect because devices in the SSE-200
take priority over those in the board model (armsse.c maps
s->board_memory at priority -2).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-2-peter.maydell@linaro.org


  Commit: 902b28ae4eba6df303cba57016945426865a6d59
      
https://github.com/qemu/qemu/commit/902b28ae4eba6df303cba57016945426865a6d59
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Make SRAM_ADDR_WIDTH board-specific

The AN547 sets the SRAM_ADDR_WIDTH for the SSE-300 to 21;
since this is not the default value for the SSE-300, model this
in mps2-tz.c as a per-board value.

Reported-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-3-peter.maydell@linaro.org


  Commit: 4eb1770988397354ed95dec2bd63c09348ebf707
      
https://github.com/qemu/qemu/commit/4eb1770988397354ed95dec2bd63c09348ebf707
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/armsse.c

  Log Message:
  -----------
  hw/arm/armsse.c: Correct modelling of SSE-300 internal SRAMs

The SSE-300 was not correctly modelling its internal SRAMs:
 * the SRAM address width default is 18
 * the SRAM is mapped at 0x2100_0000, not 0x2000_0000 like
   the SSE-200 and IoTKit

The default address width is no longer guest-visible since
our only SSE-300 board sets it explicitly to a non-default
value, but following the hardware's default will help for
any future boards we need to model.

Reported-by: Devaraj Ranganna <devaraj.ranganna@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-4-peter.maydell@linaro.org


  Commit: 32962103523838faf15c070bff0fc75dfd2f42c8
      
https://github.com/qemu/qemu/commit/32962103523838faf15c070bff0fc75dfd2f42c8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/armsse.c

  Log Message:
  -----------
  hw/arm/armsse: Convert armsse_realize() to use ERRP_GUARD

Convert armsse_realize() to use ERRP_GUARD(), following
the rules in include/qapi/error.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-5-peter.maydell@linaro.org


  Commit: 2f12dca05928078ecc5c7d209a2bc5af61bff966
      
https://github.com/qemu/qemu/commit/2f12dca05928078ecc5c7d209a2bc5af61bff966
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Allow board to specify a boot RAM size

Currently we model the ITCM in the AN547's RAMInfo list. This is incorrect
because this RAM is really a part of the SSE-300. We can't just delete
it from the RAMInfo list, though, because this would make boot_ram_size()
assert because it wouldn't be able to find an entry in the list covering
guest address 0.

Allow a board to specify a boot RAM size manually if it doesn't have
any RAM itself at address 0 and is relying on the SSE for that, and
set the correct value for the AN547. The other boards can continue
to use the "look it up from the RAMInfo list" logic.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-6-peter.maydell@linaro.org


  Commit: cbb563887781d813e67c59b68dd76891cb78c3d4
      
https://github.com/qemu/qemu/commit/cbb563887781d813e67c59b68dd76891cb78c3d4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M hw/arm/armsse.c
    M hw/arm/mps2-tz.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm: Model TCMs in the SSE-300, not the AN547

The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000.
Currently we model these in the AN547 board, but this is conceptually
wrong, because they are a part of the SSE-300 itself. Move the
modelling of the TCMs out of mps2-tz.c into sse300.c.

This has no guest-visible effects.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210510190844.17799-7-peter.maydell@linaro.org


  Commit: 659f042ba8ef80ca1053042a781a4488f9a587dc
      
https://github.com/qemu/qemu/commit/659f042ba8ef80ca1053042a781a4488f9a587dc
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/m_helper.c

  Log Message:
  -----------
  target/arm: Use correct SP in M-profile exception return

When an M-profile CPU is restoring registers from the stack on
exception return, the stack pointer to use is determined based on
bits in the magic exception return type value.  We were not getting
this logic entirely correct.

Whether we use one of the Secure stack pointers or one of the
Non-Secure stack pointers depends on the EXCRET.S bit.  However,
whether we use the MSP or the PSP then depends on the SPSEL bit in
either the CONTROL_S or CONTROL_NS register.  We were incorrectly
selecting MSP vs PSP based on the EXCRET.SPSEL bit.

(In the pseudocode this is in the PopStack() function, which calls
LookUpSp_with_security_mode() which in turn looks at the relevant
CONTROL.SPSEL bit.)

The buggy behaviour wasn't noticeable in most cases, because we write
EXCRET.SPSEL to the CONTROL.SPSEL bit for the S/NS register selected
by EXCRET.ES, so we only do the wrong thing when EXCRET.S and
EXCRET.ES are different.  This will happen when secure code takes a
secure exception, which then tail-chains to a non-secure exception
which finally returns to the original secure code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520130905.2049-1-peter.maydell@linaro.org


  Commit: 6d244788616a286fa0bceaca68a6b8b6aa7b40f7
      
https://github.com/qemu/qemu/commit/6d244788616a286fa0bceaca68a6b8b6aa7b40f7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Replace g_new() + memcpy() by g_memdup()

Using g_memdup is a bit more compact than g_new + memcpy.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-2-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3c4ddec169836c0dfc955d662dc0cc4f82ba7993
      
https://github.com/qemu/qemu/commit/3c4ddec169836c0dfc955d662dc0cc4f82ba7993
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Pass length argument to tlb_flush_range_locked()

Rename tlb_flush_page_bits_locked() -> tlb_flush_range_locked(), and
have callers pass a length argument (currently TARGET_PAGE_SIZE) via
the TLBFlushPageBitsByMMUIdxData structure.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-3-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3960a59f8d10cde717a4187c3d3aad93b1c1e472
      
https://github.com/qemu/qemu/commit/3960a59f8d10cde717a4187c3d3aad93b1c1e472
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData

Rename the structure to match the rename of tlb_flush_range_locked.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-4-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d34e4d1afa1507f8851aa38dc1e74bacd5d7668f
      
https://github.com/qemu/qemu/commit/d34e4d1afa1507f8851aa38dc1e74bacd5d7668f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Remove {encode,decode}_pbm_to_runon

We will not be able to fit address + length into a 64-bit packet.
Drop this optimization before re-organizing this code.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-10-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMM: Moved patch earlier in the series]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e5b1921bd45d8d882016d08d9afc514091c15142
      
https://github.com/qemu/qemu/commit/e5b1921bd45d8d882016d08d9afc514091c15142
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  accel/tcg: Add tlb_flush_range_by_mmuidx()

Forward tlb_flush_page_bits_by_mmuidx to tlb_flush_range_by_mmuidx
passing TARGET_PAGE_SIZE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-5-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 600b819f235d6b6eb33fc33e09fe64f53eb9a9a6
      
https://github.com/qemu/qemu/commit/600b819f235d6b6eb33fc33e09fe64f53eb9a9a6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus()

Forward tlb_flush_page_bits_by_mmuidx_all_cpus to
tlb_flush_range_by_mmuidx_all_cpus passing TARGET_PAGE_SIZE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-6-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c13b27d826797ee12dcf4e4c289a7a6c401e620b
      
https://github.com/qemu/qemu/commit/c13b27d826797ee12dcf4e4c289a7a6c401e620b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()

Forward tlb_flush_page_bits_by_mmuidx_all_cpus_synced to
tlb_flush_range_by_mmuidx_all_cpus_synced passing TARGET_PAGE_SIZE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-7-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6be48e45ac996cb5186dc77ca91bff812ed27f85
      
https://github.com/qemu/qemu/commit/6be48e45ac996cb5186dc77ca91bff812ed27f85
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0

Rename to match tlb_flush_range_locked.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-8-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 206a583d13246b7b516318333f55cfba490c7037
      
https://github.com/qemu/qemu/commit/206a583d13246b7b516318333f55cfba490c7037
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1]

Rename to match tlb_flush_range_locked.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210509151618.2331764-9-f4bug@amsat.org
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 84940ed82552d3c7c7327c83076b02cee7978257
      
https://github.com/qemu/qemu/commit/84940ed82552d3c7c7327c83076b02cee7978257
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for FEAT_TLBIRANGE

ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI
maintenance instructions that apply to a range of input addresses.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210512182337.18563-2-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7113d618505b1ba7a0b029df2d2617a0d0259e37
      
https://github.com/qemu/qemu/commit/7113d618505b1ba7a0b029df2d2617a0d0259e37
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add support for FEAT_TLBIOS

ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI
maintenance instructions that extend to the Outer Shareable domain.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210512182337.18563-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7b9171cc83f37d078ae7d544d2bacd6a851453d8
      
https://github.com/qemu/qemu/commit/7b9171cc83f37d078ae7d544d2bacd6a851453d8
  Author: Rebecca Cran <rebecca@nuviainc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210512182337.18563-4-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2fed21d25b3a95628698825d682d7386c5a08ae2
      
https://github.com/qemu/qemu/commit/2fed21d25b3a95628698825d682d7386c5a08ae2
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M disas/libvixl/vixl/code-buffer.h
    M disas/libvixl/vixl/globals.h
    M disas/libvixl/vixl/invalset.h
    M disas/libvixl/vixl/platform.h
    M disas/libvixl/vixl/utils.cc
    M disas/libvixl/vixl/utils.h

  Log Message:
  -----------
  disas/libvixl: Protect C system header for C++ compiler

When selecting an ARM target on Debian unstable, we get:

  Compiling C++ object libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
  FAILED: libcommon.fa.p/disas_libvixl_vixl_utils.cc.o
  c++ -Ilibcommon.fa.p -I. -I.. [...] -o 
libcommon.fa.p/disas_libvixl_vixl_utils.cc.o -c ../disas/libvixl/vixl/utils.cc
  In file included from /home/philmd/qemu/disas/libvixl/vixl/utils.h:30,
                   from ../disas/libvixl/vixl/utils.cc:27:
  /usr/include/string.h:36:43: error: missing binary operator before token "("
     36 | #if defined __cplusplus && (__GNUC_PREREQ (4, 4) \
        |                                           ^
  /usr/include/string.h:53:62: error: missing binary operator before token "("
     53 | #if defined __USE_MISC || defined __USE_XOPEN || __GLIBC_USE (ISOC2X)
        |                                                              ^
  /usr/include/string.h:165:21: error: missing binary operator before token "("
    165 |      || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE (ISOC2X))
        |                     ^
  /usr/include/string.h:174:43: error: missing binary operator before token "("
    174 | #if defined __USE_XOPEN2K8 || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE 
(ISOC2X)
        |                                           ^
  /usr/include/string.h:492:19: error: missing binary operator before token "("
    492 | #if __GNUC_PREREQ (3,4)
        |                   ^

Relevant information from the host:

  $ lsb_release -d
  Description:    Debian GNU/Linux 11 (bullseye)
  $ gcc --version
  gcc (Debian 10.2.1-6) 10.2.1 20210110
  $ dpkg -S /usr/include/string.h
  libc6-dev: /usr/include/string.h
  $ apt-cache show libc6-dev
  Package: libc6-dev
  Version: 2.31-11

Partially cherry-pick vixl commit 78973f258039f6e96 [*]:

  Refactor VIXL to use `extern` block when including C header
  that do not have a C++ counterpart.

which is similar to commit 875df03b221 ('osdep: protect qemu/osdep.h
with extern "C"').

[*] https://git.linaro.org/arm/vixl.git/commit/?id=78973f258039f6e96

Buglink: https://bugs.launchpad.net/qemu/+bug/1914870
Suggested-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20210516171023.510778-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2dc10fa2f900fbb6fa5573c6c9411145b3a166f9
      
https://github.com/qemu/qemu/commit/2dc10fa2f900fbb6fa5573c6c9411145b3a166f9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2

Will be used for SVE2 isa subset enablement.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5dad1ba52f39f1c0bbf76c20b0b9f30636b51c88
      
https://github.com/qemu/qemu/commit/5dad1ba52f39f1c0bbf76c20b0b9f30636b51c88
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 Integer Multiply - Unpredicated

For MUL, we can rely on generic support.  For SMULH and UMULH,
create some trivial helpers.  For PMUL, back in a21bb78e5817,
we organized helper_gvec_pmul_b in preparation for this use.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d4b1e59d98470534246bbe369de8a0b40cb5d399
      
https://github.com/qemu/qemu/commit/d4b1e59d98470534246bbe369de8a0b40cb5d399
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer pairwise add and accumulate long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: db366da809bf18749e43f6cbd947ffc596500675
      
https://github.com/qemu/qemu/commit/db366da809bf18749e43f6cbd947ffc596500675
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer unary operations (predicated)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8b3f15b0a3b6d6ffbe7dfcb8dfbceb6d8da7ee6a
      
https://github.com/qemu/qemu/commit/8b3f15b0a3b6d6ffbe7dfcb8dfbceb6d8da7ee6a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/neon_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Split out saturating/rounding shifts from neon

Split these operations out into a header that can be shared
between neon and sve.  The "sat" pointer acts both as a boolean
for control of saturating behavior and controls the difference
in behavior between neon and sve -- QC bit or no QC bit.

Widen the shift operand in the new helpers, as the SVE2 insns treat
the whole input element as significant.  For the neon uses, truncate
the shift to int8_t while passing the parameter.

Implement right-shift rounding as

    tmp = src >> (shift - 1);
    dst = (tmp >> 1) + (tmp & 1);

This is the same number of instructions as the current

    tmp = 1 << (shift - 1);
    dst = (src + tmp) >> shift;

without any possibility of intermediate overflow.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 45d9503d0a44a3ccc1e009dea88fd453c7cc3026
      
https://github.com/qemu/qemu/commit/45d9503d0a44a3ccc1e009dea88fd453c7cc3026
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a47dc220e98c32d422e042c68ddb769c5df990b5
      
https://github.com/qemu/qemu/commit/a47dc220e98c32d422e042c68ddb769c5df990b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer halving add/subtract (predicated)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8597dc8b86883c25c95f15db8ffd93da2856d9b4
      
https://github.com/qemu/qemu/commit/8597dc8b86883c25c95f15db8ffd93da2856d9b4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer pairwise arithmetic

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4f07fbebb154240769ac48ccfc30e776273b266b
      
https://github.com/qemu/qemu/commit/4f07fbebb154240769ac48ccfc30e776273b266b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating add/subtract (predicated)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0ce1dda8b6fe764d6704d1226a9c67569d15238a
      
https://github.com/qemu/qemu/commit/0ce1dda8b6fe764d6704d1226a9c67569d15238a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer add/subtract long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: daec426b2d16a422dc90dfa01b382aef50f2e23d
      
https://github.com/qemu/qemu/commit/daec426b2d16a422dc90dfa01b382aef50f2e23d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer add/subtract interleaved long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 81fccf092285731a05d9354159c3cd2d1a92fed9
      
https://github.com/qemu/qemu/commit/81fccf092285731a05d9354159c3cd2d1a92fed9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer add/subtract wide

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 69ccc0991b92471b6626c54ccb5e2910eb0c71bb
      
https://github.com/qemu/qemu/commit/69ccc0991b92471b6626c54ccb5e2910eb0c71bb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer multiply long

Exclude PMULL from this category for the moment.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e3a561318327417523693f94e99745516f690eb7
      
https://github.com/qemu/qemu/commit/e3a561318327417523693f94e99745516f690eb7
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 PMULLB, PMULLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4269fef1f901927dd2c56deea6c45da8e8c5170e
      
https://github.com/qemu/qemu/commit/4269fef1f901927dd2c56deea6c45da8e8c5170e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise shift left long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2df3ca5599055d891940153a1fd544a77a231e80
      
https://github.com/qemu/qemu/commit/2df3ca5599055d891940153a1fd544a77a231e80
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise exclusive-or interleaved

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cb9c33b817d8c6057f6f6a190e964d2c1e26f2a2
      
https://github.com/qemu/qemu/commit/cb9c33b817d8c6057f6f6a190e964d2c1e26f2a2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise permute

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ed4a63872634ad7ce07e36b2c1beabcb0df4a986
      
https://github.com/qemu/qemu/commit/ed4a63872634ad7ce07e36b2c1beabcb0df4a986
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 complex integer add

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 38650638fbc6749d08a73466d2772d5e26ae6185
      
https://github.com/qemu/qemu/commit/38650638fbc6749d08a73466d2772d5e26ae6185
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer absolute difference and accumulate long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b8295dfb48e5672a66db7815ea3c0e0c40893028
      
https://github.com/qemu/qemu/commit/b8295dfb48e5672a66db7815ea3c0e0c40893028
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer add/subtract long with carry

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a7e3a90e7322c70586e8d8478cf27e8a91a0ca74
      
https://github.com/qemu/qemu/commit/a7e3a90e7322c70586e8d8478cf27e8a91a0ca74
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise shift right and accumulate

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc12b46a461bf6d3632e7c86587e17c379bc5082
      
https://github.com/qemu/qemu/commit/fc12b46a461bf6d3632e7c86587e17c379bc5082
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise shift and insert

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 289a17976d425a576d9e682037ec59d197b14b80
      
https://github.com/qemu/qemu/commit/289a17976d425a576d9e682037ec59d197b14b80
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer absolute difference and accumulate

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5ff2838d3d79ffa69233da31ee548af6eca3e7ce
      
https://github.com/qemu/qemu/commit/5ff2838d3d79ffa69233da31ee548af6eca3e7ce
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating extract narrow

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b87dbeebe6c8e236cc8abf74ec15e63765af5b61
      
https://github.com/qemu/qemu/commit/b87dbeebe6c8e236cc8abf74ec15e63765af5b61
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 floating-point pairwise

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 46d111b243b979a5b79d20abb0269a7d340d3a7c
      
https://github.com/qemu/qemu/commit/46d111b243b979a5b79d20abb0269a7d340d3a7c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 SHRN, RSHRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 81fd3e6e4f02690b57a51ae53da2ff280712ae1f
      
https://github.com/qemu/qemu/commit/81fd3e6e4f02690b57a51ae53da2ff280712ae1f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c13418da7612fe4290209981f589a8370c13c04b
      
https://github.com/qemu/qemu/commit/c13418da7612fe4290209981f589a8370c13c04b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 UQSHRN, UQRSHRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 743bb147733170b86a4d7d34ac83873ddc9c7061
      
https://github.com/qemu/qemu/commit/743bb147733170b86a4d7d34ac83873ddc9c7061
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 SQSHRN, SQRSHRN

This completes the section "SVE2 bitwise shift right narrow".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 34688dbc1c49dfbdd6d87bfddaae1b0b338e18cb
      
https://github.com/qemu/qemu/commit/34688dbc1c49dfbdd6d87bfddaae1b0b338e18cb
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 14f6dad168e89cd23e1c164f1563323ff885a48a
      
https://github.com/qemu/qemu/commit/14f6dad168e89cd23e1c164f1563323ff885a48a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 WHILERW, WHILEWR

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 911cdc6d79d4310e842cd11f0c5c08cb47f6efd0
      
https://github.com/qemu/qemu/commit/911cdc6d79d4310e842cd11f0c5c08cb47f6efd0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise ternary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e0ae6ec38329b48b4e69a2f67d4d88b732d9d823
      
https://github.com/qemu/qemu/commit/e0ae6ec38329b48b4e69a2f67d4d88b732d9d823
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 MATCH, NMATCH

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-34-richard.henderson@linaro.org
Message-Id: <20200415145915.2859-1-steplong@quicinc.com>
[rth: Expanded comment for do_match2]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bfc9307ee1ccec92ba7191c307f4aa3bb0eb6eac
      
https://github.com/qemu/qemu/commit/bfc9307ee1ccec92ba7191c307f4aa3bb0eb6eac
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply-add long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ab3ddf3185422eaacab6835d6eb70b068b3a0039
      
https://github.com/qemu/qemu/commit/ab3ddf3185422eaacab6835d6eb70b068b3a0039
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON,
there is no saturation flag.  Create new entry points for SVE2
that do not set QC.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 45a32e80b913c25fbdff661e9fcd5ea2f164a1f9
      
https://github.com/qemu/qemu/commit/45a32e80b913c25fbdff661e9fcd5ea2f164a1f9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer multiply-add long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d782d3ca9fc2f572607fe03b6e55514716981157
      
https://github.com/qemu/qemu/commit/d782d3ca9fc2f572607fe03b6e55514716981157
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Implement SVE2 complex integer multiply-add

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 40d5ea508eef797adfd1863acf15224ab79e0aaf
      
https://github.com/qemu/qemu/commit/40d5ea508eef797adfd1863acf15224ab79e0aaf
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 ADDHNB, ADDHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-39-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-2-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0ea3ff02c21cb9f515c4a0bcf83d07a47b1040b1
      
https://github.com/qemu/qemu/commit/0ea3ff02c21cb9f515c4a0bcf83d07a47b1040b1
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 RADDHNB, RADDHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-40-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c3cd676685af87d1084e5b974b4ef2ca39405c64
      
https://github.com/qemu/qemu/commit/c3cd676685af87d1084e5b974b4ef2ca39405c64
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 SUBHNB, SUBHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-41-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-4-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e9443d1098d108243f2a7a8b87550e9a5980b840
      
https://github.com/qemu/qemu/commit/e9443d1098d108243f2a7a8b87550e9a5980b840
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 RSUBHNB, RSUBHNT

This completes the section 'SVE2 integer add/subtract narrow high part'

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-42-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-5-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d47ac94a7c15e820d41adda4cf706c2001e675c
      
https://github.com/qemu/qemu/commit/7d47ac94a7c15e820d41adda4cf706c2001e675c
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 HISTCNT, HISTSEG

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-43-richard.henderson@linaro.org
Message-Id: <20200416173109.8856-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e6eba6e532a5f19519d925c8f68da032537abcac
      
https://github.com/qemu/qemu/commit/e6eba6e532a5f19519d925c8f68da032537abcac
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6ebca45faffd697a045f1d54800d00c6f77c5eb9
      
https://github.com/qemu/qemu/commit/6ebca45faffd697a045f1d54800d00c6f77c5eb9
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 scatter store insns

Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.

64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)

32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-45-richard.henderson@linaro.org
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cf327449816d5643106445420a0b06b0f38d4f01
      
https://github.com/qemu/qemu/commit/cf327449816d5643106445420a0b06b0f38d4f01
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 gather load insns

Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.

64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)

32-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-46-richard.henderson@linaro.org
Message-Id: <20200422152343.12493-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4f26756b8758f28f9f2eb5846cdbd5c0b024dc34
      
https://github.com/qemu/qemu/commit/4f26756b8758f28f9f2eb5846cdbd5c0b024dc34
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 FMMLA

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-47-richard.henderson@linaro.org
Message-Id: <20200422165503.13511-1-steplong@quicinc.com>
[rth: Fix indexing in helpers, expand macro to straight functions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 751147928eaa46c3d9ce229ec5be9982590d8297
      
https://github.com/qemu/qemu/commit/751147928eaa46c3d9ce229ec5be9982590d8297
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 SPLICE, EXT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-48-richard.henderson@linaro.org
Message-Id: <20200423180347.9403-1-steplong@quicinc.com>
[rth: Rename the trans_* functions to *_sve2.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 77e786bb958c1fa6f51d94aac6e6c9202ce665ef
      
https://github.com/qemu/qemu/commit/77e786bb958c1fa6f51d94aac6e6c9202ce665ef
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Use correct output type for gvec_sdot_*_b

The signed dot product routines produce a signed result.
Since we use -fwrapv, there is no functional change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-49-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bc2bd6974ef152f0539681afd9875eddaa8e62d9
      
https://github.com/qemu/qemu/commit/bc2bd6974ef152f0539681afd9875eddaa8e62d9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the
movprfx instruction.  Currently we do not optimize movprfx,
so the problem is not visible.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 636ddeb15c086e67c29751764eb7fa77450a1d66
      
https://github.com/qemu/qemu/commit/636ddeb15c086e67c29751764eb7fa77450a1d66
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the
movprfx instruction.  Currently we do not optimize movprfx,
so the problem is not visible.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-51-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1c737d9c5f133bc83f69ae1e81fd424e1e32b4c2
      
https://github.com/qemu/qemu/commit/1c737d9c5f133bc83f69ae1e81fd424e1e32b4c2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode

  Log Message:
  -----------
  target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-52-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0a82d963b7e12711921a1e9de4fb74aee3bfd89b
      
https://github.com/qemu/qemu/commit/0a82d963b7e12711921a1e9de4fb74aee3bfd89b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more.
Split FMLA from FMLS to avoid an extra sub field;
similarly for SDOT from UDOT.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 814d4c521f6ff04b93de24d8de72e1c59da1485f
      
https://github.com/qemu/qemu/commit/814d4c521f6ff04b93de24d8de72e1c59da1485f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer multiply (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-54-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8a02aac74012290b32eb44fd8d6f893683da4ed5
      
https://github.com/qemu/qemu/commit/8a02aac74012290b32eb44fd8d6f893683da4ed5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer multiply-add (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-55-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 75d6d5fc330adc239f6383785bef3625c75af8b6
      
https://github.com/qemu/qemu/commit/75d6d5fc330adc239f6383785bef3625c75af8b6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply-add high (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c5c455d78370a986edbad21e6ff88a37ab3e1039
      
https://github.com/qemu/qemu/commit/c5c455d78370a986edbad21e6ff88a37ab3e1039
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply-add (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-57-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b95f5eebf6be4ebcc8ff13aaa5d93431c20e9b07
      
https://github.com/qemu/qemu/commit/b95f5eebf6be4ebcc8ff13aaa5d93431c20e9b07
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-58-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 169d7c58253414d2d845e721ac9334795075fd88
      
https://github.com/qemu/qemu/commit/169d7c58253414d2d845e721ac9334795075fd88
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 signed saturating doubling multiply high

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-59-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1aee2d70e345877d67b16dd01006dd52cf361551
      
https://github.com/qemu/qemu/commit/1aee2d70e345877d67b16dd01006dd52cf361551
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 saturating multiply high (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-60-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d462469fc68094b1cedc58d6867f5a0df84a709b
      
https://github.com/qemu/qemu/commit/d462469fc68094b1cedc58d6867f5a0df84a709b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 multiply-add long (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-61-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d3949c4c7b6017ce492db4cd5398234041dda9c4
      
https://github.com/qemu/qemu/commit/d3949c4c7b6017ce492db4cd5398234041dda9c4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 integer multiply long (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-62-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3b787ed8084364f51c55536549f9591b3351437e
      
https://github.com/qemu/qemu/commit/3b787ed8084364f51c55536549f9591b3351437e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 complex integer multiply-add (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-63-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 21068f39725bbb7854b92dcbf4abd16f0ac907a6
      
https://github.com/qemu/qemu/commit/21068f39725bbb7854b92dcbf4abd16f0ac907a6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 complex integer dot product

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-64-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5c57e3b9542a0bf0acd9841149817f45f1fab6f0
      
https://github.com/qemu/qemu/commit/5c57e3b9542a0bf0acd9841149817f45f1fab6f0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Macroize helper_gvec_{s,u}dot_{b,h}

We're about to add more variations on this theme.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-65-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7020ffd656a5980f4aca87e61c95d82cc4707fd6
      
https://github.com/qemu/qemu/commit/7020ffd656a5980f4aca87e61c95d82cc4707fd6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}

We're about to add more variations on this theme.
Accept the inner loop for the _h variants, rather
than keep it unrolled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-66-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2867039a9fb68866673f73d48d43761c1133e4db
      
https://github.com/qemu/qemu/commit/2867039a9fb68866673f73d48d43761c1133e4db
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE mixed sign dot product (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-67-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6a98cb2ae07ad1f1066d3d4d2a945e0d046bde77
      
https://github.com/qemu/qemu/commit/6a98cb2ae07ad1f1066d3d4d2a945e0d046bde77
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE mixed sign dot product

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-68-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b2bcd1be4b93dc43034123757d6a5c5145a149dd
      
https://github.com/qemu/qemu/commit/b2bcd1be4b93dc43034123757d6a5c5145a149dd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 crypto unary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-69-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3cc7a88e0de813615794156e2b272e1b2ba2e72a
      
https://github.com/qemu/qemu/commit/3cc7a88e0de813615794156e2b272e1b2ba2e72a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 crypto destructive binary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-70-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3358eb3fb71a4f1663f3260773e5cf7ced7879c8
      
https://github.com/qemu/qemu/commit/3358eb3fb71a4f1663f3260773e5cf7ced7879c8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 crypto constructive binary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-71-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 80a712a2bec1162b18721303903541ba684a0ac7
      
https://github.com/qemu/qemu/commit/80a712a2bec1162b18721303903541ba684a0ac7
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 TBL, TBX

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-72-richard.henderson@linaro.org
Message-Id: <20200428144352.9275-1-steplong@quicinc.com>
[rth: rearrange the macros a little and rebase]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5c1b7226f554d00ce4c0692e826612aefc8eeb3d
      
https://github.com/qemu/qemu/commit/5c1b7226f554d00ce4c0692e826612aefc8eeb3d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 FCVTNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-73-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-2-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 83c2523f80ddef26b1c295db388f55ca95d8dd79
      
https://github.com/qemu/qemu/commit/83c2523f80ddef26b1c295db388f55ca95d8dd79
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 FCVTLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-74-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9536527731d099fb4a2dea1b83a1d915738fa172
      
https://github.com/qemu/qemu/commit/9536527731d099fb4a2dea1b83a1d915738fa172
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 FCVTXNT, FCVTX

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-75-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-4-steplong@quicinc.com>
[rth: Use do_frint_mode, which avoids a specific runtime helper.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 631be02e29ad47eae4ad23c55e4e5631146151d9
      
https://github.com/qemu/qemu/commit/631be02e29ad47eae4ad23c55e4e5631146151d9
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 FLOGB

Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-76-richard.henderson@linaro.org
Message-Id: <20200430191405.21641-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c182c6dbd141e7d3e43f75e21630863a291acb89
      
https://github.com/qemu/qemu/commit/c182c6dbd141e7d3e43f75e21630863a291acb89
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa;
we can share them by passing dtype instead of msz to do_ldrq.

The lack of MTE handling in do_ldrq was a bug, fixed by this change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-77-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7924d239f42ba6e0f4edc8bda59571f50fcb34e2
      
https://github.com/qemu/qemu/commit/7924d239f42ba6e0f4edc8bda59571f50fcb34e2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Tidy do_ldrq

Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-78-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 12c563f683397f13615bc89ef82ba2c8d500d96a
      
https://github.com/qemu/qemu/commit/12c563f683397f13615bc89ef82ba2c8d500d96a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 LD1RO

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-79-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 74b64b2562fc9798765f2a9b883b678666b71215
      
https://github.com/qemu/qemu/commit/74b64b2562fc9798765f2a9b883b678666b71215
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement 128-bit ZIP, UZP, TRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-80-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a5421b54c4a333c8b3aa342cae23180d8d0ecd04
      
https://github.com/qemu/qemu/commit/a5421b54c4a333c8b3aa342cae23180d8d0ecd04
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE2 bitwise shift immediate

Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-81-richard.henderson@linaro.org
Message-Id: <20200430194159.24064-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 93966af1d38213b26ef6efc4719851cbc18ec64f
      
https://github.com/qemu/qemu/commit/93966af1d38213b26ef6efc4719851cbc18ec64f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  target/arm: Move endian adjustment macros to vec_internal.h

We have two copies of these, one set of which is not complete.
Move them to a common header.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-82-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 50d102bd42a66fb19e268ecfb5e39c8e0c2b3b0e
      
https://github.com/qemu/qemu/commit/50d102bd42a66fb19e268ecfb5e39c8e0c2b3b0e
  Author: Stephen Long <steplong@quicinc.com>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE2 fp multiply-add long

Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-83-richard.henderson@linaro.org
Message-Id: <20200504171240.11220-1-steplong@quicinc.com>
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f7da051f5eb349b5bcf34db64fac17b89e869f81
      
https://github.com/qemu/qemu/commit/f7da051f5eb349b5bcf34db64fac17b89e869f81
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Implement aarch64 SUDOT, USDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-84-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 505fce5060eac5daf04abbdc0f347ddd53a73c66
      
https://github.com/qemu/qemu/commit/505fce5060eac5daf04abbdc0f347ddd53a73c66
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-85-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 25fa6f8341f4dda26f43182090ec9cf9fd8ee7ce
      
https://github.com/qemu/qemu/commit/25fa6f8341f4dda26f43182090ec9cf9fd8ee7ce
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-86-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 64ea60869be0fc80e32055912fe3c1a55290231c
      
https://github.com/qemu/qemu/commit/64ea60869be0fc80e32055912fe3c1a55290231c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm.  Remove the incorrect
name and remove the incorrect decode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5a46304c03265d2c632583436b8d7c8641fa0d16
      
https://github.com/qemu/qemu/commit/5a46304c03265d2c632583436b8d7c8641fa0d16
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Split out do_neon_ddda

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-88-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f0ad96cb28637a91f7904b83b55a001e294e62c0
      
https://github.com/qemu/qemu/commit/f0ad96cb28637a91f7904b83b55a001e294e62c0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not
save much.  Also, this will solve an upcoming naming problem.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-89-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 51879c671b7b0bf513cac6a5386097c8cfd17b3c
      
https://github.com/qemu/qemu/commit/51879c671b7b0bf513cac6a5386097c8cfd17b3c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/neon-shared.decode
    M target/arm/translate-neon.c

  Log Message:
  -----------
  target/arm: Implement aarch32 VSUDOT, VUSDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-90-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2323c5ffd4b5c705e768c2f457bc3298a46bf856
      
https://github.com/qemu/qemu/commit/2323c5ffd4b5c705e768c2f457bc3298a46bf856
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon-shared.decode
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE,
and V{S,U,US}MMLA.S8 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-91-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: cdc8d8b273379a2842ad5cd220299352ea23065e
      
https://github.com/qemu/qemu/commit/cdc8d8b273379a2842ad5cd220299352ea23065e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user/aarch64: Enable hwcap bits for sve2 and related extensions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-92-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f8680aaa6e5bfc6022b75157c23db7d2ea98ab11
      
https://github.com/qemu/qemu/commit/f8680aaa6e5bfc6022b75157c23db7d2ea98ab11
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c

  Log Message:
  -----------
  target/arm: Enable SVE2 and related extensions

Disable I8MM again for !have_neon during realize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-93-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 92f8c6fef13b31ba222c4d20ad8afd2b79c4c28e
      
https://github.com/qemu/qemu/commit/92f8c6fef13b31ba222c4d20ad8afd2b79c4c28e
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-25 (Tue, 25 May 2021)

  Changed paths:
    M accel/tcg/cputlb.c
    M disas/libvixl/vixl/code-buffer.h
    M disas/libvixl/vixl/globals.h
    M disas/libvixl/vixl/invalset.h
    M disas/libvixl/vixl/platform.h
    M disas/libvixl/vixl/utils.cc
    M disas/libvixl/vixl/utils.h
    M hw/arm/armsse.c
    M hw/arm/mps2-tz.c
    M hw/arm/smmuv3.c
    M hw/intc/arm_gicv3_cpuif.c
    M include/exec/exec-all.h
    M include/hw/arm/armsse.h
    M linux-user/elfload.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper-sve.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/kvm64.c
    M target/arm/m_helper.c
    M target/arm/neon-shared.decode
    M target/arm/neon_helper.c
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-a64.h
    M target/arm/translate-neon.c
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c
    M target/arm/vec_internal.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210525' 
into staging

target-arm queue:
 * Implement SVE2 emulation
 * Implement integer matrix multiply accumulate
 * Implement FEAT_TLBIOS
 * Implement FEAT_TLBRANGE
 * disas/libvixl: Protect C system header for C++ compiler
 * Use correct SP in M-profile exception return
 * AN524, AN547: Correct modelling of internal SRAMs
 * hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic
 * hw/arm/smmuv3: Another range invalidation fix

# gpg: Signature made Tue 25 May 2021 16:02:25 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210525: (114 commits)
  target/arm: Enable SVE2 and related extensions
  linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
  target/arm: Implement integer matrix multiply accumulate
  target/arm: Implement aarch32 VSUDOT, VUSDOT
  target/arm: Split decode of VSDOT and VUDOT
  target/arm: Split out do_neon_ddda
  target/arm: Fix decode for VDOT (indexed)
  target/arm: Remove unused fpst from VDOT_scalar
  target/arm: Split out do_neon_ddda_fpst
  target/arm: Implement aarch64 SUDOT, USDOT
  target/arm: Implement SVE2 fp multiply-add long
  target/arm: Move endian adjustment macros to vec_internal.h
  target/arm: Implement SVE2 bitwise shift immediate
  target/arm: Implement 128-bit ZIP, UZP, TRN
  target/arm: Implement SVE2 LD1RO
  target/arm: Tidy do_ldrq
  target/arm: Share table of sve load functions
  target/arm: Implement SVE2 FLOGB
  target/arm: Implement SVE2 FCVTXNT, FCVTX
  target/arm: Implement SVE2 FCVTLT
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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