[Qemu-commits] [qemu/qemu] abbf4c: target/riscv: Remove privilege v1.9 s

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[Qemu-commits] [qemu/qemu] abbf4c: target/riscv: Remove privilege v1.9 s

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] abbf4c: target/riscv: Remove privilege v1.9 specific CSR r...
Date:	Tue, 11 May 2021 00:43:53 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: abbf4c60668e88c6d55fd2829ce03acf8244857b
      
https://github.com/qemu/qemu/commit/abbf4c60668e88c6d55fd2829ce03acf8244857b
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/machine.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove privilege v1.9 specific CSR related code

Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
 - Rebase on latest patches
 - Bump the vmstate_riscv_cpu version_id and minimum_version_id
 ]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 852430c321c4c4ce7a4d169af0905681bf1684c4
      
https://github.com/qemu/qemu/commit/852430c321c4c4ce7a4d169af0905681bf1684c4
  Author: Axel Heider <axelheider@gmx.de>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M docs/system/generic-loader.rst

  Log Message:
  -----------
  docs/system/generic-loader.rst: Fix style

Fix style to have a proper description of the parameter 'force-raw'.

Signed-off-by: Axel Heider <axelheider@gmx.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a7e50a64-1c7c-2d41-96d3-d8a417a659ac@gmx.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a2938b0b922ea63a25244eaadbdf31467dfea7df
      
https://github.com/qemu/qemu/commit/a2938b0b922ea63a25244eaadbdf31467dfea7df
  Author: Dylan Jhong <dylan@andestech.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Align the data type of reset vector address

Use target_ulong to instead of uint64_t on reset vector address
to adapt on both 32/64 machine.

Signed-off-by: Dylan Jhong <dylan@andestech.com>
Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210329034801.22667-1-dylan@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d14b31b227755a9c6fa23d5ff6518ef5d7b345d3
      
https://github.com/qemu/qemu/commit/d14b31b227755a9c6fa23d5ff6518ef5d7b345d3
  Author: Bin Meng <bmeng.cn@gmail.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M hw/riscv/sifive_e.c

  Log Message:
  -----------
  hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

This was accidentally dropped before. Add it back.

Fixes: 732612856a8 ("hw/riscv: Drop 'struct MemmapEntry'")
Reported-by: Emmanuel Blot <eblot.ml@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210331103612.654261-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7d0d5c36fdda044f64a89bad6668cb53e595fd7c
      
https://github.com/qemu/qemu/commit/7d0d5c36fdda044f64a89bad6668cb53e595fd7c
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add Shakti C class CPU

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-2-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4071a367329687376260f16659824244620af835
      
https://github.com/qemu/qemu/commit/4071a367329687376260f16659824244620af835
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M MAINTAINERS
    M default-configs/devices/riscv64-softmmu.mak
    M hw/riscv/Kconfig
    M hw/riscv/meson.build
    A hw/riscv/shakti_c.c
    A include/hw/riscv/shakti_c.h

  Log Message:
  -----------
  riscv: Add initial support for Shakti C machine

Add support for emulating Shakti reference platform based on C-class
running on arty-100T board.

https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-3-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4645e71c958aae56fc756cff254c72595ce8d52f
      
https://github.com/qemu/qemu/commit/4645e71c958aae56fc756cff254c72595ce8d52f
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M MAINTAINERS
    M hw/char/meson.build
    A hw/char/shakti_uart.c
    M hw/char/trace-events
    A include/hw/char/shakti_uart.h

  Log Message:
  -----------
  hw/char: Add Shakti UART emulation

This is the initial implementation of Shakti UART.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-4-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 775a1f479ae968d4ce15fac3fa3edc81d059d0ad
      
https://github.com/qemu/qemu/commit/775a1f479ae968d4ce15fac3fa3edc81d059d0ad
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M hw/riscv/shakti_c.c
    M include/hw/riscv/shakti_c.h

  Log Message:
  -----------
  hw/riscv: Connect Shakti UART to Shakti platform

Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 92083f26cf3c98e9cd261c21ec4a2b947d649903
      
https://github.com/qemu/qemu/commit/92083f26cf3c98e9cd261c21ec4a2b947d649903
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Convert the RISC-V exceptions to an enum

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com


  Commit: 9206ca48d35d8ab8d9e3b3683bb91a619f4a3368
      
https://github.com/qemu/qemu/commit/9206ca48d35d8ab8d9e3b3683bb91a619f4a3368
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Use the RISCVException enum for CSR predicates

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
187261fa671c3a77cf5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com


  Commit: bb299606c266400fdf11aedd6adf720842e90967
      
https://github.com/qemu/qemu/commit/bb299606c266400fdf11aedd6adf720842e90967
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Fix 32-bit HS mode access permissions

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com


  Commit: e8eea3649c1b0726965816a130fa2bf7ab216562
      
https://github.com/qemu/qemu/commit/e8eea3649c1b0726965816a130fa2bf7ab216562
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Use the RISCVException enum for CSR operations

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
8566c4c271723f27f3ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com


  Commit: f0d5a1acdc60a3ce35eb95c4d74b13318e36eb22
      
https://github.com/qemu/qemu/commit/f0d5a1acdc60a3ce35eb95c4d74b13318e36eb22
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Use RISCVException enum for CSR access

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com


  Commit: 34f7513436a9e852d2711e511ef1fd497ebe8d63
      
https://github.com/qemu/qemu/commit/34f7513436a9e852d2711e511ef1fd497ebe8d63
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update the RISC-V CPU Maintainers

Update the RISC-V maintainers by removing Sagar and Bastian who haven't
been involved recently.

Also add Bin who has been helping with reviews.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 
6564ba829c40ad9aa7d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com


  Commit: 190ba831a29f446f5f33320592a90da652afd59a
      
https://github.com/qemu/qemu/commit/190ba831a29f446f5f33320592a90da652afd59a
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M hw/intc/ibex_plic.c
    M hw/riscv/opentitan.c
    M include/hw/riscv/opentitan.h

  Log Message:
  -----------
  hw/opentitan: Update the interrupt layout

Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com


  Commit: 55dc715f692331e81dc56191a5337704b8e185d8
      
https://github.com/qemu/qemu/commit/55dc715f692331e81dc56191a5337704b8e185d8
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M hw/riscv/Kconfig

  Log Message:
  -----------
  hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine

imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:

qemu-system-riscv64: Virtio VGA not available

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com


  Commit: 198dde64c7d06beae093cc20fc79fdd29b5c9d2e
      
https://github.com/qemu/qemu/commit/198dde64c7d06beae093cc20fc79fdd29b5c9d2e
  Author: Jade Fink <qemu@jade.fyi>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  riscv: don't look at SUM when accessing memory from a debugger context

Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.

Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: fcba74cb96069bc9b9e6e095092aff0740caaeca
      
https://github.com/qemu/qemu/commit/fcba74cb96069bc9b9e6e095092aff0740caaeca
  Author: LIU Zhiwei <zhiwei_liu@c-sky.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Fixup saturate subtract function

The overflow predication ((a - b) ^ a) & (a ^ b) & INT64_MIN is right.
However, when the predication is ture and a is 0, it should return maximum.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210212150256.885-4-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ffb3dae611061f7bc84fc75411f8041b9c890595
      
https://github.com/qemu/qemu/commit/ffb3dae611061f7bc84fc75411f8041b9c890595
  Author: Vijai Kumar K <vijai@behindbytes.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    A docs/system/riscv/shakti-c.rst
    M docs/system/target-riscv.rst

  Log Message:
  -----------
  docs: Add documentation for shakti_c machine

Add documentation for Shakti C reference platform.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210412174248.8668-1-vijai@behindbytes.com
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
[ Changes from Bin Meng:
 - Add missing TOC
 Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2205a1526e7aaaeb153e1a8c6a89586be4a0d61b
      
https://github.com/qemu/qemu/commit/2205a1526e7aaaeb153e1a8c6a89586be4a0d61b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Fix the PMP is locked check when using TOR

The RISC-V spec says:
    if PMP entry i is locked and pmpicfg.A is set to TOR, writes to
    pmpaddri-1 are ignored.

The current QEMU code ignores accesses to pmpaddri-1 and pmpcfgi-1 which
is incorrect.

Update the pmp_is_locked() function to not check the supporting fields
and instead enforce the lock functionality in the pmpaddr write operation.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
2831241458163f445a89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com


  Commit: 86c1ae00964935e79c72e810197c60a2f3e47eb6
      
https://github.com/qemu/qemu/commit/86c1ae00964935e79c72e810197c60a2f3e47eb6
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Define ePMP mseccfg

Use address 0x390 and 0x391 for the ePMP CSRs.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: b995a0e8ae8ecb33aef5f2ce6fa407667c660e9c
      
https://github.com/qemu/qemu/commit/b995a0e8ae8ecb33aef5f2ce6fa407667c660e9c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add the ePMP feature

The spec is avaliable at:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
28c8855c80b0388a08c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com


  Commit: 189b90f43464097863ad406d639f36959257381f
      
https://github.com/qemu/qemu/commit/189b90f43464097863ad406d639f36959257381f
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/trace-events

  Log Message:
  -----------
  target/riscv: Add ePMP CSR access functions

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Fix build errors
 - Fix some style issues
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: 70c1aab2c5de0175c618ca632e3c27418e3290e6
      
https://github.com/qemu/qemu/commit/70c1aab2c5de0175c618ca632e3c27418e3290e6
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Implementation of enhanced PMP (ePMP)

This commit adds support for ePMP v0.9.1.

The ePMP spec can be found in:
https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
fef23b885f9649a4d54e7c98b168bdec5d297bb1.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
 - Rebase on master
 - Update to latest spec
 - Use a switch case to handle ePMP MML permissions
 - Fix a few bugs
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: ba2b90e331741f965a95c9b0f7ecb8fb354ded81
      
https://github.com/qemu/qemu/commit/ba2b90e331741f965a95c9b0f7ecb8fb354ded81
  Author: Hou Weiying <weiying_hou@outlook.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a config option for ePMP

Add a config option to enable experimental support for ePMP. This
is disabled by default and can be enabled with 'x-epmp=true'.

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
a22ccdaf9314078bc735d3b323f966623f8af020.1618812899.git.alistair.francis@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


  Commit: f4c6a588e510abd534d50c37841140e60f225124
      
https://github.com/qemu/qemu/commit/f4c6a588e510abd534d50c37841140e60f225124
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp: Remove outdated comment

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
10387eec21d2f17c499a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com


  Commit: 4be00161d05ad215a750dd83c93158cc0cdeffb6
      
https://github.com/qemu/qemu/commit/4be00161d05ad215a750dd83c93158cc0cdeffb6
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Add ePMP support for the Ibex CPU

The physical Ibex CPU has ePMP support and it's enabled for the
OpenTitan machine so let's enable ePMP support for the Ibex CPU in QEMU.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
d426baabab0c9361ed2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com


  Commit: 8560a511938b316adaa881cd67a2bebf50d403a8
      
https://github.com/qemu/qemu/commit/8560a511938b316adaa881cd67a2bebf50d403a8
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: fix vrgather macro index variable type bug

ETYPE may be type of uint64_t, thus index variable has to be declared as
type of uint64_t, too. Otherwise the value read from vs1 register may be
truncated to type of uint32_t.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419060302.14075-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 90677f8bed9f9b1ff7e2d71c8bfcd8ba84184c33
      
https://github.com/qemu/qemu/commit/90677f8bed9f9b1ff7e2d71c8bfcd8ba84184c33
  Author: Emmanuel Blot <emmanuel.blot@sifive.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: fix exception index on instruction access fault

When no MMU is used and the guest code attempts to fetch an instruction
from an invalid memory location, the exception index defaults to a data
load access fault, rather an instruction access fault.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: FB9EA197-B018-4879-AB0F-922C2047A08B@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9d090edd7fbe0112a14c3b6607eb733b93c9fa4d
      
https://github.com/qemu/qemu/commit/9d090edd7fbe0112a14c3b6607eb733b93c9fa4d
  Author: Alexander Wagner <alexander.wagner@ulal.de>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M hw/riscv/opentitan.c

  Log Message:
  -----------
  hw/riscv: Fix OT IBEX reset vector

The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".

[1] 
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst

Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 7a8caadacb06fb528dd4af3c6c6d9e15f3543308
      
https://github.com/qemu/qemu/commit/7a8caadacb06fb528dd4af3c6c6d9e15f3543308
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M fpu/softfloat-specialize.c.inc

  Log Message:
  -----------
  fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

In IEEE 754-2008 spec:
  Invalid operation exception is signaled when doing:
  fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c)
  unless c is a quiet NaN; if c is a quiet NaN then it is
  implementation defined whether the invalid operation exception
  is signaled.

In RISC-V Unprivileged ISA spec:
  The fused multiply-add instructions must set the invalid
  operation exception flag when the multiplicands are Inf and
  zero, even when the addend is a quiet NaN.

This commit set invalid operation execption flag for RISC-V when
multiplicands of muladd instructions are Inf and zero.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210420013150.21992-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 81c86d2169f533bd22712ed18890e43601d62e7a
      
https://github.com/qemu/qemu/commit/81c86d2169f533bd22712ed18890e43601d62e7a
  Author: Emmanuel Blot <emmanuel.blot@sifive.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: fix a typo with interrupt names

Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 63b414771c3f7aaf66a4c3eb5682ea878b491b0d
      
https://github.com/qemu/qemu/commit/63b414771c3f7aaf66a4c3eb5682ea878b491b0d
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Remove the hardcoded RVXLEN macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com


  Commit: 87f54c8fd9e1dd6724436bd8c0800e5e462801a1
      
https://github.com/qemu/qemu/commit/87f54c8fd9e1dd6724436bd8c0800e5e462801a1
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded SSTATUS_SD macro

This also ensures that the SD bit is not writable.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
9ea842309f0fd7adff172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com


  Commit: 34e3aed01c01dbc34c4d0dc6c124e9e054d5c821
      
https://github.com/qemu/qemu/commit/34e3aed01c01dbc34c4d0dc6c124e9e054d5c821
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded HGATP_MODE macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
665f624bfdc2e3ca64265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com


  Commit: b2495110eac15881239f68121a98034392b8398c
      
https://github.com/qemu/qemu/commit/b2495110eac15881239f68121a98034392b8398c
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded MSTATUS_SD macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com


  Commit: dc509d269d737dbee68d11b0651e04ffdd3359e0
      
https://github.com/qemu/qemu/commit/dc509d269d737dbee68d11b0651e04ffdd3359e0
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/monitor.c

  Log Message:
  -----------
  target/riscv: Remove the hardcoded SATP_MODE macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com


  Commit: c445bcbe841d88fc83bcbf8fa25e48dbaccbc62a
      
https://github.com/qemu/qemu/commit/c445bcbe841d88fc83bcbf8fa25e48dbaccbc62a
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Remove the unused HSTATUS_WPRI macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
e095b57af0d419c8ed822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com


  Commit: 7e7f4c8e8bab708bdd4c0caab54cc87d89dbc86b
      
https://github.com/qemu/qemu/commit/7e7f4c8e8bab708bdd4c0caab54cc87d89dbc86b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Remove an unused CASE_OP_32_64 macro

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 
4853459564af35a6690120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com


  Commit: cf3ea4ef61f416e4f8a7e011feabf06a2541e60b
      
https://github.com/qemu/qemu/commit/cf3ea4ef61f416e4f8a7e011feabf06a2541e60b
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/fpu_helper.c
    M target/riscv/helper.h
    R target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/meson.build
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Consolidate RV32/64 32-bit instructions

This patch removes the insn32-64.decode decode file and consolidates the
instructions into the general RISC-V insn32.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
db709360e2be47d2f9c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com


  Commit: 17d1fd70582d795e49cdfb3b8a4271c4eebb79de
      
https://github.com/qemu/qemu/commit/17d1fd70582d795e49cdfb3b8a4271c4eebb79de
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    R target/riscv/insn16-32.decode
    R target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/meson.build

  Log Message:
  -----------
  target/riscv: Consolidate RV32/64 16-bit instructions

This patch removes the insn16-32.decode and insn16-64.decode decode
files and consolidates the instructions into the general RISC-V
insn16.decode decode tree.

This means that all of the instructions are avaliable in both the 32-bit
and 64-bit builds. This also means that we run a check to ensure we are
running a 64-bit softmmu before we execute the 64-bit only instructions.
This allows us to include the 32-bit instructions in the 64-bit build,
while also ensuring that 32-bit only software can not execute the
instructions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
01e2b0efeae311adc7ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com


  Commit: d9e1a4683bc52ff218dcc133f73017bc4c496346
      
https://github.com/qemu/qemu/commit/d9e1a4683bc52ff218dcc133f73017bc4c496346
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-05-06 (Thu, 06 May 2021)

  Changed paths:
    M target/riscv/insn32.decode

  Log Message:
  -----------
  target/riscv: Fix the RV64H decode comment

BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com


  Commit: 9a408f75dfe499237ef9197d64037210a29fe52f
      
https://github.com/qemu/qemu/commit/9a408f75dfe499237ef9197d64037210a29fe52f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-11 (Tue, 11 May 2021)

  Changed paths:
    M MAINTAINERS
    M default-configs/devices/riscv64-softmmu.mak
    M docs/system/generic-loader.rst
    A docs/system/riscv/shakti-c.rst
    M docs/system/target-riscv.rst
    M fpu/softfloat-specialize.c.inc
    M hw/char/meson.build
    A hw/char/shakti_uart.c
    M hw/char/trace-events
    M hw/intc/ibex_plic.c
    M hw/riscv/Kconfig
    M hw/riscv/meson.build
    M hw/riscv/opentitan.c
    A hw/riscv/shakti_c.c
    M hw/riscv/sifive_e.c
    A include/hw/char/shakti_uart.h
    M include/hw/riscv/opentitan.h
    A include/hw/riscv/shakti_c.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/gdbstub.c
    M target/riscv/helper.h
    R target/riscv/insn16-32.decode
    R target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    R target/riscv/insn32-64.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_rva.c.inc
    M target/riscv/insn_trans/trans_rvd.c.inc
    M target/riscv/insn_trans/trans_rvf.c.inc
    M target/riscv/insn_trans/trans_rvh.c.inc
    M target/riscv/insn_trans/trans_rvi.c.inc
    M target/riscv/insn_trans/trans_rvm.c.inc
    M target/riscv/insn_trans/trans_rvv.c.inc
    M target/riscv/machine.c
    M target/riscv/meson.build
    M target/riscv/monitor.c
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h
    M target/riscv/trace-events
    M target/riscv/translate.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210506' into staging

A large collection of RISC-V fixes, improvements and features

 - Clenaup some left over v1.9 code
 - Documentation improvements
 - Support for the shakti_c machine
 - Internal cleanup of the CSR accesses
 - Updates to the OpenTitan platform
 - Support for the virtio-vga
 - Fix for the saturate subtract in vector extensions
 - Experimental support for the ePMP spec
 - A range of other internal code cleanups and bug fixes

# gpg: Signature made Thu 06 May 2021 00:03:50 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210506: (42 commits)
  target/riscv: Fix the RV64H decode comment
  target/riscv: Consolidate RV32/64 16-bit instructions
  target/riscv: Consolidate RV32/64 32-bit instructions
  target/riscv: Remove an unused CASE_OP_32_64 macro
  target/riscv: Remove the unused HSTATUS_WPRI macro
  target/riscv: Remove the hardcoded SATP_MODE macro
  target/riscv: Remove the hardcoded MSTATUS_SD macro
  target/riscv: Remove the hardcoded HGATP_MODE macro
  target/riscv: Remove the hardcoded SSTATUS_SD macro
  target/riscv: Remove the hardcoded RVXLEN macro
  target/riscv: fix a typo with interrupt names
  fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
  hw/riscv: Fix OT IBEX reset vector
  target/riscv: fix exception index on instruction access fault
  target/riscv: fix vrgather macro index variable type bug
  target/riscv: Add ePMP support for the Ibex CPU
  target/riscv/pmp: Remove outdated comment
  target/riscv: Add a config option for ePMP
  target/riscv: Implementation of enhanced PMP (ePMP)
  target/riscv: Add ePMP CSR access functions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


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