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[Qemu-commits] [qemu/qemu] 0df2d9: aspeed/smc: Use the RAM memory region

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 0df2d9: aspeed/smc: Use the RAM memory region for DMAs
Date: Tue, 04 May 2021 09:11:42 -0700 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 0df2d9a673543c4ab06646d9f6bd21153c632a4c
      
https://github.com/qemu/qemu/commit/0df2d9a673543c4ab06646d9f6bd21153c632a4c
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: Use the RAM memory region for DMAs

Instead of passing the memory address space region, simply use the RAM
memory region instead. This simplifies RAM accesses.

This patch breaks migration compatibility.

Fixes: c4e1f0b48322 ("aspeed/smc: Add support for DMAs")
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210407171637.777743-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d177892d4a48668a422772e19bed9b6baa384a08
      
https://github.com/qemu/qemu/commit/d177892d4a48668a422772e19bed9b6baa384a08
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Remove unused "sdram-base" property

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210407171637.777743-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 7492515909f043c4d82909ecdebb8643ed944c68
      
https://github.com/qemu/qemu/commit/7492515909f043c4d82909ecdebb8643ed944c68
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: Fix DMA address mask

The RAM memory region is now used for DMAs accesses instead of the
memory address space region. Mask off the top bits of the DMA address
to reflect this change.

Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210407171637.777743-4-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 3f7a53b22469ed4b80649ef92b94378c60dda5d0
      
https://github.com/qemu/qemu/commit/3f7a53b22469ed4b80649ef92b94378c60dda5d0
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/i2c/aspeed_i2c.c

  Log Message:
  -----------
  aspeed/i2c: Rename DMA address space

It improves 'info mtree' output.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210407171637.777743-5-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: e9c568dbc22551f069dbc30ca3b61e168f494d47
      
https://github.com/qemu/qemu/commit/e9c568dbc22551f069dbc30ca3b61e168f494d47
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias

The flash mmio region is exposed as an AddressSpace.
AddressSpaces must not be sysbus-mapped, therefore map
the region using an alias.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[ clg : Fix DMA_FLASH_ADDR() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210312182851.1922972-3-f4bug@amsat.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210407171637.777743-6-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: c5475b3f9aa28c1c1422c7de0bab40c5dff77341
      
https://github.com/qemu/qemu/commit/c5475b3f9aa28c1c1422c7de0bab40c5dff77341
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M docs/system/arm/aspeed.rst
    A hw/misc/aspeed_hace.c
    M hw/misc/meson.build
    A include/hw/misc/aspeed_hace.h

  Log Message:
  -----------
  hw: Model ASPEED's Hash and Crypto Engine

The HACE (Hash and Crypto Engine) is a device that offloads MD5, SHA1,
SHA2, RSA and other cryptographic algorithms.

This initial model implements a subset of the device's functionality;
currently only MD5/SHA hashing, and on the ast2600's scatter gather
engine.

Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
[ clg: - fixes for 32-bit and OSX builds ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210409000253.1475587-2-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a3888d757acdd92c4c49fb9cad5f5733d8280a86
      
https://github.com/qemu/qemu/commit/a3888d757acdd92c4c49fb9cad5f5733d8280a86
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M docs/system/arm/aspeed.rst
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: Integrate HACE

Add the hash and crypto engine model to the Aspeed socs.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210409000253.1475587-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 666099520aabd27f1995efd54a34ae8522eb2602
      
https://github.com/qemu/qemu/commit/666099520aabd27f1995efd54a34ae8522eb2602
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M MAINTAINERS
    A tests/qtest/aspeed_hace-test.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  tests/qtest: Add test for Aspeed HACE

This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
the currently implemented behavior of the hash functionality.

The tests are similar, but are cut/pasted instead of broken out into a
common function so the assert machinery produces useful output when a
test fails.

Co-developed-by: Cédric Le Goater <clg@kaod.org>
Co-developed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210409000253.1475587-4-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: a3a178c663eef3bc1a105e8d710f40ba44192ffd
      
https://github.com/qemu/qemu/commit/a3a178c663eef3bc1a105e8d710f40ba44192ffd
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/acceptance: Test ast2400 and ast2500 machines

Test MTD images from the OpenBMC project on AST2400 and AST2500 SoCs
from ASPEED, by booting Palmetto and Romulus BMC machines.

The images are fetched from OpenBMC's release directory on github.

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Wainer dos Santos Moschetta <wainersm@redhat.com>
Co-developed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cleber Rosa <crosa@redhat.com>
Tested-by: Cleber Rosa <crosa@redhat.com>
[ clg : - removed comment
        - removed ending self.vm.shutdown() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210304123951.163411-2-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210407171637.777743-12-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 224f010ba81ff25c972c33c1e13d79c85ed40e35
      
https://github.com/qemu/qemu/commit/224f010ba81ff25c972c33c1e13d79c85ed40e35
  Author: Joel Stanley <joel@jms.id.au>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/acceptance: Test ast2600 machine

This tests a Debian multi-soc arm32 Linux kernel on the AST2600 based
Tacoma BMC machine.

There is no root file system so the test terminates when boot reaches
the stage where it attempts and fails to mount something.

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Wainer dos Santos Moschetta <wainersm@redhat.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
[ clg : - removed comment
        - removed ending self.vm.shutdown() ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210304123951.163411-3-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-Id: <20210407171637.777743-13-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 8efbee28f4729f16cae5cbf93a029bfa55198fc2
      
https://github.com/qemu/qemu/commit/8efbee28f4729f16cae5cbf93a029bfa55198fc2
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/misc/aspeed_xdma.c
    M include/hw/misc/aspeed_xdma.h

  Log Message:
  -----------
  hw/misc/aspeed_xdma: Add AST2600 support

When we introduced support for the AST2600 SoC, the XDMA controller
was forgotten. It went unnoticed because it's not used under emulation.
But the register layout being different, the reset procedure is bogus
and this breaks kexec.

Add a AspeedXDMAClass to take into account the register differences.

Cc: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Message-Id: <20210407171637.777743-14-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1c5ee69da5e65cc04055b304a784d82fd04de764
      
https://github.com/qemu/qemu/commit/1c5ee69da5e65cc04055b304a784d82fd04de764
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Add a 'features' attribute to the object class

It will simplify extensions of the SMC model.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210407171637.777743-15-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 1769a70e54181bb3e54783f16350892e847a3a89
      
https://github.com/qemu/qemu/commit/1769a70e54181bb3e54783f16350892e847a3a89
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: Add extra controls to request DMA

The AST2600 SPI controllers have a set of bits to request/grant DMA
access. Add a new SMC feature for these controllers and use it to
check access to the DMA registers.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210407171637.777743-16-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 5fde7f10c0185929db15401ba72abd44b9abc466
      
https://github.com/qemu/qemu/commit/5fde7f10c0185929db15401ba72abd44b9abc466
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    A tests/qtest/aspeed_smc-test.c
    R tests/qtest/m25p80-test.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  tests/qtest: Rename m25p80 test in aspeed_smc test

The m25p80 test depends on the Aspeed SMC controller to test our
SPI-NOR flash support. Reflect this dependency by changing the name.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210407171637.777743-17-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 63a9c7e0a0ebb141c211112b164a0d31740d5031
      
https://github.com/qemu/qemu/commit/63a9c7e0a0ebb141c211112b164a0d31740d5031
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M docs/system/deprecated.rst
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Deprecate the swift-bmc machine

The SWIFT machine never came out of the lab and we already have enough
AST2500 based OpenPower machines.

Cc: Adriana Kobylak <anoo@us.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 58e52bdb87675093c76f8febdca52e3398f11391
      
https://github.com/qemu/qemu/commit/58e52bdb87675093c76f8febdca52e3398f11391
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add support for the rainier-bmc board

The Rainier BMC board is a board for the middle range POWER10 IBM systems.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210407171637.777743-19-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: d24aa3241a6248e183532381e479f6c49c33fc28
      
https://github.com/qemu/qemu/commit/d24aa3241a6248e183532381e479f6c49c33fc28
  Author: Cédric Le Goater <clg@kaod.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block: m25p80: Add support for mt25ql02g and mt25qu02g

The Micron mt25ql02g is a 3V 2Gb serial NOR flash memory supporting
dual I/O and quad I/O, 4KB, 32KB, 64KB sector erase. It also supports
4B opcodes. The mt25qu02g operates at 1.8V.

  
https://4donline.ihs.com/images/VipMasterIC/IC/MICT/MICT-S-A0008500026/MICT-S-A0008511423-1.pdf?hkey=52A5661711E402568146F3353EA87419

Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Francisco Iglesias <francisco.iglesias@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 9cccb912cfa865f0bae6b156fa94e2f216dd8835
      
https://github.com/qemu/qemu/commit/9cccb912cfa865f0bae6b156fa94e2f216dd8835
  Author: Patrick Venture <venture@google.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add support for the quanta-q7l1-bmc board

The Quanta-Q71l BMC board is a board supported by OpenBMC.

Tested: Booted quanta-q71l firmware.
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210416162426.3217033-1-venture@google.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>


  Commit: 87c6cef605a077b20a245d54167127ccf7996e23
      
https://github.com/qemu/qemu/commit/87c6cef605a077b20a245d54167127ccf7996e23
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-04 (Tue, 04 May 2021)

  Changed paths:
    M MAINTAINERS
    M docs/system/arm/aspeed.rst
    M docs/system/deprecated.rst
    M hw/arm/aspeed.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_soc.c
    M hw/block/m25p80.c
    M hw/i2c/aspeed_i2c.c
    A hw/misc/aspeed_hace.c
    M hw/misc/aspeed_xdma.c
    M hw/misc/meson.build
    M hw/ssi/aspeed_smc.c
    M include/hw/arm/aspeed_soc.h
    A include/hw/misc/aspeed_hace.h
    M include/hw/misc/aspeed_xdma.h
    M include/hw/ssi/aspeed_smc.h
    M tests/acceptance/boot_linux_console.py
    A tests/qtest/aspeed_hace-test.c
    A tests/qtest/aspeed_smc-test.c
    R tests/qtest/m25p80-test.c
    M tests/qtest/meson.build

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210503' 
into staging

Aspeed patches :

* Fixes for the DMA space
* New model for ASPEED's Hash and Crypto Engine (Joel and Klaus)
* Acceptance tests (Joel)
* A fix for the XDMA  model
* Some extra features for the SMC controller.
* Two new boards : rainier-bmc and quanta-q7l1-bmc (Patrick)

# gpg: Signature made Mon 03 May 2021 06:23:36 BST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* remotes/legoater/tags/pull-aspeed-20210503:
  aspeed: Add support for the quanta-q7l1-bmc board
  hw/block: m25p80: Add support for mt25ql02g and mt25qu02g
  aspeed: Add support for the rainier-bmc board
  aspeed: Deprecate the swift-bmc machine
  tests/qtest: Rename m25p80 test in aspeed_smc test
  aspeed/smc: Add extra controls to request DMA
  aspeed/smc: Add a 'features' attribute to the object class
  hw/misc/aspeed_xdma: Add AST2600 support
  tests/acceptance: Test ast2600 machine
  tests/acceptance: Test ast2400 and ast2500 machines
  tests/qtest: Add test for Aspeed HACE
  aspeed: Integrate HACE
  hw: Model ASPEED's Hash and Crypto Engine
  hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias
  aspeed/i2c: Rename DMA address space
  aspeed/i2c: Fix DMA address mask
  aspeed/smc: Remove unused "sdram-base" property
  aspeed/smc: Use the RAM memory region for DMAs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/3e13d8e34b53...87c6cef605a0
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