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[Qemu-commits] [qemu/qemu] bcad13: hw/isa/piix4: Use qdev_get_gpio_in_na
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] bcad13: hw/isa/piix4: Use qdev_get_gpio_in_named() to get ... |
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Date: |
Tue, 04 May 2021 02:10:56 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: bcad139192b0101e3d7ef593144c314bed4cb8c2
https://github.com/qemu/qemu/commit/bcad139192b0101e3d7ef593144c314bed4cb8c2
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M hw/isa/piix4.c
Log Message:
-----------
hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller")
the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias.
Use this alias to get IRQ for the power management PCI function.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210324182902.692419-1-f4bug@amsat.org>
Commit: 84c2fdc397b6609d1cef76aec2f1367139d1372e
https://github.com/qemu/qemu/commit/84c2fdc397b6609d1cef76aec2f1367139d1372e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
The CACHEE opcode "requires CP0 privilege".
The pseudocode checks in the ISA manual is:
if is_eva and not C0.Config5.EVA:
raise exception('RI')
if not IsCoprocessor0Enabled():
raise coprocessor_exception(0)
Add the missing checks.
Inspired-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
Commit: 298d43c96b0f7dc7ea6550ea73b128b3d4ed67f9
https://github.com/qemu/qemu/commit/298d43c96b0f7dc7ea6550ea73b128b3d4ed67f9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes
Per the nanoMIPS32 Instruction Set Technical Reference Manual,
Revision 01.01, Chapter 3. "Instruction Definitions":
The Read/Write Previous GPR opcodes "require CP0 privilege".
Add the missing CP0 checks.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
Commit: bc2eb5ea1b595fb686b7bef81bbf20e6a9635476
https://github.com/qemu/qemu/commit/bc2eb5ea1b595fb686b7bef81bbf20e6a9635476
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode
When running with '-d unimp' all MTHC0 opcode executed
are logged as unimplemented... Add the proper 'return'
statement missed from commit 5204ea79ea7.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210422081055.2349216-1-f4bug@amsat.org>
Commit: df44e81703968d22ce59e1160f970c5e70db2cfb
https://github.com/qemu/qemu/commit/df44e81703968d22ce59e1160f970c5e70db2cfb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/machine.c
Log Message:
-----------
target/mips: Migrate missing CPU fields
Add various missing fields to the CPU migration vmstate:
- CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03)
- CMGCRBase (c870e3f52ca 2016-03-15)
- CP0_ErrCtl (0d74a222c27 2016-03-25)
- MXU GPR[] & CR (eb5559f67dc 2018-10-18)
- R5900 128-bit upper half (a168a796e1c 2019-01-17)
This is a migration break.
Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading")
Fixes: c870e3f52ca ("target-mips: add CMGCRBase register")
Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the
CPU")
Fixes: eb5559f67dc ("target/mips: Introduce MXU registers")
Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210423220044.3004195-1-f4bug@amsat.org>
Commit: 905bdf72a6373bcb46fbdc8b9d7d9f83d134a266
https://github.com/qemu/qemu/commit/905bdf72a6373bcb46fbdc8b9d7d9f83d134a266
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Make check_cp0_enabled() return a boolean
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420193453.1913810-4-f4bug@amsat.org>
Commit: 58ecf15d76e6e232d908bf115236108a639daa71
https://github.com/qemu/qemu/commit/58ecf15d76e6e232d908bf115236108a639daa71
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/meson.build
Log Message:
-----------
target/mips: Simplify meson TCG rules
We already have the mips_tcg_ss source set for TCG-specific files,
use it for mxu_translate.c and tx79_translate.c to simplify a bit.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-2-f4bug@amsat.org>
Commit: 830a72301c35548907ff05399a99f34dab9c867d
https://github.com/qemu/qemu/commit/830a72301c35548907ff05399a99f34dab9c867d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
A target/mips/fpu.c
M target/mips/fpu_helper.c
M target/mips/meson.build
Log Message:
-----------
target/mips: Move IEEE rounding mode array to new source file
restore_msa_fp_status() is declared inlined in fpu_helper.h,
and uses the ieee_rm[] array. Therefore any code calling
restore_msa_fp_status() must have access to this ieee_rm[] array.
kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c,
calls restore_msa_fp_status.
Except this tiny array, the rest of fpu_helper.c is only useful
for the TCG accelerator.
To be able to restrict fpu_helper.c to TCG, we need to move the
ieee_rm[] array to a new source file.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-3-f4bug@amsat.org>
Commit: fed50ffd5ce4b03f94036232c613b2ca8fba06eb
https://github.com/qemu/qemu/commit/fed50ffd5ce4b03f94036232c613b2ca8fba06eb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/meson.build
A target/mips/msa.c
M target/mips/msa_helper.c
Log Message:
-----------
target/mips: Move msa_reset() to new source file
mips_cpu_reset() is used by all accelerators, and calls
msa_reset(), which is defined in msa_helper.c.
Beside msa_reset(), the rest of msa_helper.c is only useful
to the TCG accelerator. To be able to restrict this helper
file to TCG, we need to move msa_reset() out of it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-4-f4bug@amsat.org>
Commit: adbf1be325482af13e374573fc875fbe15600348
https://github.com/qemu/qemu/commit/adbf1be325482af13e374573fc875fbe15600348
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/fpu.c
M target/mips/internal.h
M target/mips/translate.c
Log Message:
-----------
target/mips: Make CPU/FPU regnames[] arrays global
The CPU/FPU regnames[] arrays is used in mips_tcg_init() and
mips_cpu_dump_state(), which while being in translate.c is
not specific to TCG.
To be able to move mips_cpu_dump_state() to cpu.c, which is
compiled for all accelerator, we need to make the regnames[]
arrays global to target/mips/ by declaring them in "internal.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-5-f4bug@amsat.org>
Commit: 830b87ea25b3710c3fce04dee782bcf1c89ba27f
https://github.com/qemu/qemu/commit/830b87ea25b3710c3fce04dee782bcf1c89ba27f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/fpu.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Optimize CPU/FPU regnames[] arrays
Since all entries are no more than 4 bytes (including nul
terminator), can save space and pie runtime relocations by
declaring regnames[] as array of 4 const char.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-6-f4bug@amsat.org>
Commit: 4f14ce4bf4ec01a840a8de4007a95a77998c5736
https://github.com/qemu/qemu/commit/4f14ce4bf4ec01a840a8de4007a95a77998c5736
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/translate.c
Log Message:
-----------
target/mips: Restrict mips_cpu_dump_state() to cpu.c
As mips_cpu_dump_state() is only used once to initialize the
CPUClass::dump_state handler, we can move it to cpu.c to keep
it symbol local.
Beside, this handler is used by all accelerators, while the
translate.c file targets TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-7-f4bug@amsat.org>
Commit: 4d169b9cce25bcef691d0c50a6c7d0d6350003ae
https://github.com/qemu/qemu/commit/4d169b9cce25bcef691d0c50a6c7d0d6350003ae
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
Log Message:
-----------
target/mips: Turn printfpr() macro into a proper function
Turn printfpr() macro into a proper function: fpu_dump_fpr().
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-8-f4bug@amsat.org>
Commit: 533fc64feb96b6aafdb0d604cd1cd97877451878
https://github.com/qemu/qemu/commit/533fc64feb96b6aafdb0d604cd1cd97877451878
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Declare mips_env_set_pc() inlined in "internal.h"
Rename set_pc() as mips_env_set_pc(), declare it inlined
and use it in cpu.c and op_helper.c.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428170410.479308-9-f4bug@amsat.org>
Commit: 0debf1400c000154948e8a6fcb89c3149d4e0880
https://github.com/qemu/qemu/commit/0debf1400c000154948e8a6fcb89c3149d4e0880
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
M target/mips/op_helper.c
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Merge do_translate_address into cpu_mips_translate_address
Currently cpu_mips_translate_address() calls raise_mmu_exception(),
and do_translate_address() calls cpu_loop_exit_restore().
This API split is dangerous, we could call cpu_mips_translate_address
without returning to the main loop.
As there is only one caller, it is trivial (and safer) to merge
do_translate_address() back to cpu_mips_translate_address().
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-10-f4bug@amsat.org>
Commit: 6f4aec6a6d5524fb89e6dbd71de9920e7ec416e7
https://github.com/qemu/qemu/commit/6f4aec6a6d5524fb89e6dbd71de9920e7ec416e7
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
A target/mips/ldst_helper.c
M target/mips/meson.build
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Extract load/store helpers to ldst_helper.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-11-f4bug@amsat.org>
Commit: 46369b50ee3f72782507a7f88158fa62753be469
https://github.com/qemu/qemu/commit/46369b50ee3f72782507a7f88158fa62753be469
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M meson.build
Log Message:
-----------
meson: Introduce meson_user_arch source set for arch-specific user-mode
Similarly to the 'target_softmmu_arch' source set which allows
to restrict target-specific sources to system emulation, add
the equivalent 'target_user_arch' set for user emulation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-12-f4bug@amsat.org>
Commit: 6fe25ce58798815237307cf1924ef5b4d13cac99
https://github.com/qemu/qemu/commit/6fe25ce58798815237307cf1924ef5b4d13cac99
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
A target/mips/tcg/tcg-internal.h
Log Message:
-----------
target/mips: Introduce tcg-internal.h for TCG specific declarations
We will gradually move TCG-specific declarations to a new local
header: "tcg-internal.h". To keep review simple, first add this
header with 2 TCG prototypes, which we are going to move in the
next 2 commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-13-f4bug@amsat.org>
Commit: 0a31c16c9ce2639c8706b9f863724ba42a46f121
https://github.com/qemu/qemu/commit/0a31c16c9ce2639c8706b9f863724ba42a46f121
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/meson.build
A target/mips/tcg/meson.build
A target/mips/tcg/user/meson.build
A target/mips/tcg/user/tlb_helper.c
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Add simple user-mode mips_cpu_do_interrupt()
The #ifdef'ry hides that the user-mode implementation of
mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE.
Add this simple implementation to tcg/user/tlb_helper.c, and
the corresponding Meson machinery to build this file when user
emulation is configured.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-14-f4bug@amsat.org>
Commit: 8074365fc7ab51c582565f4d77299889e511af5b
https://github.com/qemu/qemu/commit/8074365fc7ab51c582565f4d77299889e511af5b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/tcg/user/tlb_helper.c
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Add simple user-mode mips_cpu_tlb_fill()
tlb_helper.c's #ifdef'ry hides a quite simple user-mode
implementation of mips_cpu_tlb_fill().
Copy the user-mode implementation (without #ifdef'ry) to
tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry.
This will allow us to restrict tlb_helper.c to sysemu.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-15-f4bug@amsat.org>
Commit: 44e3b05005c6696cd526a4575293513db453f4b5
https://github.com/qemu/qemu/commit/44e3b05005c6696cd526a4575293513db453f4b5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
Log Message:
-----------
target/mips: Move cpu_signal_handler definition around
We have 2 blocks guarded with #ifdef for sysemu, which
are simply separated by the cpu_signal_handler definition.
To simplify the following commits which involve various
changes in internal.h, first join the sysemu-guarded blocks.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-16-f4bug@amsat.org>
Commit: 85d8da3fea0c4ff38bbe759febfc2d2299b33ccd
https://github.com/qemu/qemu/commit/85d8da3fea0c4ff38bbe759febfc2d2299b33ccd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M MAINTAINERS
R target/mips/addr.c
R target/mips/cp0_timer.c
R target/mips/machine.c
M target/mips/meson.build
A target/mips/sysemu/addr.c
A target/mips/sysemu/cp0_timer.c
A target/mips/sysemu/machine.c
A target/mips/sysemu/meson.build
Log Message:
-----------
target/mips: Move sysemu specific files under sysemu/ subfolder
Move sysemu-specific files under the new sysemu/ subfolder
and adapt the Meson machinery.
Update the KVM MIPS entry in MAINTAINERS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-17-f4bug@amsat.org>
Commit: 137f4d87c6dd3c727fd5b5e777e89f610b51ae8d
https://github.com/qemu/qemu/commit/137f4d87c6dd3c727fd5b5e777e89f610b51ae8d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
M target/mips/sysemu/meson.build
A target/mips/sysemu/physaddr.c
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Move physical addressing code to sysemu/physaddr.c
Declare get_physical_address() with local scope and move it along
with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-18-f4bug@amsat.org>
Commit: 8b28cde403468c2f8feff4d97a9c2b98ea3d8adb
https://github.com/qemu/qemu/commit/8b28cde403468c2f8feff4d97a9c2b98ea3d8adb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tcg/tcg-internal.h
Log Message:
-----------
target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-19-f4bug@amsat.org>
Commit: ad520a978447bca03374b71e90d948826e669603
https://github.com/qemu/qemu/commit/ad520a978447bca03374b71e90d948826e669603
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
R target/mips/cp0_helper.c
M target/mips/helper.h
M target/mips/meson.build
R target/mips/mips-semi.c
M target/mips/tcg/meson.build
A target/mips/tcg/sysemu/cp0_helper.c
A target/mips/tcg/sysemu/meson.build
A target/mips/tcg/sysemu/mips-semi.c
A target/mips/tcg/sysemu_helper.h.inc
Log Message:
-----------
target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.
Move the opcode definitions to tcg/sysemu_helper.h.inc.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-20-f4bug@amsat.org>
Commit: c284201702386b159277422318e51697647a2047
https://github.com/qemu/qemu/commit/c284201702386b159277422318e51697647a2047
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
M target/mips/tcg/tcg-internal.h
Log Message:
-----------
target/mips: Restrict mmu_init() to TCG
mmu_init() is only required by TCG accelerator.
Restrict its declaration and call to TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-21-f4bug@amsat.org>
Commit: 920b48cc14fe44a466f7387263993e86b4e21bce
https://github.com/qemu/qemu/commit/920b48cc14fe44a466f7387263993e86b4e21bce
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
M target/mips/meson.build
M target/mips/tcg/sysemu/meson.build
A target/mips/tcg/sysemu/tlb_helper.c
M target/mips/tcg/tcg-internal.h
R target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Move tlb_helper.c to tcg/sysemu/
Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()
Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-22-f4bug@amsat.org>
Commit: f3185ec2f35e43c06384f5ac5edc4edfbfd11623
https://github.com/qemu/qemu/commit/f3185ec2f35e43c06384f5ac5edc4edfbfd11623
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tcg/sysemu/tlb_helper.c
Log Message:
-----------
target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
The 3 map_address() handlers are local to tlb_helper.c,
no need to have their prototype declared publically.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-23-f4bug@amsat.org>
Commit: d60146a9389db771fa4061d9376ba3e208ff2cdb
https://github.com/qemu/qemu/commit/d60146a9389db771fa4061d9376ba3e208ff2cdb
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/helper.h
M target/mips/op_helper.c
M target/mips/tcg/sysemu/meson.build
A target/mips/tcg/sysemu/special_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/tcg/tcg-internal.h
Log Message:
-----------
target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
Move the Special opcodes helpers to tcg/sysemu/special_helper.c.
Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-24-f4bug@amsat.org>
Commit: ecdbcb0a9450e9109ae3dd6cfa10c71fda753bda
https://github.com/qemu/qemu/commit/ecdbcb0a9450e9109ae3dd6cfa10c71fda753bda
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/helper.h
M target/mips/op_helper.c
M target/mips/tcg/sysemu/special_helper.c
M target/mips/tcg/sysemu_helper.h.inc
M target/mips/translate.c
Log Message:
-----------
target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
Move helper_cache() to tcg/sysemu/special_helper.c.
The CACHE opcode is privileged and is not accessible in user
emulation. However we get a link failure when restricting the
symbol to sysemu. For now, add a stub helper to satisfy linking,
which abort if ever called.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-25-f4bug@amsat.org>
Commit: 6575529b654ffeaebf1b00c53e33c834d68b7c33
https://github.com/qemu/qemu/commit/6575529b654ffeaebf1b00c53e33c834d68b7c33
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/helper.h
M target/mips/internal.h
M target/mips/op_helper.c
M target/mips/tcg/sysemu/tlb_helper.c
M target/mips/tcg/sysemu_helper.h.inc
Log Message:
-----------
target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
Move TLB management helpers to tcg/sysemu/tlb_helper.c.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-26-f4bug@amsat.org>
Commit: 8aa52bdc87aaf54c497902a91aaf4096cb780660
https://github.com/qemu/qemu/commit/8aa52bdc87aaf54c497902a91aaf4096cb780660
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
A target/mips/exception.c
M target/mips/internal.h
M target/mips/meson.build
M target/mips/op_helper.c
M target/mips/tcg/tcg-internal.h
Log Message:
-----------
target/mips: Move exception management code to exception.c
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-27-f4bug@amsat.org>
Commit: 5679479b9a1b0dd4772904c3af0d02bb3c9e635f
https://github.com/qemu/qemu/commit/5679479b9a1b0dd4772904c3af0d02bb3c9e635f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
A target/mips/sysemu/cp0.c
M target/mips/sysemu/meson.build
Log Message:
-----------
target/mips: Move CP0 helpers to sysemu/cp0.c
Opcodes accessing Coprocessor 0 are privileged.
Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-28-f4bug@amsat.org>
Commit: a2b0a27d33e9b1079698cee04ff029a0555b5ea5
https://github.com/qemu/qemu/commit/a2b0a27d33e9b1079698cee04ff029a0555b5ea5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
R target/mips/dsp_helper.c
R target/mips/exception.c
R target/mips/fpu_helper.c
M target/mips/helper.h
M target/mips/internal.h
R target/mips/ldst_helper.c
R target/mips/lmmi_helper.c
M target/mips/meson.build
R target/mips/mips32r6.decode
R target/mips/mips64r6.decode
R target/mips/msa32.decode
R target/mips/msa64.decode
R target/mips/msa_helper.c
R target/mips/msa_helper.h.inc
R target/mips/msa_translate.c
R target/mips/mxu_translate.c
R target/mips/op_helper.c
R target/mips/rel6_translate.c
A target/mips/tcg/dsp_helper.c
A target/mips/tcg/exception.c
A target/mips/tcg/fpu_helper.c
A target/mips/tcg/ldst_helper.c
A target/mips/tcg/lmmi_helper.c
M target/mips/tcg/meson.build
A target/mips/tcg/mips32r6.decode
A target/mips/tcg/mips64r6.decode
A target/mips/tcg/msa32.decode
A target/mips/tcg/msa64.decode
A target/mips/tcg/msa_helper.c
A target/mips/tcg/msa_helper.h.inc
A target/mips/tcg/msa_translate.c
A target/mips/tcg/mxu_translate.c
A target/mips/tcg/op_helper.c
A target/mips/tcg/rel6_translate.c
M target/mips/tcg/tcg-internal.h
A target/mips/tcg/translate.c
A target/mips/tcg/translate_addr_const.c
A target/mips/tcg/tx79.decode
A target/mips/tcg/tx79_translate.c
A target/mips/tcg/txx9_translate.c
R target/mips/translate.c
R target/mips/translate_addr_const.c
R target/mips/tx79.decode
R target/mips/tx79_translate.c
R target/mips/txx9_translate.c
Log Message:
-----------
target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
Commit: db6b6f4dbfb395c4fdc4f6e601315151dbbe0190
https://github.com/qemu/qemu/commit/db6b6f4dbfb395c4fdc4f6e601315151dbbe0190
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M hw/mips/meson.build
Log Message:
-----------
hw/mips: Restrict non-virtualized machines to TCG
Only the malta and loongson3-virt machines support KVM.
Restrict the other machines to TCG:
- mipssim
- magnum
- pica61
- fuloong2e
- boston
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-30-f4bug@amsat.org>
Commit: 1c13514449439b5ff1f746ed0bf73b298da39cf0
https://github.com/qemu/qemu/commit/1c13514449439b5ff1f746ed0bf73b298da39cf0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-05-02 (Sun, 02 May 2021)
Changed paths:
M .gitlab-ci.d/crossbuilds.yml
Log Message:
-----------
gitlab-ci: Add KVM mips64el cross-build jobs
Add a new job to cross-build the mips64el target without
the TCG accelerator (IOW: only KVM accelerator enabled).
Only build the mips64el target which is known to work
and has users.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-31-f4bug@amsat.org>
Commit: e93d8bcf9dbd5b8dd3b9ddbb1ece6a37e608f300
https://github.com/qemu/qemu/commit/e93d8bcf9dbd5b8dd3b9ddbb1ece6a37e608f300
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-05-03 (Mon, 03 May 2021)
Changed paths:
M .gitlab-ci.d/crossbuilds.yml
M MAINTAINERS
M hw/isa/piix4.c
M hw/mips/meson.build
M meson.build
R target/mips/addr.c
R target/mips/cp0_helper.c
R target/mips/cp0_timer.c
M target/mips/cpu.c
R target/mips/dsp_helper.c
A target/mips/fpu.c
R target/mips/fpu_helper.c
M target/mips/helper.h
M target/mips/internal.h
R target/mips/lmmi_helper.c
R target/mips/machine.c
M target/mips/meson.build
R target/mips/mips-semi.c
R target/mips/mips32r6.decode
R target/mips/mips64r6.decode
A target/mips/msa.c
R target/mips/msa32.decode
R target/mips/msa64.decode
R target/mips/msa_helper.c
R target/mips/msa_helper.h.inc
R target/mips/msa_translate.c
R target/mips/mxu_translate.c
R target/mips/op_helper.c
R target/mips/rel6_translate.c
A target/mips/sysemu/addr.c
A target/mips/sysemu/cp0.c
A target/mips/sysemu/cp0_timer.c
A target/mips/sysemu/machine.c
A target/mips/sysemu/meson.build
A target/mips/sysemu/physaddr.c
A target/mips/tcg/dsp_helper.c
A target/mips/tcg/exception.c
A target/mips/tcg/fpu_helper.c
A target/mips/tcg/ldst_helper.c
A target/mips/tcg/lmmi_helper.c
A target/mips/tcg/meson.build
A target/mips/tcg/mips32r6.decode
A target/mips/tcg/mips64r6.decode
A target/mips/tcg/msa32.decode
A target/mips/tcg/msa64.decode
A target/mips/tcg/msa_helper.c
A target/mips/tcg/msa_helper.h.inc
A target/mips/tcg/msa_translate.c
A target/mips/tcg/mxu_translate.c
A target/mips/tcg/op_helper.c
A target/mips/tcg/rel6_translate.c
A target/mips/tcg/sysemu/cp0_helper.c
A target/mips/tcg/sysemu/meson.build
A target/mips/tcg/sysemu/mips-semi.c
A target/mips/tcg/sysemu/special_helper.c
A target/mips/tcg/sysemu/tlb_helper.c
A target/mips/tcg/sysemu_helper.h.inc
A target/mips/tcg/tcg-internal.h
A target/mips/tcg/translate.c
A target/mips/tcg/translate_addr_const.c
A target/mips/tcg/tx79.decode
A target/mips/tcg/tx79_translate.c
A target/mips/tcg/txx9_translate.c
A target/mips/tcg/user/meson.build
A target/mips/tcg/user/tlb_helper.c
R target/mips/tlb_helper.c
R target/mips/translate.c
M target/mips/translate.h
R target/mips/translate_addr_const.c
R target/mips/tx79.decode
R target/mips/tx79_translate.c
R target/mips/txx9_translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging
MIPS patches queue
- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_irq() call in PIIX4 south bridge
- Add various missing fields to the MIPS CPU migration vmstate
- Lot of code moved around to allow TCG or KVM only builds
- Restrict non-virtualized machines to TCG
- Add KVM mips64el cross-build jobs to gitlab-ci
# gpg: Signature made Sun 02 May 2021 15:56:51 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-20210502: (36 commits)
gitlab-ci: Add KVM mips64el cross-build jobs
hw/mips: Restrict non-virtualized machines to TCG
target/mips: Move TCG source files under tcg/ sub directory
target/mips: Move CP0 helpers to sysemu/cp0.c
target/mips: Move exception management code to exception.c
target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
target/mips: Move tlb_helper.c to tcg/sysemu/
target/mips: Restrict mmu_init() to TCG
target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
target/mips: Move physical addressing code to sysemu/physaddr.c
target/mips: Move sysemu specific files under sysemu/ subfolder
target/mips: Move cpu_signal_handler definition around
target/mips: Add simple user-mode mips_cpu_tlb_fill()
target/mips: Add simple user-mode mips_cpu_do_interrupt()
target/mips: Introduce tcg-internal.h for TCG specific declarations
meson: Introduce meson_user_arch source set for arch-specific user-mode
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/15106f7dc329...e93d8bcf9dbd