[Qemu-commits] [qemu/qemu] a27c10: target/hexagon: translation changes

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[Qemu-commits] [qemu/qemu] a27c10: target/hexagon: translation changes

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] a27c10: target/hexagon: translation changes
Date:	Sat, 01 May 2021 12:45:43 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a27c100c23d2b23a8d5342b8d8d75e238f6342ba
      
https://github.com/qemu/qemu/commit/a27c100c23d2b23a8d5342b8d8d75e238f6342ba
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/translate.c

  Log Message:
  -----------
  target/hexagon: translation changes

Change cpu_ldl_code to translator_ldl.
Don't end the TB after every packet when HEX_DEBUG is on.
Make gen_check_store_width a simple call.

Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615783984-25918-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 4c82c2b433fab9814000e7794d9168044863ecfc
      
https://github.com/qemu/qemu/commit/4c82c2b433fab9814000e7794d9168044863ecfc
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/iclass.c

  Log Message:
  -----------
  target/hexagon: remove unnecessary checks in find_iclass_slots

Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615784037-26129-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1de468b3987e6a85bc0a046d444bf76659242dd1
      
https://github.com/qemu/qemu/commit/1de468b3987e6a85bc0a046d444bf76659242dd1
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/decode.c

  Log Message:
  -----------
  target/hexagon: Change DECODE_MAPPED_REG operand name to OPNUM

Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615784049-26215-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d9099caf04bda396e084429d3dd3f6601e23b7ca
      
https://github.com/qemu/qemu/commit/d9099caf04bda396e084429d3dd3f6601e23b7ca
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/op_helper.c

  Log Message:
  -----------
  target/hexagon: fix typo in comment

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615784115-26559-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5f261764cec291bb159ffecd291a1bfd6800215b
      
https://github.com/qemu/qemu/commit/5f261764cec291bb159ffecd291a1bfd6800215b
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h

  Log Message:
  -----------
  target/hexagon: remove unnecessary semicolons

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reported-by: Richard Henderson <<richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1615784100-26459-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d799f8ad08742e9c042e208d970febf87a2c4901
      
https://github.com/qemu/qemu/commit/d799f8ad08742e9c042e208d970febf87a2c4901
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/genptr.c

  Log Message:
  -----------
  Hexagon (target/hexagon) TCG generation cleanup

Simplify TCG generation of hex_reg_written

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-2-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: edf26ade436f69c170e7eec77d4b5d1d2db78d3f
      
https://github.com/qemu/qemu/commit/edf26ade436f69c170e7eec77d4b5d1d2db78d3f
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/genptr.c

  Log Message:
  -----------
  Hexagon (target/hexagon) cleanup gen_log_predicated_reg_write_pair

Similar to previous cleanup of gen_log_predicated_reg_write

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-3-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2d27cebbf8994621e0a4bda9609d24982f5ba8c6
      
https://github.com/qemu/qemu/commit/2d27cebbf8994621e0a4bda9609d24982f5ba8c6
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/cpu.c
    M target/hexagon/decode.c
    M target/hexagon/fma_emu.c
    M target/hexagon/op_helper.c
    M target/hexagon/translate.c

  Log Message:
  -----------
  Hexagon (target/hexagon) remove unnecessary inline directives

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-4-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7d9ab2021f98b93a5af10f594daad6472b530e4d
      
https://github.com/qemu/qemu/commit/7d9ab2021f98b93a5af10f594daad6472b530e4d
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M linux-user/hexagon/cpu_loop.c
    M target/hexagon/cpu.c
    M target/hexagon/cpu.h
    M target/hexagon/op_helper.c
    M target/hexagon/translate.c

  Log Message:
  -----------
  Hexagon (target/hexagon) use env_archcpu and env_cpu

Remove hexagon_env_get_cpu and replace with env_archcpu
Replace CPU(hexagon_env_get_cpu(env)) with env_cpu(env)

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-5-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 743debbc373ffcd8eb66dc388632c03f5e951bfc
      
https://github.com/qemu/qemu/commit/743debbc373ffcd8eb66dc388632c03f5e951bfc
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/translate.c
    M target/hexagon/translate.h

  Log Message:
  -----------
  Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN

When exiting a TB, generate all the code before returning from
hexagon_tr_translate_packet so that nothing needs to be done in
hexagon_tr_tb_stop.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-6-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6c677c60ae34bd2c7936781ee8969e41b1dac81e
      
https://github.com/qemu/qemu/commit/6c677c60ae34bd2c7936781ee8969e41b1dac81e
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg_funcs.py
    M target/hexagon/genptr.c
    M target/hexagon/translate.c
    M target/hexagon/translate.h
    M tests/tcg/hexagon/misc.c

  Log Message:
  -----------
  Hexagon (target/hexagon) decide if pred has been written at TCG gen time

Multiple writes to the same preg are and'ed together.  Rather than
generating a runtime check, we can determine at TCG generation time
if the predicate has previously been written in the packet.

Test added to tests/tcg/hexagon/misc.c

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-7-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 92cfa25fd2cf65749a93507e132225066bc19ed5
      
https://github.com/qemu/qemu/commit/92cfa25fd2cf65749a93507e132225066bc19ed5
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/cpu_bits.h
    M target/hexagon/decode.c
    M target/hexagon/insn.h
    M target/hexagon/op_helper.c
    M target/hexagon/translate.c
    M target/hexagon/translate.h

  Log Message:
  -----------
  Hexagon (target/hexagon) change variables from int to bool when appropriate

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-8-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 85511161f7cd1f52a177413e2128b1a05b71163e
      
https://github.com/qemu/qemu/commit/85511161f7cd1f52a177413e2128b1a05b71163e
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c
    M target/hexagon/arch.h
    M target/hexagon/macros.h

  Log Message:
  -----------
  Hexagon (target/hexagon) remove unused carry_from_add64 function

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-9-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8c36752435da380ddf2733d499c4be2cdb8c1b6f
      
https://github.com/qemu/qemu/commit/8c36752435da380ddf2733d499c4be2cdb8c1b6f
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c

  Log Message:
  -----------
  Hexagon (target/hexagon) change type of softfloat_roundingmodes

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-10-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: c0336c87b773614eebd23714e3a866bfcd78e9f2
      
https://github.com/qemu/qemu/commit/c0336c87b773614eebd23714e3a866bfcd78e9f2
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M fpu/softfloat-specialize.c.inc
    M target/hexagon/cpu.c
    M target/hexagon/op_helper.c

  Log Message:
  -----------
  Hexagon (target/hexagon) use softfloat default NaN and tininess

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-11-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1cb532fe45991b70cf47c414e0bc4fe63f571a8a
      
https://github.com/qemu/qemu/commit/1cb532fe45991b70cf47c414e0bc4fe63f571a8a
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c

  Log Message:
  -----------
  Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-12-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b3f37abdd3f4919c81ea42f9f729875544623df2
      
https://github.com/qemu/qemu/commit/b3f37abdd3f4919c81ea42f9f729875544623df2
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    R target/hexagon/conv_emu.c
    R target/hexagon/conv_emu.h
    M target/hexagon/fma_emu.c
    M target/hexagon/helper.h
    M target/hexagon/meson.build
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/fpstuff.c

  Log Message:
  -----------
  Hexagon (target/hexagon) use softfloat for float-to-int conversions

Use the proper return for helpers that convert to unsigned
Remove target/hexagon/conv_emu.[ch]

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-13-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9fe33c0e7048b979d39ee579962d94871ea42e0a
      
https://github.com/qemu/qemu/commit/9fe33c0e7048b979d39ee579962d94871ea42e0a
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/imported/compare.idef

  Log Message:
  -----------
  Hexagon (target/hexagon) cleanup ternary operators in semantics

Change  (cond ? (res = x) : (res = y)) to res = (cond ? x : y)

This makes the semnatics easier to for idef-parser to deal with

The following instructions are impacted
    C2_any8
    C2_all8
    C2_mux
    C2_muxii
    C2_muxir
    C2_muxri

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-14-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 80be682844ddfeffa21576ce0cb61d06bf6b87f8
      
https://github.com/qemu/qemu/commit/80be682844ddfeffa21576ce0cb61d06bf6b87f8
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/reg_fields.c
    M target/hexagon/reg_fields.h

  Log Message:
  -----------
  Hexagon (target/hexagon) cleanup reg_field_info definition

Include size in declaration
Remove {0, 0} entry

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-15-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a33872eb533c5b4d2eb7658fa07e6a281bfd609b
      
https://github.com/qemu/qemu/commit/a33872eb533c5b4d2eb7658fa07e6a281bfd609b
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/genptr.c

  Log Message:
  -----------
  Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-16-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 85580a65577898288a29d849160601895979c661
      
https://github.com/qemu/qemu/commit/85580a65577898288a29d849160601895979c661
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/genptr.c
    M target/hexagon/helper.h
    M target/hexagon/internal.h
    M target/hexagon/op_helper.c
    M target/hexagon/translate.c
    M target/hexagon/translate.h

  Log Message:
  -----------
  Hexagon (target/hexagon) compile all debug code

Change #if HEX_DEBUG to if (HEX_DEBUG) so the debug code doesn't bit rot

Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-17-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: d934c16d8a1e0fb82fd4abfa54dcb5217430577c
      
https://github.com/qemu/qemu/commit/d934c16d8a1e0fb82fd4abfa54dcb5217430577c
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c
    M target/hexagon/arch.h
    M target/hexagon/gen_tcg.h
    M target/hexagon/helper.h
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/float.idef
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/Makefile.target
    M tests/tcg/hexagon/fpstuff.c
    A tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Hexagon (target/hexagon) add F2_sfrecipa instruction

Rd32,Pe4 = sfrecipa(Rs32, Rt32)
    Recripocal approx

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-18-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: dd8705bdf529d2c694ec3a4d4a2c18bb770d5c6c
      
https://github.com/qemu/qemu/commit/dd8705bdf529d2c694ec3a4d4a2c18bb770d5c6c
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c
    M target/hexagon/arch.h
    M target/hexagon/gen_tcg.h
    M target/hexagon/helper.h
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/float.idef
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/fpstuff.c
    M tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Hexagon (target/hexagon) add F2_sfinvsqrta

Rd32,Pe4 = sfinvsqrta(Rs32)
    Square root approx

The helper packs the 2 32-bit results into a 64-bit value,
and the fGEN_TCG override unpacks them into the proper results.

Test cases in tests/tcg/hexagon/multi_result.c
FP exception tests added to tests/tcg/hexagon/fpstuff.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-19-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: da74cd2dced1ca36ffa864e70cf5ee8d3a8c1fab
      
https://github.com/qemu/qemu/commit/da74cd2dced1ca36ffa864e70cf5ee8d3a8c1fab
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/helper.h
    M target/hexagon/imported/alu.idef
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Hexagon (target/hexagon) add A5_ACS (vacsh)

Rxx32,Pe4 = vacsh(Rss32, Rtt32)
    Add compare and select elements of two vectors

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-20-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0a65d286936a5fd0ac459a0a047e527ce55731e3
      
https://github.com/qemu/qemu/commit/0a65d286936a5fd0ac459a0a047e527ce55731e3
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/genptr.c
    M target/hexagon/imported/alu.idef
    M target/hexagon/imported/encode_pp.def
    M tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Hexagon (target/hexagon) add A6_vminub_RdP

Rdd32,Pe4 = vminub(Rtt32, Rss32)
    Vector min of bytes

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-21-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 57d352ac298b27617a53783305af2554025060d9
      
https://github.com/qemu/qemu/commit/57d352ac298b27617a53783305af2554025060d9
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/genptr.c
    M target/hexagon/imported/alu.idef
    M target/hexagon/imported/encode_pp.def
    M tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Hexagon (target/hexagon) add A4_addp_c/A4_subp_c

Rdd32 = add(Rss32, Rtt32, Px4):carry
    Add with carry
Rdd32 = sub(Rss32, Rtt32, Px4):carry
    Sub with carry

Test cases in tests/tcg/hexagon/multi_result.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-22-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 893df14ed1bfea93fe312e4a3bdd3617b7e7ace1
      
https://github.com/qemu/qemu/commit/893df14ed1bfea93fe312e4a3bdd3617b7e7ace1
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/genptr.c
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/ldst.idef
    M target/hexagon/imported/macros.def
    M target/hexagon/macros.h
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/Makefile.target
    A tests/tcg/hexagon/circ.c

  Log Message:
  -----------
  Hexagon (target/hexagon) circular addressing

The following instructions are added
    L2_loadrub_pci          Rd32 = memub(Rx32++#s4:0:circ(Mu2))
    L2_loadrb_pci           Rd32 = memb(Rx32++#s4:0:circ(Mu2))
    L2_loadruh_pci          Rd32 = memuh(Rx32++#s4:1:circ(Mu2))
    L2_loadrh_pci           Rd32 = memh(Rx32++#s4:1:circ(Mu2))
    L2_loadri_pci           Rd32 = memw(Rx32++#s4:2:circ(Mu2))
    L2_loadrd_pci           Rdd32 = memd(Rx32++#s4:3:circ(Mu2))
    S2_storerb_pci          memb(Rx32++#s4:0:circ(Mu2)) = Rt32
    S2_storerh_pci          memh(Rx32++#s4:1:circ(Mu2)) = Rt32
    S2_storerf_pci          memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32
    S2_storeri_pci          memw(Rx32++#s4:2:circ(Mu2)) = Rt32
    S2_storerd_pci          memd(Rx32++#s4:3:circ(Mu2)) = Rtt32
    S2_storerbnew_pci       memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new
    S2_storerhnew_pci       memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new
    S2_storerinew_pci       memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new
    L2_loadrub_pcr          Rd32 = memub(Rx32++I:circ(Mu2))
    L2_loadrb_pcr           Rd32 = memb(Rx32++I:circ(Mu2))
    L2_loadruh_pcr          Rd32 = memuh(Rx32++I:circ(Mu2))
    L2_loadrh_pcr           Rd32 = memh(Rx32++I:circ(Mu2))
    L2_loadri_pcr           Rd32 = memw(Rx32++I:circ(Mu2))
    L2_loadrd_pcr           Rdd32 = memd(Rx32++I:circ(Mu2))
    S2_storerb_pcr          memb(Rx32++I:circ(Mu2)) = Rt32
    S2_storerh_pcr          memh(Rx32++I:circ(Mu2)) = Rt32
    S2_storerf_pcr          memh(Rx32++I:circ(Mu2)) = Rt32.H32
    S2_storeri_pcr          memw(Rx32++I:circ(Mu2)) = Rt32
    S2_storerd_pcr          memd(Rx32++I:circ(Mu2)) = Rtt32
    S2_storerbnew_pcr       memb(Rx32++I:circ(Mu2)) = Nt8.new
    S2_storerhnew_pcr       memh(Rx32++I:circ(Mu2)) = Nt8.new
    S2_storerinew_pcr       memw(Rx32++I:circ(Mu2)) = Nt8.new

Test cases in tests/tcg/hexagon/circ.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 27f582b2ffc85d1e1c23698a79d667f1da0b8f64
      
https://github.com/qemu/qemu/commit/27f582b2ffc85d1e1c23698a79d667f1da0b8f64
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/helper.h
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/ldst.idef
    M target/hexagon/imported/macros.def
    M target/hexagon/macros.h
    M target/hexagon/op_helper.c
    M tests/tcg/hexagon/Makefile.target
    A tests/tcg/hexagon/brev.c

  Log Message:
  -----------
  Hexagon (target/hexagon) bit reverse (brev) addressing

The following instructions are added
    L2_loadrub_pbr          Rd32 = memub(Rx32++Mu2:brev)
    L2_loadrb_pbr           Rd32 = memb(Rx32++Mu2:brev)
    L2_loadruh_pbr          Rd32 = memuh(Rx32++Mu2:brev)
    L2_loadrh_pbr           Rd32 = memh(Rx32++Mu2:brev)
    L2_loadri_pbr           Rd32 = memw(Rx32++Mu2:brev)
    L2_loadrd_pbr           Rdd32 = memd(Rx32++Mu2:brev)
    S2_storerb_pbr          memb(Rx32++Mu2:brev).=.Rt32
    S2_storerh_pbr          memh(Rx32++Mu2:brev).=.Rt32
    S2_storerf_pbr          memh(Rx32++Mu2:brev).=.Rt.H32
    S2_storeri_pbr          memw(Rx32++Mu2:brev).=.Rt32
    S2_storerd_pbr          memd(Rx32++Mu2:brev).=.Rt32
    S2_storerinew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new
    S2_storerbnew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new
    S2_storerhnew_pbr       memw(Rx32++Mu2:brev).=.Nt8.new

Test cases in tests/tcg/hexagon/brev.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 883c43834a1d0ca392215a0ee298afd42d69085a
      
https://github.com/qemu/qemu/commit/883c43834a1d0ca392215a0ee298afd42d69085a
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/genptr.c
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/ldst.idef
    M target/hexagon/macros.h
    M tests/tcg/hexagon/Makefile.target
    A tests/tcg/hexagon/load_unpack.c

  Log Message:
  -----------
  Hexagon (target/hexagon) load and unpack bytes instructions

The following instructions are added
    L2_loadbzw2_io          Rd32 = memubh(Rs32+#s11:1)
    L2_loadbzw4_io          Rdd32 = memubh(Rs32+#s11:1)
    L2_loadbsw2_io          Rd32 = membh(Rs32+#s11:1)
    L2_loadbsw4_io          Rdd32 = membh(Rs32+#s11:1)

    L4_loadbzw2_ur          Rd32 = memubh(Rt32<<#u2+#U6)
    L4_loadbzw4_ur          Rdd32 = memubh(Rt32<<#u2+#U6)
    L4_loadbsw2_ur          Rd32 = membh(Rt32<<#u2+#U6)
    L4_loadbsw4_ur          Rdd32 = membh(Rt32<<#u2+#U6)

    L4_loadbzw2_ap          Rd32 = memubh(Re32=#U6)
    L4_loadbzw4_ap          Rdd32 = memubh(Re32=#U6)
    L4_loadbsw2_ap          Rd32 = membh(Re32=#U6)
    L4_loadbsw4_ap          Rdd32 = membh(Re32=#U6)

    L2_loadbzw2_pr          Rd32 = memubh(Rx32++Mu2)
    L2_loadbzw4_pr          Rdd32 = memubh(Rx32++Mu2)
    L2_loadbsw2_pr          Rd32 = membh(Rx32++Mu2)
    L2_loadbsw4_pr          Rdd32 = membh(Rx32++Mu2)

    L2_loadbzw2_pbr         Rd32 = memubh(Rx32++Mu2:brev)
    L2_loadbzw4_pbr         Rdd32 = memubh(Rx32++Mu2:brev)
    L2_loadbsw2_pbr         Rd32 = membh(Rx32++Mu2:brev)
    L2_loadbsw4_pbr         Rdd32 = membh(Rx32++Mu2:brev)

    L2_loadbzw2_pi          Rd32 = memubh(Rx32++#s4:1)
    L2_loadbzw4_pi          Rdd32 = memubh(Rx32++#s4:1)
    L2_loadbsw2_pi          Rd32 = membh(Rx32++#s4:1)
    L2_loadbsw4_pi          Rdd32 = membh(Rx32++#s4:1)

    L2_loadbzw2_pci         Rd32 = memubh(Rx32++#s4:1:circ(Mu2))
    L2_loadbzw4_pci         Rdd32 = memubh(Rx32++#s4:1:circ(Mu2))
    L2_loadbsw2_pci         Rd32 = membh(Rx32++#s4:1:circ(Mu2))
    L2_loadbsw4_pci         Rdd32 = membh(Rx32++#s4:1:circ(Mu2))

    L2_loadbzw2_pcr         Rd32 = memubh(Rx32++I:circ(Mu2))
    L2_loadbzw4_pcr         Rdd32 = memubh(Rx32++I:circ(Mu2))
    L2_loadbsw2_pcr         Rd32 = membh(Rx32++I:circ(Mu2))
    L2_loadbsw4_pcr         Rdd32 = membh(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_unpack.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-25-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ded83339e65c0d1a47efd7afcb48ed5e100e5f96
      
https://github.com/qemu/qemu/commit/ded83339e65c0d1a47efd7afcb48ed5e100e5f96
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/gen_tcg.h
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/ldst.idef
    M tests/tcg/hexagon/Makefile.target
    A tests/tcg/hexagon/load_align.c

  Log Message:
  -----------
  Hexagon (target/hexagon) load into shifted register instructions

The following instructions are added
    L2_loadalignb_io          Ryy32 = memb_fifo(Rs32+#s11:1)
    L2_loadalignh_io          Ryy32 = memh_fifo(Rs32+#s11:1)
    L4_loadalignb_ur          Ryy32 = memb_fifo(Rt32<<#u2+#U6)
    L4_loadalignh_ur          Ryy32 = memh_fifo(Rt32<<#u2+#U6)
    L4_loadalignb_ap          Ryy32 = memb_fifo(Re32=#U6)
    L4_loadalignh_ap          Ryy32 = memh_fifo(Re32=#U6)
    L2_loadalignb_pr          Ryy32 = memb_fifo(Rx32++Mu2)
    L2_loadalignh_pr          Ryy32 = memh_fifo(Rx32++Mu2)
    L2_loadalignb_pbr         Ryy32 = memb_fifo(Rx32++Mu2:brev)
    L2_loadalignh_pbr         Ryy32 = memh_fifo(Rx32++Mu2:brev)
    L2_loadalignb_pi          Ryy32 = memb_fifo(Rx32++#s4:1)
    L2_loadalignh_pi          Ryy32 = memh_fifo(Rx32++#s4:1)
    L2_loadalignb_pci         Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2))
    L2_loadalignh_pci         Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2))
    L2_loadalignb_pcr         Ryy32 = memb_fifo(Rx32++I:circ(Mu2))
    L2_loadalignh_pcr         Ryy32 = memh_fifo(Rx32++I:circ(Mu2))

Test cases in tests/tcg/hexagon/load_align.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 26f7c044ad234c3dfa7ca2ddf047a71d815e66dc
      
https://github.com/qemu/qemu/commit/26f7c044ad234c3dfa7ca2ddf047a71d815e66dc
  Author: Taylor Simpson <tsimpson@quicinc.com>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M target/hexagon/arch.c
    M target/hexagon/arch.h
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/macros.def
    M target/hexagon/imported/shift.idef
    M target/hexagon/macros.h
    M tests/tcg/hexagon/misc.c

  Log Message:
  -----------
  Hexagon (target/hexagon) CABAC decode bin

The following instruction is added
    S2_cabacdecbin            Rdd32=decbin(Rss32,Rtt32)

Test cases added to tests/tcg/hexagon/misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 86f8364dcbadc7db1f5091b53ad636bfaa63f41f
      
https://github.com/qemu/qemu/commit/86f8364dcbadc7db1f5091b53ad636bfaa63f41f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-05-01 (Sat, 01 May 2021)

  Changed paths:
    M fpu/softfloat-specialize.c.inc
    M linux-user/hexagon/cpu_loop.c
    M target/hexagon/arch.c
    M target/hexagon/arch.h
    R target/hexagon/conv_emu.c
    R target/hexagon/conv_emu.h
    M target/hexagon/cpu.c
    M target/hexagon/cpu.h
    M target/hexagon/cpu_bits.h
    M target/hexagon/decode.c
    M target/hexagon/fma_emu.c
    M target/hexagon/gen_tcg.h
    M target/hexagon/gen_tcg_funcs.py
    M target/hexagon/genptr.c
    M target/hexagon/helper.h
    M target/hexagon/iclass.c
    M target/hexagon/imported/alu.idef
    M target/hexagon/imported/compare.idef
    M target/hexagon/imported/encode_pp.def
    M target/hexagon/imported/float.idef
    M target/hexagon/imported/ldst.idef
    M target/hexagon/imported/macros.def
    M target/hexagon/imported/shift.idef
    M target/hexagon/insn.h
    M target/hexagon/internal.h
    M target/hexagon/macros.h
    M target/hexagon/meson.build
    M target/hexagon/op_helper.c
    M target/hexagon/reg_fields.c
    M target/hexagon/reg_fields.h
    M target/hexagon/translate.c
    M target/hexagon/translate.h
    M tests/tcg/hexagon/Makefile.target
    A tests/tcg/hexagon/brev.c
    A tests/tcg/hexagon/circ.c
    M tests/tcg/hexagon/fpstuff.c
    A tests/tcg/hexagon/load_align.c
    A tests/tcg/hexagon/load_unpack.c
    M tests/tcg/hexagon/misc.c
    A tests/tcg/hexagon/multi_result.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210501' into 
staging

Minor cleanups.
Finish the rest of the hexagon integer instructions.

# gpg: Signature made Sat 01 May 2021 19:41:00 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-hex-20210501: (31 commits)
  Hexagon (target/hexagon) CABAC decode bin
  Hexagon (target/hexagon) load into shifted register instructions
  Hexagon (target/hexagon) load and unpack bytes instructions
  Hexagon (target/hexagon) bit reverse (brev) addressing
  Hexagon (target/hexagon) circular addressing
  Hexagon (target/hexagon) add A4_addp_c/A4_subp_c
  Hexagon (target/hexagon) add A6_vminub_RdP
  Hexagon (target/hexagon) add A5_ACS (vacsh)
  Hexagon (target/hexagon) add F2_sfinvsqrta
  Hexagon (target/hexagon) add F2_sfrecipa instruction
  Hexagon (target/hexagon) compile all debug code
  Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h
  Hexagon (target/hexagon) cleanup reg_field_info definition
  Hexagon (target/hexagon) cleanup ternary operators in semantics
  Hexagon (target/hexagon) use softfloat for float-to-int conversions
  Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn
  Hexagon (target/hexagon) use softfloat default NaN and tininess
  Hexagon (target/hexagon) change type of softfloat_roundingmodes
  Hexagon (target/hexagon) remove unused carry_from_add64 function
  Hexagon (target/hexagon) change variables from int to bool when appropriate
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/a31aa2127ede...86f8364dcbad
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