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[Qemu-commits] [qemu/qemu] 0cef06: Update version for v6.0.0-rc5 release
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 0cef06: Update version for v6.0.0-rc5 release |
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Date: |
Fri, 30 Apr 2021 03:35:39 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 0cef06d18762374c94eb4d511717a4735d668a24
https://github.com/qemu/qemu/commit/0cef06d18762374c94eb4d511717a4735d668a24
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-26 (Mon, 26 Apr 2021)
Changed paths:
M VERSION
Log Message:
-----------
Update version for v6.0.0-rc5 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 609d7596524ab204ccd71ef42c9eee4c7c338ea4
https://github.com/qemu/qemu/commit/609d7596524ab204ccd71ef42c9eee4c7c338ea4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-29 (Thu, 29 Apr 2021)
Changed paths:
M VERSION
Log Message:
-----------
Update version for v6.0.0 release
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ccdf06c1db192152ac70a1dd974c624f566cb7d4
https://github.com/qemu/qemu/commit/ccdf06c1db192152ac70a1dd974c624f566cb7d4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M VERSION
Log Message:
-----------
Open 6.1 development tree
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bf559ee4025adaf9713e22def862d31f1db5994e
https://github.com/qemu/qemu/commit/bf559ee4025adaf9713e22def862d31f1db5994e
Author: Kunkun Jiang <jiangkunkun@huawei.com>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Support 16K translation granule
The driver can query some bits in SMMUv3 IDR5 to learn which
translation granules are supported. Arm recommends that SMMUv3
implementations support at least 4K and 64K granules. But in
the vSMMUv3, there seems to be no reason not to support 16K
translation granule. In addition, if 16K is not supported,
vSVA will failed to be enabled in the future for 16K guest
kernel. So it'd better to support it.
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8196fe9d83d6519128b514f332418bae06513970
https://github.com/qemu/qemu/commit/8196fe9d83d6519128b514f332418bae06513970
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Make Thumb store insns UNDEF for Rn==1111
The Arm ARM specifies that for Thumb encodings of the various plain
store insns, if the Rn field is 1111 then we must UNDEF. This is
different from the Arm encodings, where this case is either
UNPREDICTABLE or has well-defined behaviour. The exclusive stores,
store-release and STRD do not have this UNDEF case for any encoding.
Enforce the UNDEF for this case in the Thumb plain store insns.
Fixes: https://bugs.launchpad.net/qemu/+bug/1922887
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210408162402.5822-1-peter.maydell@linaro.org
Commit: 98f96050aacb1f48956413832ae36392169801a1
https://github.com/qemu/qemu/commit/98f96050aacb1f48956413832ae36392169801a1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Fix mte_checkN
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags. But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses. So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.
Therefore, the first failure is always either the first byte of the
access, or the first byte of the granule.
In addition, some of the arithmetic is off for last-first -> count.
This does not become directly visible until a later patch that passes
single bytes into this function, so ptr == ptr_last.
Buglink: https://bugs.launchpad.net/bugs/1921948
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked a comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f8c8a8606071b2966f83ebaccc69714ac3cad548
https://github.com/qemu/qemu/commit/f8c8a8606071b2966f83ebaccc69714ac3cad548
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Split out mte_probe_int
Split out a helper function from mte_checkN to perform
all of the checking and address manpulation. So far,
just use this in mte_checkN itself.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a09a21345e8adb4734ecb5be59bac9c4d82aa85
https://github.com/qemu/qemu/commit/4a09a21345e8adb4734ecb5be59bac9c4d82aa85
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/mte_helper.c
Log Message:
-----------
target/arm: Fix unaligned checks for mte_check1, mte_probe1
We were incorrectly assuming that only the first byte of an MTE access
is checked against the tags. But per the ARM, unaligned accesses are
pre-decomposed into single-byte accesses. So by the time we reach the
actual MTE check in the ARM pseudocode, all accesses are aligned.
We cannot tell a priori whether or not a given scalar access is aligned,
therefore we must at least check. Use mte_probe_int, which is already
set up for checking multiple granules.
Buglink: https://bugs.launchpad.net/bugs/1921948
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 09641ef93112c45bc32cf86a4999d0e0532909c3
https://github.com/qemu/qemu/commit/09641ef93112c45bc32cf86a4999d0e0532909c3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-5.c
Log Message:
-----------
test/tcg/aarch64: Add mte-5
Buglink: https://bugs.launchpad.net/bugs/1921948
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 28f3250306e52ae94df9faab93b9d0167fe6b587
https://github.com/qemu/qemu/commit/28f3250306e52ae94df9faab93b9d0167fe6b587
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/translate-a64.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1
After recent changes, mte_checkN does not use ESIZE,
and mte_check1 never used TSIZE. We can combine the
two into a single field: SIZEM1.
Choose to pass size - 1 because size == 0 is never used,
our immediate need in mte_probe_int is for the address
of the last byte (ptr + size - 1), and since almost all
operations are powers of 2, this makes the immediate
constant one bit smaller.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bd47b61c5ebc8c5f696910644125a28115d3f6ea
https://github.com/qemu/qemu/commit/bd47b61c5ebc8c5f696910644125a28115d3f6ea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/helper-a64.h
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/sve_helper.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Merge mte_check1, mte_checkN
The mte_check1 and mte_checkN functions are now identical.
Drop mte_check1 and rename mte_checkN to mte_check.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d304d280b3167289323f3f2c6c2fbfa1dfe8d1d7
https://github.com/qemu/qemu/commit/d304d280b3167289323f3f2c6c2fbfa1dfe8d1d7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Rename mte_probe1 to mte_probe
For consistency with the mte_check1 + mte_checkN merge
to mte_check, rename the probe function as well.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4c3310c73f7349f1aabae55a7babd6419eeb1d04
https://github.com/qemu/qemu/commit/4c3310c73f7349f1aabae55a7babd6419eeb1d04
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Simplify sve mte checking
Now that mte_check1 and mte_checkN have been merged, we can
merge sve_cont_ldst_mte_check1 and sve_cont_ldst_mte_checkN.
Which means that we can eliminate the function pointer into
sve_ldN_r and sve_stN_r, calling sve_cont_ldst_mte_check directly.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 33e74c3172defc841692b4281d2dbd8f8a966e17
https://github.com/qemu/qemu/commit/33e74c3172defc841692b4281d2dbd8f8a966e17
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Remove log2_esize parameter to gen_mte_checkN
The log2_esize parameter is not used except trivially.
Drop the parameter and the deferral to gen_mte_check1.
This fixes a bug in that the parameters as documented
in the header file were the reverse from those in the
implementation. Which meant that translate-sve.c was
passing the parameters in the wrong order.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416183106.1516563-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a736cbc303f3c3f79b7b0b09e0dd4e18c8bcf94c
https://github.com/qemu/qemu/commit/a736cbc303f3c3f79b7b0b09e0dd4e18c8bcf94c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/neon-ls.decode
M target/arm/translate-neon.c.inc
Log Message:
-----------
target/arm: Fix decode of align in VLDST_single
The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field. This error was hidden
by what should have been unnecessary masking in translate.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6a01eab7d823d8ae7430015e27922370f4bf9107
https://github.com/qemu/qemu/commit/6a01eab7d823d8ae7430015e27922370f4bf9107
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename TBFLAG_A32, SCTLR_B
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So SCTLR_B -> SCTLR__B in the 3 uses, and document it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ae6eb1e9b3ccc211d96261a5c650e6650b508aa6
https://github.com/qemu/qemu/commit/ae6eb1e9b3ccc211d96261a5c650e6650b508aa6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Rename TBFLAG_ANY, PSTATE_SS
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So PSTATE_SS -> PSTATE__SS in the uses, and document it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a729a46b05ab09e473cd757ee7a62373a175fa62
https://github.com/qemu/qemu/commit/a729a46b05ab09e473cd757ee7a62373a175fa62
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Add wrapper macros for accessing tbflags
We're about to split tbflags into two parts. These macros
will ensure that the correct part is used with the correct
set of bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3902bfc6f06144016b8b25f5b6fb2211e85406fc
https://github.com/qemu/qemu/commit/3902bfc6f06144016b8b25f5b6fb2211e85406fc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Introduce CPUARMTBFlags
In preparation for splitting tb->flags across multiple
fields, introduce a structure to hold the value(s).
So far this only migrates the one uint32_t and fixes
all of the places that require adjustment to match.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a378206a205a65c182854a961d99acbce00cda86
https://github.com/qemu/qemu/commit/a378206a205a65c182854a961d99acbce00cda86
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Move mode specific TB flags to tb->cs_base
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5896f39253ead37f65a2c13a9b0066f56c282d4c
https://github.com/qemu/qemu/commit/5896f39253ead37f65a2c13a9b0066f56c282d4c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move TBFLAG_AM32 bits to the top
Now that these bits have been moved out of tb->flags,
where TBFLAG_ANY was filling from the top, move AM32
to fill from the top, and A32 and M32 to fill from the
bottom. This means fewer changes when adding new bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eee81d41ec4c5bf9bbde4e4d35648e29e2244f3f
https://github.com/qemu/qemu/commit/eee81d41ec4c5bf9bbde4e4d35648e29e2244f3f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move TBFLAG_ANY bits to the bottom
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd
https://github.com/qemu/qemu/commit/4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9d486b40e895b0e4cfaf47a0bdbd9144547b66d5
https://github.com/qemu/qemu/commit/9d486b40e895b0e4cfaf47a0bdbd9144547b66d5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness
Create a finalize_memop function that computes alignment and
endianness and returns the final MemOp for the operation.
Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special
handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32
so that s->be_data is not added by the callers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 37bf7a055f6b26a398dd0e953bf73d44e2312b33
https://github.com/qemu/qemu/commit/37bf7a055f6b26a398dd0e953bf73d44e2312b33
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
This is the only caller. Adjust some commentary to talk
about SCTLR_B instead of the vanishing function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9565ac4cc7e1d1aaccf3d8c6aed423b776e7995f
https://github.com/qemu/qemu/commit/9565ac4cc7e1d1aaccf3d8c6aed423b776e7995f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: abe66294e1d4899b312c296e93abcd3b88f2492e
https://github.com/qemu/qemu/commit/abe66294e1d4899b312c296e93abcd3b88f2492e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
Log Message:
-----------
target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.
This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes. Thus we
retain an "internal" interface which is identical to the
current gen_aa32_{ld,st}_i64 interface.
The "new" interface will gain users as we remove the legacy
interfaces, gen_aa32_ld64 and gen_aa32_st64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4d753eb5fb03ee7bc71ecd453a650b7546be81da
https://github.com/qemu/qemu/commit/4d753eb5fb03ee7bc71ecd453a650b7546be81da
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Enforce word alignment for LDRD/STRD
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 824efdf5256399c9830941ddd78c28e3aa4618d8
https://github.com/qemu/qemu/commit/824efdf5256399c9830941ddd78c28e3aa4618d8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
https://github.com/qemu/qemu/commit/2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Enforce alignment for LDM/STM
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c0c7f66087b193303bf9afe6e5e675fd02a17e12
https://github.com/qemu/qemu/commit/c0c7f66087b193303bf9afe6e5e675fd02a17e12
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Enforce alignment for RFE
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2fd0800c68b48c5402eea0f88bd68aadfdc15004
https://github.com/qemu/qemu/commit/2fd0800c68b48c5402eea0f88bd68aadfdc15004
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Enforce alignment for SRS
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ad9aeae1a9bbb3498bb8acfc13799f9e1cd86c97
https://github.com/qemu/qemu/commit/ad9aeae1a9bbb3498bb8acfc13799f9e1cd86c97
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-vfp.c.inc
Log Message:
-----------
target/arm: Enforce alignment for VLDM/VSTM
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6cd623d166025c8299f76ba0389fd7e879f82779
https://github.com/qemu/qemu/commit/6cd623d166025c8299f76ba0389fd7e879f82779
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-vfp.c.inc
Log Message:
-----------
target/arm: Enforce alignment for VLDR/VSTR
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a8502b37f69f256456ee6599a7850db38e5cc90a
https://github.com/qemu/qemu/commit/a8502b37f69f256456ee6599a7850db38e5cc90a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-neon.c.inc
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Enforce alignment for VLDn (all lanes)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7c68c196cf693e6098a04bd24985004db5983914
https://github.com/qemu/qemu/commit/7c68c196cf693e6098a04bd24985004db5983914
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-neon.c.inc
Log Message:
-----------
target/arm: Enforce alignment for VLDn/VSTn (multiple)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 88976ff0a4a8b27046df6fd05fb7be70a2f987da
https://github.com/qemu/qemu/commit/88976ff0a4a8b27046df6fd05fb7be70a2f987da
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-neon.c.inc
Log Message:
-----------
target/arm: Enforce alignment for VLDn/VSTn (single)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dc821642296ad0307ae6c0220e4b9ba1ae165d9e
https://github.com/qemu/qemu/commit/dc821642296ad0307ae6c0220e4b9ba1ae165d9e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use finalize_memop for aa64 gpr load/store
In the case of gpr load, merge the size and is_signed arguments;
otherwise, simply convert size to memop.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4044a3cd1cdf07503b1fe896ca145328dceba435
https://github.com/qemu/qemu/commit/4044a3cd1cdf07503b1fe896ca145328dceba435
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use finalize_memop for aa64 fpr load/store
For 128-bit load/store, use 16-byte alignment. This
requires that we perform the two operations in the
correct order so that we generate the alignment fault
before modifying memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: acb07e08d634bc36a18936dd5e2ebc318bcaf3db
https://github.com/qemu/qemu/commit/acb07e08d634bc36a18936dd5e2ebc318bcaf3db
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enforce alignment for aa64 load-acq/store-rel
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a9e89e539ec3a67f5257ce055a8ed38bd58fc89f
https://github.com/qemu/qemu/commit/a9e89e539ec3a67f5257ce055a8ed38bd58fc89f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Use MemOp for size + endian in aa64 vector ld/st
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c8f638d99aaf8284b9ba81fb49ad6985d109794f
https://github.com/qemu/qemu/commit/c8f638d99aaf8284b9ba81fb49ad6985d109794f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 37abe399df6a8b7006a19f3378715b650599e8fa
https://github.com/qemu/qemu/commit/37abe399df6a8b7006a19f3378715b650599e8fa
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0ca0f8720a424a643d33cce802a4b769fbb62836
https://github.com/qemu/qemu/commit/0ca0f8720a424a643d33cce802a4b769fbb62836
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Enforce alignment for sve LD1R
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: da7e13c00b5962016b9c72079bef5e0a5398db0d
https://github.com/qemu/qemu/commit/da7e13c00b5962016b9c72079bef5e0a5398db0d
Author: Cornelia Huck <cohuck@redhat.com>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M hw/arm/virt.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/i386/pc.h
Log Message:
-----------
hw: add compat machines for 6.1
Add 6.1 machine types for arm/i440fx/q35/s390x/spapr.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Acked-by: Greg Kurz <groug@kaod.org>
Message-id: 20210331111900.118274-1-cohuck@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a6091108aa44e9017af4ca13c43f55a629e3744c
https://github.com/qemu/qemu/commit/a6091108aa44e9017af4ca13c43f55a629e3744c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M hw/core/machine.c
M hw/pci-host/gpex.c
M include/hw/pci-host/gpex.h
Log Message:
-----------
hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
Currently the gpex PCI controller implements no special behaviour for
guest accesses to areas of the PIO and MMIO where it has not mapped
any PCI devices, which means that for Arm you end up with a CPU
exception due to a data abort.
Most host OSes expect "like an x86 PC" behaviour, where bad accesses
like this return -1 for reads and ignore writes. In the interests of
not being surprising, make host CPU accesses to these windows behave
as -1/discard where there's no mapped PCI device.
The old behaviour generally didn't cause any problems, because
almost always the guest OS will map the PCI devices and then only
access where it has mapped them. One corner case where you will see
this kind of access is if Linux attempts to probe legacy ISA
devices via a PIO window access. So far the only case where we've
seen this has been via the syzkaller fuzzer.
Reported-by: Dmitry Vyukov <dvyukov@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20210325163315.27724-1-peter.maydell@linaro.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1918917
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c3811c08ac0c80e9d823317dde07b4c12de67069
https://github.com/qemu/qemu/commit/c3811c08ac0c80e9d823317dde07b4c12de67069
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-04-30 (Fri, 30 Apr 2021)
Changed paths:
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/core/machine.c
M hw/i386/pc.c
M hw/i386/pc_piix.c
M hw/i386/pc_q35.c
M hw/pci-host/gpex.c
M hw/ppc/spapr.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/boards.h
M include/hw/i386/pc.h
M include/hw/pci-host/gpex.h
M target/arm/cpu.h
M target/arm/helper-a64.c
M target/arm/helper-a64.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/mte_helper.c
M target/arm/neon-ls.decode
M target/arm/sve_helper.c
M target/arm/translate-a64.c
M target/arm/translate-a64.h
M target/arm/translate-neon.c.inc
M target/arm/translate-sve.c
M target/arm/translate-vfp.c.inc
M target/arm/translate.c
M target/arm/translate.h
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/mte-5.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210430'
into staging
target-arm queue:
* hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
* hw: add compat machines for 6.1
* Fault misaligned accesses where the architecture requires it
* Fix some corner cases of MTE faults (notably with misaligned accesses)
* Make Thumb store insns UNDEF for Rn==1111
* hw/arm/smmuv3: Support 16K translation granule
# gpg: Signature made Fri 30 Apr 2021 11:33:45 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210430: (43 commits)
hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
hw: add compat machines for 6.1
target/arm: Enforce alignment for sve LD1R
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
target/arm: Use MemOp for size + endian in aa64 vector ld/st
target/arm: Enforce alignment for aa64 load-acq/store-rel
target/arm: Use finalize_memop for aa64 fpr load/store
target/arm: Use finalize_memop for aa64 gpr load/store
target/arm: Enforce alignment for VLDn/VSTn (single)
target/arm: Enforce alignment for VLDn/VSTn (multiple)
target/arm: Enforce alignment for VLDn (all lanes)
target/arm: Enforce alignment for VLDR/VSTR
target/arm: Enforce alignment for VLDM/VSTM
target/arm: Enforce alignment for SRS
target/arm: Enforce alignment for RFE
target/arm: Enforce alignment for LDM/STM
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
target/arm: Enforce word alignment for LDRD/STRD
target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/5351fb7cb2ca...c3811c08ac0c