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[Qemu-commits] [qemu/qemu] af1bb5: osdep: include glib-compat.h before o


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] af1bb5: osdep: include glib-compat.h before other QEMU hea...
Date: Mon, 19 Apr 2021 05:56:25 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: af1bb59c07c889c59cc22322d6eccb678991a299
      
https://github.com/qemu/qemu/commit/af1bb59c07c889c59cc22322d6eccb678991a299
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M include/qemu/osdep.h

  Log Message:
  -----------
  osdep: include glib-compat.h before other QEMU headers

glib-compat.h is sort of like a system header, and it needs to include
system headers (glib.h) that may dislike being included under
'extern "C"'.  Move it right after all system headers and before
all other QEMU headers.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416135543.20382-2-peter.maydell@linaro.org
[PMM: Added comment about why glib-compat.h is special]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 875df03b221ef6a67f175f1f283ea5598f717da5
      
https://github.com/qemu/qemu/commit/875df03b221ef6a67f175f1f283ea5598f717da5
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M disas/arm-a64.cc
    M disas/nanomips.cpp
    M include/qemu/compiler.h
    M include/qemu/osdep.h

  Log Message:
  -----------
  osdep: protect qemu/osdep.h with extern "C"

System headers may include templates if compiled with a C++ compiler,
which cause the compiler to complain if qemu/osdep.h is included
within a C++ source file's 'extern "C"' block.  Add
an 'extern "C"' block directly to qemu/osdep.h, so that
system headers can be kept out of it.

There is a stray declaration early in qemu/osdep.h, which needs
to be special cased.  Add a definition in qemu/compiler.h to
make it look nice.

config-host.h, CONFIG_TARGET, exec/poison.h and qemu/compiler.h
are included outside the 'extern "C"' block; that is not
an issue because they consist entirely of preprocessor directives.

This allows us to move the include of osdep.h in our two C++
source files outside the extern "C" block they were previously
using for it, which in turn means that they compile successfully
against newer versions of glib which insist that glib.h is
*not* inside an extern "C" block.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416135543.20382-3-peter.maydell@linaro.org
[PMM: Moved disas/arm-a64.cc osdep.h include out of its extern "C" block;
 explained in commit message why we're doing this]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: ec63ca2d356f7be018138d7f66b13dffd2396b9f
      
https://github.com/qemu/qemu/commit/ec63ca2d356f7be018138d7f66b13dffd2396b9f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M include/qemu/osdep.h

  Log Message:
  -----------
  include/qemu/osdep.h: Move system includes to top

Mostly osdep.h puts the system includes at the top of the file; but
there are a couple of exceptions where we include a system header
halfway through the file.  Move these up to the top with the rest
so that all the system headers we include are included before
we include os-win32.h or os-posix.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416135543.20382-4-peter.maydell@linaro.org
Message-id: 20210414184343.26235-1-peter.maydell@linaro.org


  Commit: 1df0878cff267128393b0076da4a96467ac04094
      
https://github.com/qemu/qemu/commit/1df0878cff267128393b0076da4a96467ac04094
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M hw/arm/armsse.c

  Log Message:
  -----------
  hw/arm/armsse: Give SSE-300 its own Property array

SSE-300 currently shares the SSE-200 Property array. This is
bad principally because the default values of the CPU0_FPU
and CPU0_DSP properties disable the FPU and DSP on the CPU.
That is correct for the SSE-200 but not the SSE-300.
Give the SSE-300 its own Property array with the correct
SSE-300 specific settings:
 * SSE-300 has only one CPU, so no CPU1* properties
 * SSE-300 CPU has FPU and DSP

Buglink: https://bugs.launchpad.net/qemu/+bug/1923861
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210415182353.8173-1-peter.maydell@linaro.org


  Commit: 330ef14e6e749919c5c70e9fd6f73aaeac8a15ae
      
https://github.com/qemu/qemu/commit/330ef14e6e749919c5c70e9fd6f73aaeac8a15ae
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M hw/arm/armsse.c

  Log Message:
  -----------
  hw/arm/armsse: Make SSE-300 use Cortex-M55

The SSE-300 has a Cortex-M55 (which was the whole reason for us
modelling it), but we forgot to actually update the code to let it
have a different CPU type from the IoTKit and SSE-200.  Add CPU type
as a field for ARMSSEInfo instead of hardcoding it to always use a
Cortex-M33.

Buglink: https://bugs.launchpad.net/qemu/+bug/1923861
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210416104010.13228-1-peter.maydell@linaro.org


  Commit: c57b27ea89ac3ca8a4bc6b682231823f081478d0
      
https://github.com/qemu/qemu/commit/c57b27ea89ac3ca8a4bc6b682231823f081478d0
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: drop CF_LAST_IO/dc->condjump check

This is a left over erroneous check from the days front-ends handled
io start/end themselves. Regardless just because IO could be performed
on the last instruction doesn't obligate the front end to do so.

This fixes an abort faced by the aspeed execute-in-place support which
will necessarily trigger this state (even before the one-shot
CF_LAST_IO fix). The test still seems to hang once it attempts to boot
the Linux kernel but I suspect this is an unrelated issue with icount
and the timer handling code.

The original intention of the cpu_abort (added in commit 2e70f6efa8b9
when the icount stuff was first added) seems to have been to act as
an assert() to catch an unhandled corner case where the generated code
would be something like:
    conditional branch to condlabel if its cc failed
    implementation of the insn (a conditional branch or trap)
    code emitted by gen_io_end()
 condlabel:
    gen_goto_tb or equivalent thing to go to next insn

At runtime the cc-failed case would skip over the code emitted by
gen_io_end(), leaving the can_do_io flag incorrectly set.

In commit ba3e7926691ed33 we switched to an implementation which
always clears can_do_io at the start of the following TB instead
of trying to clear it at the end of a TB that did IO. So the corner
case that this cpu_abort() was trying to flag is no longer possible,
because the gen_io_end() call has been deleted. We can therefore
safely remove the no-longer-valid assertion.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210416170207.12504-1-alex.bennee@linaro.org
Cc: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 277aed998ac2cd3649bf0e13b22f47769519eb61
      
https://github.com/qemu/qemu/commit/277aed998ac2cd3649bf0e13b22f47769519eb61
  Author: Alex Bennée <alex.bennee@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M accel/tcg/translate-all.c

  Log Message:
  -----------
  accel/tcg: avoid re-translating one-shot instructions

By definition a single instruction is capable of being an IO
instruction. This avoids a problem of triggering a cpu_io_recompile on
a non-recorded translation which then fails because it expects
tcg_tb_lookup() to succeed unconditionally. The normal use case
requires a TB to be able to resolve machine state.

The other users of tcg_tb_lookup() are able to tolerate a missing TB
if the machine state has been resolved by other means - which in the
single-shot case is always true because machine state is synced at the
start of a block.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210415162454.22056-1-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0c5393a1349a72013b577dae0e1b8c9a20d277f4
      
https://github.com/qemu/qemu/commit/0c5393a1349a72013b577dae0e1b8c9a20d277f4
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-04-17 (Sat, 17 Apr 2021)

  Changed paths:
    M accel/tcg/translate-all.c
    M disas/arm-a64.cc
    M disas/nanomips.cpp
    M hw/arm/armsse.c
    M include/qemu/compiler.h
    M include/qemu/osdep.h
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210417' 
into staging

Fixes for rc4:
 * Fix compile failures of C++ files with new glib headers
 * mps3-an547: Use correct Cortex-M55 CPU and don't disable its FPU
 * accel/tcg: Fix assertion failure executing from non-RAM with -icount

# gpg: Signature made Sat 17 Apr 2021 20:39:58 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210417:
  accel/tcg: avoid re-translating one-shot instructions
  target/arm: drop CF_LAST_IO/dc->condjump check
  hw/arm/armsse: Make SSE-300 use Cortex-M55
  hw/arm/armsse: Give SSE-300 its own Property array
  include/qemu/osdep.h: Move system includes to top
  osdep: protect qemu/osdep.h with extern "C"
  osdep: include glib-compat.h before other QEMU headers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8fe9f1f891ef...0c5393a1349a



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