[Qemu-commits] [qemu/qemu] a62ee0: net/npcm7xx_emc.c: Fix handling of receiving packe...

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: a62ee00aa063b8fa27076ec5100b2475fcd677ed
      
https://github.com/qemu/qemu/commit/a62ee00aa063b8fa27076ec5100b2475fcd677ed
  Author: Doug Evans <dje@google.com>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M hw/net/npcm7xx_emc.c
    M tests/qtest/npcm7xx_emc-test.c

  Log Message:
  -----------
  net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set

Turning REG_MCMDR_RXON is enough to start receiving packets.

Signed-off-by: Doug Evans <dje@google.com>
Message-id: 20210319195044.741821-1-dje@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c8aaa24537cb87ebe5a2a6a1ea9cfff337e98bb4
      
https://github.com/qemu/qemu/commit/c8aaa24537cb87ebe5a2a6a1ea9cfff337e98bb4
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M hw/display/xlnx_dp.c

  Log Message:
  -----------
  hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()

When building with --enable-sanitizers we get:

  Direct leak of 16 byte(s) in 1 object(s) allocated from:
      #0 0x5618479ec7cf in malloc (qemu-system-aarch64+0x233b7cf)
      #1 0x7f675745f958 in g_malloc (/lib64/libglib-2.0.so.0+0x58958)
      #2 0x561847c2dcc9 in xlnx_dp_init hw/display/xlnx_dp.c:1259:5
      #3 0x56184a5bdab8 in object_init_with_type qom/object.c:375:9
      #4 0x56184a5a2bda in object_initialize_with_type qom/object.c:517:5
      #5 0x56184a5a24d5 in object_initialize qom/object.c:536:5
      #6 0x56184a5a2f6c in object_initialize_child_with_propsv 
qom/object.c:566:5
      #7 0x56184a5a2e60 in object_initialize_child_with_props 
qom/object.c:549:10
      #8 0x56184a5a3a1e in object_initialize_child_internal qom/object.c:603:5
      #9 0x5618495aa431 in xlnx_zynqmp_init hw/arm/xlnx-zynqmp.c:273:5

The RX/TX FIFOs are created in xlnx_dp_init(), add xlnx_dp_finalize()
to destroy them.

Fixes: 58ac482a66d ("introduce xlnx-dp")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210323182958.277654-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6c1bd93954cbdd70d8bdcd67b1f01d759747d895
      
https://github.com/qemu/qemu/commit/6c1bd93954cbdd70d8bdcd67b1f01d759747d895
  Author: Zenghui Yu <yuzenghui@huawei.com>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M hw/arm/smmuv3-internal.h

  Log Message:
  -----------
  hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()

They were introduced in commit 9bde7f0674fe ("hw/arm/smmuv3: Implement
translate callback") but never actually used. Drop them.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210325142702.790-1-yuzenghui@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f
      
https://github.com/qemu/qemu/commit/f7fb73b8cdd3f77e26f9fcff8cf24ff1b58d200f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper.c
    M target/arm/kvm64.c

  Log Message:
  -----------
  target/arm: Make number of counters in PMCR follow the CPU

Currently we give all the v7-and-up CPUs a PMU with 4 counters.  This
means that we don't provide the 6 counters that are required by the
Arm BSA (Base System Architecture) specification if the CPU supports
the Virtualization extensions.

Instead of having a single PMCR_NUM_COUNTERS, make each CPU type
specify the PMCR reset value (obtained from the appropriate TRM), and
use the 'N' field of that value to define the number of counters
provided.

This means that we now supply 6 counters for Cortex-A53, A57, A72,
A15 and A9 as well as '-cpu max'; Cortex-A7 and A8 stay at 4; and
Cortex-R5 goes down to 3.

Note that because we now use the PMCR reset value of the specific
implementation, we no longer set the LC bit out of reset.  This has
an UNKNOWN value out of reset for all cores with any AArch32 support,
so guest software should be setting it anyway if it wants it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20210311165947.27470-1-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1
      
https://github.com/qemu/qemu/commit/b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M hw/timer/renesas_tmr.c

  Log Message:
  -----------
  hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()

In commit 81b3ddaf8772ec we fixed a use of uninitialized data
in read_tcnt(). However this change wasn't enough to placate
Coverity, which is not smart enough to see that if we read a
2 bit field and then handle cases 0, 1, 2 and 3 then there cannot
be a flow of execution through the switch default. Add explicit
default cases which assert that they can't be reached, which
should help silence Coverity.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210319162458.13760-1-peter.maydell@linaro.org


  Commit: b471d5549188d01730131a322c4d154585ba1e60
      
https://github.com/qemu/qemu/commit/b471d5549188d01730131a322c4d154585ba1e60
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-30 (Tue, 30 Mar 2021)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/display/xlnx_dp.c
    M hw/net/npcm7xx_emc.c
    M hw/timer/renesas_tmr.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/cpu_tcg.c
    M target/arm/helper.c
    M target/arm/kvm64.c
    M tests/qtest/npcm7xx_emc-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210330' 
into staging

 * net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
 * hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
 * hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
 * target/arm: Make number of counters in PMCR follow the CPU
 * hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()

# gpg: Signature made Tue 30 Mar 2021 14:23:33 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210330:
  hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
  target/arm: Make number of counters in PMCR follow the CPU
  hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
  hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
  net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/4a0ba67c77a4...b471d5549188