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[Qemu-commits] [qemu/qemu] 5e437d: target/riscv: fix vs() to return prop
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 5e437d: target/riscv: fix vs() to return proper error code |
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Date: |
Tue, 23 Mar 2021 09:49:20 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 5e437d3ccdccfd85f6e69ca60f921be2dab62c3c
https://github.com/qemu/qemu/commit/5e437d3ccdccfd85f6e69ca60f921be2dab62c3c
Author: Frank Chang <frank.chang@sifive.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: fix vs() to return proper error code
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.
If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 82a4ed8e5014ee814c63be33987e6783d5eacce2
https://github.com/qemu/qemu/commit/82a4ed8e5014ee814c63be33987e6783d5eacce2
Author: Alexander Wagner <alexander.wagner@ulal.de>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M hw/char/ibex_uart.c
M include/hw/char/ibex_uart.h
Log Message:
-----------
hw/char: disable ibex uart receive if the buffer is full
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: b297129ae19e26d3cc0e376d2bfc33d76b06d83b
https://github.com/qemu/qemu/commit/b297129ae19e26d3cc0e376d2bfc33d76b06d83b
Author: Jim Shu <cwshu@andestech.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/cpu_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: propagate PMP permission to TLB page
Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.
PMP permission checking also use MMU-style API to change TLB permission
and size.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-2-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 663e119317d77780949830226f5575305405ab75
https://github.com/qemu/qemu/commit/663e119317d77780949830226f5575305405ab75
Author: Jim Shu <cwshu@andestech.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: add log of PMP permission checking
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 2c2e0f2842520bcd25472285cfce39696e52e662
https://github.com/qemu/qemu/commit/2c2e0f2842520bcd25472285cfce39696e52e662
Author: Jim Shu <cwshu@andestech.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: flush TLB pages if PMP permission has been changed
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-4-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 90ec1cff768fcbe1fa2870d2018f378376f4f744
https://github.com/qemu/qemu/commit/90ec1cff768fcbe1fa2870d2018f378376f4f744
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
According to the specification the "field SPVP of hstatus controls the
privilege level of the access" for the hypervisor virtual-machine load
and store instructions HLV, HLVX and HSV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103005.1400718-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: e89b631cf44d590dbd2c250358f4130f64b5d890
https://github.com/qemu/qemu/commit/e89b631cf44d590dbd2c250358f4130f64b5d890
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Make VSTIP and VSEIP read-only in hip
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094902.1377593-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: db9ab38b81058b41e5f469165067feea46762eee
https://github.com/qemu/qemu/commit/db9ab38b81058b41e5f469165067feea46762eee
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Use background registers also for MSTATUS_MPV
The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 0489348d0d31f216e925855f3ac37a6fc666aaaf
https://github.com/qemu/qemu/commit/0489348d0d31f216e925855f3ac37a6fc666aaaf
Author: Asherah Connor <ashe@kivikakk.ee>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M hw/riscv/Kconfig
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv: Add fw_cfg support to virt
Provides fw_cfg for the virt machine on riscv. This enables
using e.g. ramfb later.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-2-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: c346749ee9d75fcb11bb816d0665ce174425d667
https://github.com/qemu/qemu/commit/c346749ee9d75fcb11bb816d0665ce174425d667
Author: Asherah Connor <ashe@kivikakk.ee>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv: allow ramfb on virt
Allow ramfb on virt. This lets `-device ramfb' work.
Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210318235041.17175-3-ashe@kivikakk.ee
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9d5451e077cd84809bcdf460c39b5f4fec17fc79
https://github.com/qemu/qemu/commit/9d5451e077cd84809bcdf460c39b5f4fec17fc79
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix read and write accesses to vsip and vsie
The previous implementation was broken in many ways:
- Used mideleg instead of hideleg to mask accesses
- Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie
- Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...)
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311094738.1376795-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: ec352d0cab58a7bf66019057d0dfcffd9e7785a8
https://github.com/qemu/qemu/commit/ec352d0cab58a7bf66019057d0dfcffd9e7785a8
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Add proper two-stage lookup exception detection
The current two-stage lookup detection in riscv_cpu_do_interrupt falls
short of its purpose, as all it checks is whether two-stage address
translation either via the hypervisor-load store instructions or the
MPRV feature would be allowed.
What we really need instead is whether two-stage address translation was
active when the exception was raised. However, in riscv_cpu_do_interrupt
we do not have the information to reliably detect this. Therefore, when
we raise a memory fault exception we have to record whether two-stage
address translation is active.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210319141459.1196741-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: aac8e46e9da6e6ad048d858ecb033c953753f31a
https://github.com/qemu/qemu/commit/aac8e46e9da6e6ad048d858ecb033c953753f31a
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw/block: m25p80: Support fast read for SST flashes
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d6150ace2bccfee6b5f7bb555ca749739b02f687
https://github.com/qemu/qemu/commit/d6150ace2bccfee6b5f7bb555ca749739b02f687
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
Since HSS commit c20a89f8dcac, the Icicle Kit reference design has
been updated to use a register mapped at 0x4f000000 instead of a
GPIO to control whether eMMC or SD card is to be used. With this
support the same HSS image can be used for both eMMC and SD card
boot flow, while previously two different board configurations were
used. This is undocumented but one can take a look at the HSS code
HSS_MMCInit() in services/mmc/mmc_api.c.
With this commit, HSS image built from 2020.12 release boots again.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: d4e28f0eb8d6f4de42bf7685eb5d3b70407d5e50
https://github.com/qemu/qemu/commit/d4e28f0eb8d6f4de42bf7685eb5d3b70407d5e50
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
A docs/system/riscv/microchip-icicle-kit.rst
M docs/system/target-riscv.rst
Log Message:
-----------
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
This adds the documentation to describe what is supported for the
'microchip-icicle-kit' machine, and how to boot the machine in QEMU.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210322075248.136255-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9a27f69bd668d9d71674407badc412ce1231c7d5
https://github.com/qemu/qemu/commit/9a27f69bd668d9d71674407badc412ce1231c7d5
Author: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: 2021-03-22 (Mon, 22 Mar 2021)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Prevent lost illegal instruction exceptions
When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.
Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b363 anyway.
Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Commit: 9950da284fa5e2ea9ab57d87e05b693fb60c79ce
https://github.com/qemu/qemu/commit/9950da284fa5e2ea9ab57d87e05b693fb60c79ce
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-23 (Tue, 23 Mar 2021)
Changed paths:
A docs/system/riscv/microchip-icicle-kit.rst
M docs/system/target-riscv.rst
M hw/block/m25p80.c
M hw/char/ibex_uart.c
M hw/riscv/Kconfig
M hw/riscv/microchip_pfsoc.c
M hw/riscv/virt.c
M include/hw/char/ibex_uart.h
M include/hw/riscv/microchip_pfsoc.h
M include/hw/riscv/virt.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-to-apply-20210322-2' into staging
RISC-V PR for 6.0
This PR includes:
- Fix for vector CSR access
- Improvements to the Ibex UART device
- PMP improvements and bug fixes
- Hypervisor extension bug fixes
- ramfb support for the virt machine
- Fast read support for SST flash
- Improvements to the microchip_pfsoc machine
# gpg: Signature made Tue 23 Mar 2021 01:56:53 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210322-2:
target/riscv: Prevent lost illegal instruction exceptions
docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine
hw/riscv: microchip_pfsoc: Map EMMC/SD mux register
hw/block: m25p80: Support fast read for SST flashes
target/riscv: Add proper two-stage lookup exception detection
target/riscv: Fix read and write accesses to vsip and vsie
hw/riscv: allow ramfb on virt
hw/riscv: Add fw_cfg support to virt
target/riscv: Use background registers also for MSTATUS_MPV
target/riscv: Make VSTIP and VSEIP read-only in hip
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
target/riscv: flush TLB pages if PMP permission has been changed
target/riscv: add log of PMP permission checking
target/riscv: propagate PMP permission to TLB page
hw/char: disable ibex uart receive if the buffer is full
target/riscv: fix vs() to return proper error code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/97414988490d...9950da284fa5