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[Qemu-commits] [qemu/qemu] 260290: hw/mips/gt64xxx: Initialize ISD I/O m
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 260290: hw/mips/gt64xxx: Initialize ISD I/O memory region ... |
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Date: |
Mon, 15 Mar 2021 08:34:34 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 260290677e62473f1901608cc89c6e919bb77fc6
https://github.com/qemu/qemu/commit/260290677e62473f1901608cc89c6e919bb77fc6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize()
The ISD I/O region belongs to the TYPE_GT64120_PCI_HOST_BRIDGE,
so initialize it before it is realized, not after.
Rename the region as 'gt64120-isd' so it is clearer to realize
it belongs to the GT64120 in the memory tree view.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-2-f4bug@amsat.org>
Commit: 8d492c5f06e107b2f7ebeb66ccb25537cccbf269
https://github.com/qemu/qemu/commit/8d492c5f06e107b2f7ebeb66ccb25537cccbf269
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.
Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-3-f4bug@amsat.org>
Commit: 1c8d4071ee95de26a7f1feff8e94ebc6e12e0b19
https://github.com/qemu/qemu/commit/1c8d4071ee95de26a7f1feff8e94ebc6e12e0b19
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
Log Message:
-----------
hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format
Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug
printf()")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-4-f4bug@amsat.org>
Commit: 1b3422bde22b2cbdee4304369a2a9acfea75515c
https://github.com/qemu/qemu/commit/1b3422bde22b2cbdee4304369a2a9acfea75515c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
M hw/mips/trace-events
Log Message:
-----------
hw/mips/gt64xxx: Rename trace events related to interrupt registers
We want to trace all register accesses. First rename the current
gt64120_read / gt64120_write events with '_intreg' suffix, as they
are restricted to interrupt registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-5-f4bug@amsat.org>
Commit: f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69
https://github.com/qemu/qemu/commit/f8ead0d7bdebd81f4d8457c48f1d003fd4d94c69
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
M hw/mips/trace-events
Log Message:
-----------
hw/mips/gt64xxx: Trace accesses to ISD registers
Trace all accesses to Internal Space Decode (ISD) registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-6-f4bug@amsat.org>
Commit: 2897579982c3d53e3f808bf1e7cdc465ea0ea421
https://github.com/qemu/qemu/commit/2897579982c3d53e3f808bf1e7cdc465ea0ea421
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/meson.build
Log Message:
-----------
target/mips/meson: Introduce mips_tcg source set
Introduce the 'mips_tcg' source set to collect TCG specific files.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-2-f4bug@amsat.org>
Commit: 21fb03be67fa63670796f7b5d7bcd1194e6a8154
https://github.com/qemu/qemu/commit/21fb03be67fa63670796f7b5d7bcd1194e6a8154
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/meson.build
Log Message:
-----------
target/mips/meson: Restrict mips-semi.c to TCG
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-3-f4bug@amsat.org>
Commit: 4f57f43cb8c2402d5ca552eafac438ea14d584df
https://github.com/qemu/qemu/commit/4f57f43cb8c2402d5ca552eafac438ea14d584df
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Rewrite complex ifdef'ry
No need for this obfuscated ifdef'ry, KISS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-4-f4bug@amsat.org>
Commit: 2090713f650b4832b9661cdcdf193f3602d0e0c0
https://github.com/qemu/qemu/commit/2090713f650b4832b9661cdcdf193f3602d0e0c0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove XBurst Media eXtension Unit dead code
All these unimplemented MXU opcodes end up calling
gen_reserved_instruction() which is the default switch
case in decode_opc_mxu().
The translate.c file is already big enough and hard to maintain,
remove 1300 lines of unnecessary code and /* TODO */ comments.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-5-f4bug@amsat.org>
Commit: 21d66ead6a7577ad7d6699a4ff99d231a5cfa0b0
https://github.com/qemu/qemu/commit/21d66ead6a7577ad7d6699a4ff99d231a5cfa0b0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove unused CPUMIPSState* from MXU functions
None of these MXU functions use their CPUMIPSState* env argument,
remove it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-6-f4bug@amsat.org>
Commit: 965eb74bb597d4f43dbefa85244891d67634a818
https://github.com/qemu/qemu/commit/965eb74bb597d4f43dbefa85244891d67634a818
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Pass instruction opcode to decode_opc_mxu()
In the next commit we'll make decode_opc_mxu() match decodetree
prototype by returning a boolean. First pass ctx->opcode as an
argument.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-7-f4bug@amsat.org>
Commit: de5af7c5e64addc0eb89cde3cc6b0ece0225a73e
https://github.com/qemu/qemu/commit/de5af7c5e64addc0eb89cde3cc6b0ece0225a73e
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
We already have a macro and definition to extract / check
the Special2 MUL opcode. Use it instead of the unnecessary
OPC__MXU_MUL macro.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-8-f4bug@amsat.org>
Commit: 2234528618e49d27b85fab4389f393de0fe8ca98
https://github.com/qemu/qemu/commit/2234528618e49d27b85fab4389f393de0fe8ca98
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
Move the check for MUL opcode from decode_opc_mxu() callee
to decode_opc_legacy() caller, so we can simplify the ifdef'ry
and elide the call in few commits.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-9-f4bug@amsat.org>
Commit: e31b43ec507ba35a804f6323d94522c5a2e5581a
https://github.com/qemu/qemu/commit/e31b43ec507ba35a804f6323d94522c5a2e5581a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
Use "decode_{isa,ase,ext}_$name()" function name pattern for
public decodetree entrypoints.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-10-f4bug@amsat.org>
Commit: a8dad35388987fe3d55d6166d7f3f188eb607e97
https://github.com/qemu/qemu/commit/a8dad35388987fe3d55d6166d7f3f188eb607e97
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Convert decode_ase_mxu() to decodetree prototype
To easily convert MXU code to decodetree, making it return a boolean.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-11-f4bug@amsat.org>
Commit: c7abe00ae9336892ae615fbc39157ba110d1716b
https://github.com/qemu/qemu/commit/c7abe00ae9336892ae615fbc39157ba110d1716b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Simplify decode_opc_mxu() ifdef'ry
By making the prototype public and checking
'TARGET_LONG_BITS == 32' we let the compiler
elide the decode_opc_mxu() call.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-12-f4bug@amsat.org>
Commit: fe35ea94838d8faba749ecfd49256f59e5fe0653
https://github.com/qemu/qemu/commit/fe35ea94838d8faba749ecfd49256f59e5fe0653
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce mxu_translate_init() helper
Extract the MXU register initialization code from mips_tcg_init()
as a new mxu_translate_init() helper. Make it public and replace
!TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to
elide this code at preprocessing time.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-13-f4bug@amsat.org>
Commit: b24db6fcd4063db6d001e958b28bfc2dadb249d9
https://github.com/qemu/qemu/commit/b24db6fcd4063db6d001e958b28bfc2dadb249d9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/meson.build
A target/mips/mxu_translate.c
M target/mips/translate.c
Log Message:
-----------
target/mips: Extract MXU code to new mxu_translate.c file
Extract 1600+ lines from the big translate.c into a new file.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210226093111.3865906-14-f4bug@amsat.org>
Commit: c27b4579371e5d8eaed54182243ece54c752a4e5
https://github.com/qemu/qemu/commit/c27b4579371e5d8eaed54182243ece54c752a4e5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Use gen_load_gpr[_hi]() when possible
Use gen_load_gpr[_hi]() instead of open coding it.
Patch generated using the following spatch script:
@gen_load_gpr@
identifier reg_idx;
expression tcg_reg;
@@
-if (reg_idx == 0) {
- tcg_gen_movi_tl(tcg_reg, 0);
-} else {
- tcg_gen_mov_tl(tcg_reg, cpu_gpr[reg_idx]);
-}
+gen_load_gpr(tcg_reg, reg_idx);
@gen_load_gpr_hi@
identifier reg_idx;
expression tcg_reg;
@@
-if (reg_idx == 0) {
- tcg_gen_movi_i64(tcg_reg, 0);
-} else {
- tcg_gen_mov_i64(tcg_reg, cpu_gpr_hi[reg_idx]);
-}
+gen_load_gpr_hi(tcg_reg, reg_idx);
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210308131604.460693-1-f4bug@amsat.org>
Commit: ffc672aa977131ccfccfd0c2aee2b004adb69ed5
https://github.com/qemu/qemu/commit/ffc672aa977131ccfccfd0c2aee2b004adb69ed5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/meson.build
M target/mips/translate.c
M target/mips/translate.h
A target/mips/tx79.decode
A target/mips/tx79_translate.c
A target/mips/txx9_translate.c
Log Message:
-----------
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
Introduce decodetree structure to decode the tx79 opcodes.
Start it by moving the existing MFHI1 and MFLO1 opcodes.
Remove unnecessary comments.
As the TX79 share opcodes with the TX19/TX39/TX49 CPUs,
we introduce the decode_ext_txx9() dispatcher where we
will add the other decoders later.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
Commit: 1f9408d5502c877ddf91ce00f529488c4b5c98d5
https://github.com/qemu/qemu/commit/1f9408d5502c877ddf91ce00f529488c4b5c98d5
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/tx79.decode
M target/mips/tx79_translate.c
Log Message:
-----------
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
Commit: f9fa53f19786c82cab2e7ca0274d6d9f9bb59f4f
https://github.com/qemu/qemu/commit/f9fa53f19786c82cab2e7ca0274d6d9f9bb59f4f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips/translate: Make gen_rdhwr() public
We will use gen_rdhwr() outside of translate.c, make it public.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-28-f4bug@amsat.org>
Commit: ca8def9bdbf3e62ef0afd9e02a51ef536019791a
https://github.com/qemu/qemu/commit/ca8def9bdbf3e62ef0afd9e02a51ef536019791a
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips/translate: Simplify PCPYH using deposit_i64()
Simplify the PCPYH (Parallel Copy Halfword) instruction by using
multiple calls to deposit_i64() which can be optimized by some
TCG backends.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-11-f4bug@amsat.org>
Commit: 5a976c002518d46a030f125e2170d78204528497
https://github.com/qemu/qemu/commit/5a976c002518d46a030f125e2170d78204528497
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/tx79.decode
M target/mips/tx79_translate.c
Log Message:
-----------
target/mips/tx79: Move PCPYH opcode to decodetree
Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree.
Remove unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
Commit: 94c882f7d159c6f412b1778cd71d58d9e39b8ef9
https://github.com/qemu/qemu/commit/94c882f7d159c6f412b1778cd71d58d9e39b8ef9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/tx79.decode
M target/mips/tx79_translate.c
Log Message:
-----------
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
Commit: e71d0f56cedfeebe8adbf5a4fa4e84b2e2de3fdf
https://github.com/qemu/qemu/commit/e71d0f56cedfeebe8adbf5a4fa4e84b2e2de3fdf
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Remove 'C790 Multimedia Instructions' dead code
We have almost 400 lines of code full of /* TODO */ comments
which end calling gen_reserved_instruction().
As we are not going to implement them, and all the caller's
switch() default cases already call gen_reserved_instruction(),
we can remove this altogether.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-14-f4bug@amsat.org>
Commit: d27fadddc673dd85a34102342b43be23d27eaab6
https://github.com/qemu/qemu/commit/d27fadddc673dd85a34102342b43be23d27eaab6
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-13 (Sat, 13 Mar 2021)
Changed paths:
M target/mips/translate.c
M target/mips/tx79_translate.c
Log Message:
-----------
target/mips/tx79: Salvage instructions description comment
This comment describing the tx79 opcodes is helpful. As we
will implement these instructions in tx79_translate.c, move
the comment there.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-15-f4bug@amsat.org>
Commit: 36d840f35b4fc7e2d47fb54313950f82690b2286
https://github.com/qemu/qemu/commit/36d840f35b4fc7e2d47fb54313950f82690b2286
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-14 (Sun, 14 Mar 2021)
Changed paths:
M hw/mips/gt64xxx_pci.c
M hw/mips/trace-events
M target/mips/meson.build
A target/mips/mxu_translate.c
M target/mips/translate.c
M target/mips/translate.h
A target/mips/tx79.decode
A target/mips/tx79_translate.c
A target/mips/txx9_translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into staging
MIPS patches queue
- Tidy up the GT64120 north bridge
- Move XBurst Media eXtension Unit code to mxu_translate.c
- Convert TX79 to decodetree
# gpg: Signature made Sat 13 Mar 2021 22:44:44 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd/tags/mips-20210313: (27 commits)
target/mips/tx79: Salvage instructions description comment
target/mips: Remove 'C790 Multimedia Instructions' dead code
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree
target/mips/tx79: Move PCPYH opcode to decodetree
target/mips/translate: Simplify PCPYH using deposit_i64()
target/mips/translate: Make gen_rdhwr() public
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree
target/mips: Use gen_load_gpr[_hi]() when possible
target/mips: Extract MXU code to new mxu_translate.c file
target/mips: Introduce mxu_translate_init() helper
target/mips: Simplify decode_opc_mxu() ifdef'ry
target/mips: Convert decode_ase_mxu() to decodetree prototype
target/mips: Rename decode_opc_mxu() as decode_ase_mxu()
target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()
target/mips: Use OPC_MUL instead of OPC__MXU_MUL
target/mips: Pass instruction opcode to decode_opc_mxu()
target/mips: Remove unused CPUMIPSState* from MXU functions
target/mips: Remove XBurst Media eXtension Unit dead code
target/mips: Rewrite complex ifdef'ry
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/6157b0e19721...36d840f35b4f