[Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the X

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the X

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the XRAM controller
Date:	Sun, 14 Mar 2021 04:38:45 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 9f61763574fb19525a68c46f3b8f763e5936a6fe
      
https://github.com/qemu/qemu/commit/9f61763574fb19525a68c46f3b8f763e5936a6fe
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/xlnx-versal-xramc.c
    A include/hw/misc/xlnx-versal-xramc.h

  Log Message:
  -----------
  hw/misc: versal: Add a model of the XRAM controller

Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210308224637.2949533-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a55b441b2ca578417ab3a7a62129cd801e22abf4
      
https://github.com/qemu/qemu/commit/a55b441b2ca578417ab3a7a62129cd801e22abf4
  Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M docs/system/arm/xlnx-versal-virt.rst
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm: versal: Add support for the XRAMs

Connect the support for the Versal Accelerator RAMs (XRAMs).

Reviewed-by: Luc Michel <luc@lmichel.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210308224637.2949533-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 41ce9a912641cd7f820bcfccea15e30efc32104e
      
https://github.com/qemu/qemu/commit/41ce9a912641cd7f820bcfccea15e30efc32104e
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/i386/intel_iommu.c

  Log Message:
  -----------
  intel_iommu: Fix mask may be uninitialized in vtd_context_device_invalidate

With -Werror=maybe-uninitialized configuration we get
../hw/i386/intel_iommu.c: In function ‘vtd_context_device_invalidate’:
../hw/i386/intel_iommu.c:1888:10: error: ‘mask’ may be used
uninitialized in this function [-Werror=maybe-uninitialized]
 1888 |     mask = ~mask;
      |     ~~~~~^~~~~~~

Add a g_assert_not_reached() to avoid the error.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210309102742.30442-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f14fb6c2db961c3665a61b342ab329b7bd20d1e7
      
https://github.com/qemu/qemu/commit/f14fb6c2db961c3665a61b342ab329b7bd20d1e7
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/i386/intel_iommu.c
    M include/sysemu/dma.h
    M softmmu/dma-helpers.c

  Log Message:
  -----------
  dma: Introduce dma_aligned_pow2_mask()

Currently get_naturally_aligned_size() is used by the intel iommu
to compute the maximum invalidation range based on @size which is
a power of 2 while being aligned with the @start address and less
than the maximum range defined by @gaw.

This helper is also useful for other iommu devices (virtio-iommu,
SMMUv3) to make sure IOMMU UNMAP notifiers only are called with
power of 2 range sizes.

Let's move this latter into dma-helpers.c and rename it into
dma_aligned_pow2_mask(). Also rewrite the helper so that it
accomodates UINT64_MAX values for the size mask and max mask.
It now returns a mask instead of a size. Change the caller.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 20210309102742.30442-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: dde3f08b5cab24e570fc0ccbbbab86b6b50aad23
      
https://github.com/qemu/qemu/commit/dde3f08b5cab24e570fc0ccbbbab86b6b50aad23
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/virtio/virtio-iommu.c

  Log Message:
  -----------
  virtio-iommu: Handle non power of 2 range invalidations

Unmap notifiers work with an address mask assuming an
invalidation range of a power of 2. Nothing mandates this
in the VIRTIO-IOMMU spec.

So in case the range is not a power of 2, split it into
several invalidations.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-id: 20210309102742.30442-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a4b6e1be2c8fd60381feb00f06cf3b6373bbbf07
      
https://github.com/qemu/qemu/commit/a4b6e1be2c8fd60381feb00f06cf3b6373bbbf07
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/smmu-common.c

  Log Message:
  -----------
  hw/arm/smmu-common: Fix smmu_iotlb_inv_iova when asid is not set

If the asid is not set, do not attempt to locate the key directly
as all inserted keys have a valid asid.

Use g_hash_table_foreach_remove instead.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210309102742.30442-5-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6d9cd115b9dfee08faef0f64c3b90ac5c79ededc
      
https://github.com/qemu/qemu/commit/6d9cd115b9dfee08faef0f64c3b90ac5c79ededc
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Enforce invalidation on a power of two range

As of today, the driver can invalidate a number of pages that is
not a power of 2. However IOTLB unmap notifications and internal
IOTLB invalidations work with masks leading to erroneous
invalidations.

In case the range is not a power of 2, split invalidations into
power of 2 invalidations.

When looking for a single page entry in the vSMMU internal IOTLB,
let's make sure that if the entry is not found using a
g_hash_table_remove() we iterate over all the entries to find a
potential range that overlaps it.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210309102742.30442-6-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1194140b7fab588b4b9de9aeacbe9672f06c1d8f
      
https://github.com/qemu/qemu/commit/1194140b7fab588b4b9de9aeacbe9672f06c1d8f
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/smmu-internal.h
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Fix SMMU_CMD_CFGI_STE_RANGE handling

If the whole SID range (32b) is invalidated (SMMU_CMD_CFGI_ALL),
@end overflows and we fail to handle the command properly.

Once this gets fixed, the current code really is awkward in the
sense it loops over the whole range instead of removing the
currently cached configs through a hash table lookup.

Fix both the overflow and the lookup.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210309102742.30442-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fe2f5cbcfc96f1db3e1a277233f52e2fd993a9e1
      
https://github.com/qemu/qemu/commit/fe2f5cbcfc96f1db3e1a277233f52e2fd993a9e1
  Author: Eric Auger <eric.auger@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Uniformize sid traces

Convert all sid printouts to sid=0x%x.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20210309102742.30442-8-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 226e6c046c0fce8da32575aad020ca56a5a8064d
      
https://github.com/qemu/qemu/commit/226e6c046c0fce8da32575aad020ca56a5a8064d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c

  Log Message:
  -----------
  target/arm: Fix sve_uzp_p vs odd vector lengths

Missed out on compressing the second half of a predicate
with length vl % 512 > 256.

Adjust all of the x + (y << s) to x | (y << s) as a
general style fix.  Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8e7fefed1bdcc0f7e722ccf2a2fc2b4f79fe725e
      
https://github.com/qemu/qemu/commit/8e7fefed1bdcc0f7e722ccf2a2fc2b4f79fe725e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c

  Log Message:
  -----------
  target/arm: Fix sve_zip_p vs odd vector lengths

Wrote too much with low-half zip (zip1) with vl % 512 != 0.

Adjust all of the x + (y << s) to x | (y << s) as a style fix.

We only ever have exact overlap between D, M, and N.  Therefore
we only need a single temporary, and we do not need to check for
partial overlap.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fd911a21414b5a17663fa2b97f1059fb11cee99d
      
https://github.com/qemu/qemu/commit/fd911a21414b5a17663fa2b97f1059fb11cee99d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c

  Log Message:
  -----------
  target/arm: Fix sve_punpk_p vs odd vector lengths

Wrote too much with punpk1 with vl % 512 != 0.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2acbfbe4313daf43b6653ee5d82bcaeaa155e895
      
https://github.com/qemu/qemu/commit/2acbfbe4313daf43b6653ee5d82bcaeaa155e895
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Update find_last_active for PREDDESC

Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 04c774a25da78eb07d505ee5923167c2010b9f8c
      
https://github.com/qemu/qemu/commit/04c774a25da78eb07d505ee5923167c2010b9f8c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Update BRKA, BRKB, BRKN for PREDDESC

Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f556a201b5bbeb59841b37247969fcfc1ab7bd5d
      
https://github.com/qemu/qemu/commit/f556a201b5bbeb59841b37247969fcfc1ab7bd5d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Update CNTP for PREDDESC

Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-7-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e610906c56f98c76888d45beb7f579935dd61a70
      
https://github.com/qemu/qemu/commit/e610906c56f98c76888d45beb7f579935dd61a70
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Update WHILE for PREDDESC

Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c648c9b7e1ccff94b51ecbebe86a206952c47e75
      
https://github.com/qemu/qemu/commit/c648c9b7e1ccff94b51ecbebe86a206952c47e75
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Update sve reduction vs simd_desc

With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that are
not themselves a power of 2.

Pass the power-of-two value in the simd_data field instead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: b6f03acc8fe205a11e7040830f63113b7282538d
      
https://github.com/qemu/qemu/commit/b6f03acc8fe205a11e7040830f63113b7282538d
  Author: Niek Linnenbank <nieklinnenbank@gmail.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/net/allwinner-sun8i-emac.c

  Log Message:
  -----------
  hw/net/allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC 
register value

Currently the emulated EMAC for sun8i always traverses the transmit queue
from the head when transferring packets. It searches for a list of consecutive
descriptors whichs are flagged as ready for processing and transmits their 
payloads
accordingly. The controller stops processing once it finds a descriptor that is 
not
marked ready.

While the above behaviour works in most situations, it is not the same as the 
actual
EMAC in hardware. Actual hardware uses the TX_CUR_DESC register value to keep 
track
of the last position in the transmit queue and continues processing from that 
position
when software triggers the start of DMA processing. The currently emulated 
behaviour can
lead to packet loss on transmit when software fills the transmit queue with 
ready
descriptors that overlap the tail of the circular list.

This commit modifies the emulated EMAC for sun8i such that it processes
the transmit queue using the TX_CUR_DESC register in the same way as hardware.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210310195820.21950-2-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a30e114f3c41871753856e19abf6a7e0715e81c1
      
https://github.com/qemu/qemu/commit/a30e114f3c41871753856e19abf6a7e0715e81c1
  Author: Niek Linnenbank <nieklinnenbank@gmail.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/acceptance/boot_linux_console: remove Armbian 19.11.3 bionic test for 
orangepi-pc machine

The image for Armbian 19.11.3 bionic has been removed from the armbian server.
Without the image as input the test arm_orangepi_bionic_19_11 cannot run.

This commit removes the test completely and merges the code of the generic 
function
do_test_arm_orangepi_uboot_armbian back with the 20.08 test.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id: 20210310195820.21950-3-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 875ee4179bea17bdb92798a060a9f2faef0dc7a2
      
https://github.com/qemu/qemu/commit/875ee4179bea17bdb92798a060a9f2faef0dc7a2
  Author: Niek Linnenbank <nieklinnenbank@gmail.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py

  Log Message:
  -----------
  tests/acceptance/boot_linux_console: change URL for 
test_arm_orangepi_bionic_20_08

Update the download URL of the Armbian 20.08 Bionic image for
test_arm_orangepi_bionic_20_08 of the orangepi-pc machine.

The archive.armbian.com URL contains more images and should keep stable
for a longer period of time than dl.armbian.com.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id: 20210310195820.21950-4-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: e384db41d8661ff570c2e31a4aa09b2f028b3987
      
https://github.com/qemu/qemu/commit/e384db41d8661ff570c2e31a4aa09b2f028b3987
  Author: Niek Linnenbank <nieklinnenbank@gmail.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py
    M tests/acceptance/replay_kernel.py

  Log Message:
  -----------
  tests/acceptance: update sunxi kernel from armbian to 5.10.16

The linux kernel 4.20.7 binary for sunxi has been removed from apt.armbian.com:

  $ ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado 
--show=app,console run -t machine:orangepi-pc 
tests/acceptance/boot_linux_console.py
  Fetching asset from 
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi
  ...
  (1/6) 
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
    CANCEL: Missing asset 
https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb
 (0.55 s)

This commit updates the sunxi kernel to 5.10.16 for the acceptance
tests of the orangepi-pc and cubieboard machines.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id: 20210310195820.21950-5-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f4223d2e75a991c80393ac3c684b90c875d6efd9
      
https://github.com/qemu/qemu/commit/f4223d2e75a991c80393ac3c684b90c875d6efd9
  Author: Niek Linnenbank <nieklinnenbank@gmail.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M tests/acceptance/boot_linux_console.py
    M tests/acceptance/replay_kernel.py

  Log Message:
  -----------
  tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, 
cubieboard tests

Previously the ARMBIAN_ARTIFACTS_CACHED pre-condition was added to allow running
tests that have already existing armbian.com artifacts stored in the local 
avocado cache,
but do not have working URLs to download a fresh copy.

At this time of writing the URLs for artifacts on the armbian.com server are 
updated and working.
Any future broken URLs will result in a skipped acceptance test, for example:

 (1/5) 
tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
  CANCEL: Missing asset 
https://apt.armbian.com/pool/main/l/linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.deb
 (0.53 s)

This commits removes the ARMBIAN_ARTIFACTS_CACHED pre-condition such that
the acceptance tests for the orangepi-pc and cubieboard machines can run.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Message-id: 20210310195820.21950-6-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc49b77fd391fdcfc9c0b61a8c301ac0d15232e9
      
https://github.com/qemu/qemu/commit/fc49b77fd391fdcfc9c0b61a8c301ac0d15232e9
  Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/timer/sse-timer.c

  Log Message:
  -----------
  hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()

If the SSECounter link is absent, we set an error message
in sse_timer_realize() but forgot to propagate this error.
Add the missing 'return'.

Fixes: CID 1450755 (Null pointer dereferences)
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210312001845.1562670-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 516fc0a081161eab5b3a89c7f243954945ee390e
      
https://github.com/qemu/qemu/commit/516fc0a081161eab5b3a89c7f243954945ee390e
  Author: Andrew Jones <drjones@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M accel/kvm/kvm-all.c
    M include/hw/boards.h

  Log Message:
  -----------
  accel: kvm: Fix kvm_type invocation

Prior to commit f2ce39b4f067 a MachineClass kvm_type method
only needed to be registered to ensure it would be executed.
With commit f2ce39b4f067 a kvm-type machine property must also
be specified. hw/arm/virt relies on the kvm_type method to pass
its selected IPA limit to KVM, but this is not exposed as a
machine property. Restore the previous functionality of invoking
kvm_type when it's present.

Fixes: f2ce39b4f067 ("vl: make qemu_get_machine_opts static")
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210310135218.255205-2-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: bcb902a1ed1ad5e0ceebb9536f392bf6d46219f9
      
https://github.com/qemu/qemu/commit/bcb902a1ed1ad5e0ceebb9536f392bf6d46219f9
  Author: Andrew Jones <drjones@redhat.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/virt.c
    M target/arm/kvm.c
    M target/arm/kvm_arm.h

  Log Message:
  -----------
  hw/arm/virt: KVM: The IPA lower bound is 32

The virt machine already checks KVM_CAP_ARM_VM_IPA_SIZE to get the
upper bound of the IPA size. If that bound is lower than the highest
possible GPA for the machine, then QEMU will error out. However, the
IPA is set to 40 when the highest GPA is less than or equal to 40,
even when KVM may support an IPA limit as low as 32. This means KVM
may fail the VM creation unnecessarily. Additionally, 40 is selected
with the value 0, which means use the default, and that gets around
a check in some versions of KVM, causing a difficult to debug fail.
Always use the IPA size that corresponds to the highest possible GPA,
unless it's lower than 32, in which case use 32. Also, we must still
use 0 when KVM only supports the legacy fixed 40 bit IPA.

Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Message-id: 20210310135218.255205-3-drjones@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 71b50b9d1ca2f5e8ae65678294ceacbd7b6520c8
      
https://github.com/qemu/qemu/commit/71b50b9d1ca2f5e8ae65678294ceacbd7b6520c8
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/misc/npcm7xx_pwm.c
    M include/hw/misc/npcm7xx_pwm.h

  Log Message:
  -----------
  hw/misc: Add GPIOs for duty in NPCM7xx PWM

This patch adds GPIOs in NPCM7xx PWM module for its duty values.
The purpose of this is to connect it to the MFT module to provide
an input for measuring a PWM fan's RPM. Each PWM module has
NPCM7XX_PWM_PER_MODULE of GPIOs, each one corresponds to
one PWM instance and can connect to multiple fan instances in MFT.

Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210311180855.149764-2-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 380a37e49891f8d9462124f593516a9ced58343a
      
https://github.com/qemu/qemu/commit/380a37e49891f8d9462124f593516a9ced58343a
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/misc/meson.build
    A hw/misc/npcm7xx_mft.c
    M hw/misc/trace-events
    A include/hw/misc/npcm7xx_mft.h

  Log Message:
  -----------
  hw/misc: Add NPCM7XX MFT Module

This patch implements Multi Function Timer (MFT) module for NPCM7XX.
This module is mainly used to configure PWM fans. It has just enough
functionality to make the PWM fan kernel module work.

The module takes two input, the max_rpm of a fan (modifiable via QMP)
and duty cycle (a GPIO from the PWM module.) The actual measured RPM
is equal to max_rpm * duty_cycle / NPCM7XX_PWM_MAX_DUTY. The RPM is
measured as a counter compared to a prescaled input clock. The kernel
driver reads this counter and report to user space.

Refs:
https://github.com/torvalds/linux/blob/master/drivers/hwmon/npcm750-pwm-fan.c

Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210311180855.149764-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: fc11115f74b4355b38eeebc118e347cd74f35845
      
https://github.com/qemu/qemu/commit/fc11115f74b4355b38eeebc118e347cd74f35845
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M docs/system/arm/nuvoton.rst
    M hw/arm/npcm7xx.c
    M include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm: Add MFT device to NPCM7xx Soc

This patch adds the recently implemented MFT device to the NPCM7XX
SoC file.

Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Message-id: 20210311180855.149764-4-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a9d3d7b17e5a3c246ecf4e420d2d4bb089a8d7c3
      
https://github.com/qemu/qemu/commit/a9d3d7b17e5a3c246ecf4e420d2d4bb089a8d7c3
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/arm/npcm7xx_boards.c
    M include/hw/arm/npcm7xx.h

  Log Message:
  -----------
  hw/arm: Connect PWM fans in NPCM7XX boards

This patch adds fan_splitters (split IRQs) in NPCM7XX boards. Each fan
splitter corresponds to 1 PWM output and can connect to multiple fan
inputs (MFT devices).
In NPCM7XX boards(NPCM750 EVB and Quanta GSJ boards), we initializes
these splitters and connect them to their corresponding modules
according their specific device trees.

Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210311180855.149764-5-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f68c886b525959c86166f20a2ef4797c321399e7
      
https://github.com/qemu/qemu/commit/f68c886b525959c86166f20a2ef4797c321399e7
  Author: Hao Wu <wuhaotsh@google.com>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M tests/qtest/npcm7xx_pwm-test.c

  Log Message:
  -----------
  tests/qtest: Test PWM fan RPM using MFT in PWM test

This patch adds testing of PWM fan RPMs in the existing npcm7xx pwm
test. It tests whether the MFT module can measure correct fan values
for a PWM fan in NPCM7XX boards.

Reviewed-by: Doug Evans <dje@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210311180855.149764-6-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4e46bb8f06586ad41c2fe26e2d4070b8ba44aac5
      
https://github.com/qemu/qemu/commit/4e46bb8f06586ad41c2fe26e2d4070b8ba44aac5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pl110.c

  Log Message:
  -----------
  hw/display/pl110: Remove dead code for non-32-bpp surfaces

For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel. Remove the legacy dead
code from the pl110 display device which was handling the
possibility that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-2-peter.maydell@linaro.org


  Commit: 7cbd685f4a086f441aaa727d49f931631dada461
      
https://github.com/qemu/qemu/commit/7cbd685f4a086f441aaa727d49f931631dada461
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pl110.c
    M hw/display/pl110_template.h

  Log Message:
  -----------
  hw/display/pl110: Pull included-once parts of template header into pl110.c

The pl110_template.h header has a doubly-nested multiple-include pattern:
 * pl110.c includes it once for each host bit depth (now always 32)
 * every time it is included, it includes itself 6 times, to account
   for multiple guest device pixel and byte orders

Now we only have to deal with 32-bit host bit depths, we can move the
code corresponding to the outer layer of this double-nesting to be
directly in pl110.c and reduce the template header to a single layer
of nesting.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-3-peter.maydell@linaro.org


  Commit: 971226f4f4e4091cefa071adcefee0b599cccbf2
      
https://github.com/qemu/qemu/commit/971226f4f4e4091cefa071adcefee0b599cccbf2
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pl110.c
    M hw/display/pl110_template.h

  Log Message:
  -----------
  hw/display/pl110: Remove use of BITS from pl110_template.h

BITS is always 32, so remove all uses of it from the template header,
by dropping the trailing '32' from the draw function names and
not constructing the name of rgb_to_pixel32() via the glue() macro.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-4-peter.maydell@linaro.org


  Commit: 68769c02abd42e09eba0e2c04992afeb94c2c6de
      
https://github.com/qemu/qemu/commit/68769c02abd42e09eba0e2c04992afeb94c2c6de
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_lcd.c

  Log Message:
  -----------
  hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces

For a long time now the UI layer has guaranteed that the console
surface is always 32 bits per pixel.  Remove the legacy dead code
from the pxa2xx_lcd display device which was handling the possibility
that the console surface was some other format.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-5-peter.maydell@linaro.org


  Commit: 9379e406a56db1cf1c73abfac10e75a8356e1f6a
      
https://github.com/qemu/qemu/commit/9379e406a56db1cf1c73abfac10e75a8356e1f6a
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_lcd.c

  Log Message:
  -----------
  hw/display/pxa2xx_lcd: Remove dest_width state field

Since the dest_width is now always 4 because the output surface is
32bpp, we can replace the dest_width state field with a constant.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-6-peter.maydell@linaro.org


  Commit: efdedd8c5a54b43b52a098405c26d94a57dac9f5
      
https://github.com/qemu/qemu/commit/efdedd8c5a54b43b52a098405c26d94a57dac9f5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_template.h

  Log Message:
  -----------
  hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h

Now that BITS is always 32, expand out all its uses in the template
header, including removing now-useless uses of the glue() macro.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-7-peter.maydell@linaro.org


  Commit: b8a2eb9402f54b2af964420fd6178b89ea20f78c
      
https://github.com/qemu/qemu/commit/b8a2eb9402f54b2af964420fd6178b89ea20f78c
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_template.h

  Log Message:
  -----------
  hw/display/pxa2xx: Apply brace-related coding style fixes to template header

We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit fixes
missing braces in the SKIP_PIXEL() macro definition and in if()
statements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-8-peter.maydell@linaro.org


  Commit: dcdeaaeda48c1540e8f2ede210433ad636ecd663
      
https://github.com/qemu/qemu/commit/dcdeaaeda48c1540e8f2ede210433ad636ecd663
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_template.h

  Log Message:
  -----------
  hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header

We're about to move code from the template header into pxa2xx_lcd.c.
Before doing that, make coding style fixes so checkpatch doesn't
complain about the patch which moves the code. This commit is
whitespace changes only:
 * avoid hard-coded tabs
 * fix ident on function prototypes
 * no newline before open brace on array definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-9-peter.maydell@linaro.org


  Commit: 41f09f2e9f09e4dd386d84174a6dcb5136af17ca
      
https://github.com/qemu/qemu/commit/41f09f2e9f09e4dd386d84174a6dcb5136af17ca
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M hw/display/pxa2xx_lcd.c
    R hw/display/pxa2xx_template.h

  Log Message:
  -----------
  hw/display/pxa2xx: Inline template header

The template header is now included only once; just inline its contents
in hw/display/pxa2xx_lcd.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20210211141515.8755-10-peter.maydell@linaro.org


  Commit: 9a954a4a62a7aee13422591408e0d10481c0966f
      
https://github.com/qemu/qemu/commit/9a954a4a62a7aee13422591408e0d10481c0966f
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-14 (Sun, 14 Mar 2021)

  Changed paths:
    M accel/kvm/kvm-all.c
    M docs/system/arm/nuvoton.rst
    M docs/system/arm/xlnx-versal-virt.rst
    M hw/arm/npcm7xx.c
    M hw/arm/npcm7xx_boards.c
    M hw/arm/smmu-common.c
    M hw/arm/smmu-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M hw/arm/virt.c
    M hw/arm/xlnx-versal.c
    M hw/display/pl110.c
    M hw/display/pl110_template.h
    M hw/display/pxa2xx_lcd.c
    R hw/display/pxa2xx_template.h
    M hw/i386/intel_iommu.c
    M hw/misc/meson.build
    A hw/misc/npcm7xx_mft.c
    M hw/misc/npcm7xx_pwm.c
    M hw/misc/trace-events
    A hw/misc/xlnx-versal-xramc.c
    M hw/net/allwinner-sun8i-emac.c
    M hw/timer/sse-timer.c
    M hw/virtio/virtio-iommu.c
    M include/hw/arm/npcm7xx.h
    M include/hw/arm/xlnx-versal.h
    M include/hw/boards.h
    A include/hw/misc/npcm7xx_mft.h
    M include/hw/misc/npcm7xx_pwm.h
    A include/hw/misc/xlnx-versal-xramc.h
    M include/sysemu/dma.h
    M softmmu/dma-helpers.c
    M target/arm/kvm.c
    M target/arm/kvm_arm.h
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c
    M tests/acceptance/boot_linux_console.py
    M tests/acceptance/replay_kernel.py
    M tests/qtest/npcm7xx_pwm-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20210312-1' into staging

target-arm queue:
 * versal: Support XRAMs and XRAM controller
 * smmu: Various minor bug fixes
 * SVE emulation: fix bugs handling odd vector lengths
 * allwinner-sun8i-emac: traverse transmit queue using TX_CUR_DESC register 
value
 * tests/acceptance: fix orangepi-pc acceptance tests
 * hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
 * hw/arm/virt: KVM: The IPA lower bound is 32
 * npcm7xx: support MFT module
 * pl110, pxa2xx_lcd: tidy up template headers

# gpg: Signature made Fri 12 Mar 2021 13:50:34 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210312-1: (39 commits)
  hw/display/pxa2xx: Inline template header
  hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header
  hw/display/pxa2xx: Apply brace-related coding style fixes to template header
  hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h
  hw/display/pxa2xx_lcd: Remove dest_width state field
  hw/display/pxa2xx_lcd: Remove dead code for non-32-bpp surfaces
  hw/display/pl110: Remove use of BITS from pl110_template.h
  hw/display/pl110: Pull included-once parts of template header into pl110.c
  hw/display/pl110: Remove dead code for non-32-bpp surfaces
  tests/qtest: Test PWM fan RPM using MFT in PWM test
  hw/arm: Connect PWM fans in NPCM7XX boards
  hw/arm: Add MFT device to NPCM7xx Soc
  hw/misc: Add NPCM7XX MFT Module
  hw/misc: Add GPIOs for duty in NPCM7xx PWM
  hw/arm/virt: KVM: The IPA lower bound is 32
  accel: kvm: Fix kvm_type invocation
  hw/timer/sse-timer: Propagate eventual error in sse_timer_realize()
  tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, 
cubieboard tests
  tests/acceptance: update sunxi kernel from armbian to 5.10.16
  tests/acceptance/boot_linux_console: change URL for 
test_arm_orangepi_bionic_20_08
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/8e6bc6cdc82d...9a954a4a62a7
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the XRAM controller, Peter Maydell <=
- [Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the XRAM controller, Peter Maydell, 2021/03/14
Prev by Date: [Qemu-commits] [qemu/qemu] 6abcec: target/m68k: implement rtr instruction
Next by Date: [Qemu-commits] [qemu/qemu] 999be4: tests/qtest: Test PWM fan RPM using MFT in PWM test
Previous by thread: [Qemu-commits] [qemu/qemu] 6abcec: target/m68k: implement rtr instruction
Next by thread: [Qemu-commits] [qemu/qemu] 9f6176: hw/misc: versal: Add a model of the XRAM controller
Index(es):
- Date
- Thread