[Qemu-commits] [qemu/qemu] 6abcec: target/m68k: implement rtr instruction

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 6abcec36741e589c855084e59195fc3454bf4be6
      
https://github.com/qemu/qemu/commit/6abcec36741e589c855084e59195fc3454bf4be6
  Author: Laurent Vivier <laurent@vivier.eu>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: implement rtr instruction

This is needed to boot MacOS ROM.

Pull the condition code and the program counter from the stack.

Operation:

    (SP) -> CCR
    SP + 2 -> SP
    (SP) -> PC
    SP + 4 -> SP

This operation is not privileged.

Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210307212552.523552-1-laurent@vivier.eu>


  Commit: d6cbd8f7a19e6f0fd22a598aad992c4913f481f2
      
https://github.com/qemu/qemu/commit/d6cbd8f7a19e6f0fd22a598aad992c4913f481f2
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M target/m68k/op_helper.c

  Log Message:
  -----------
  target/m68k: don't set SSW ATC bit for physical bus errors

If a NuBus slot doesn't contain a card, the Quadra hardware generates a physical
bus error if the CPU attempts to access the slot address space. Both Linux and
MacOS use a separate bus error handler during NuBus accesses in order to detect
and recover when addressing empty slots.

According to the MC68040 users manual the ATC bit of the SSW is used to
distinguish between ATC faults and physical bus errors. MacOS specifically 
checks
the stack frame generated by a NuBus error and panics if the SSW ATC bit is set.

Update m68k_cpu_transaction_failed() so that the SSW ATC bit is not set if the
memory API returns MEMTX_DECODE_ERROR which will be used to indicate that an
access to an empty NuBus slot occurred.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20210308121155.2476-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 469949c90252d80693aa70652d8251d1d602557e
      
https://github.com/qemu/qemu/commit/469949c90252d80693aa70652d8251d1d602557e
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M target/m68k/cpu.h

  Log Message:
  -----------
  target/m68k: reformat m68k_features enum

Move the feature comment from after the feature name to the preceding line to
allow for longer feature names and descriptions without hitting the 80
character line limit.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210308121155.2476-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: a9431a03f70c8c711a870d4c1a0439bdbb4703cf
      
https://github.com/qemu/qemu/commit/a9431a03f70c8c711a870d4c1a0439bdbb4703cf
  Author: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
  Date:   2021-03-11 (Thu, 11 Mar 2021)

  Changed paths:
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/op_helper.c

  Log Message:
  -----------
  target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature

According to the M68040UM Appendix D the requirement for data accesses to be
word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the
68020 onwards will allow unaligned data accesses but at the cost of being less
efficient.

Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are
not required to be word aligned, and don't perform the alignment on the stack
pointer when taking an exception if this feature is not selected.

This is required because the MacOS DAFB driver attempts to call an A-trap
with a byte-aligned stack pointer during initialisation and without this the
stack pointer is off by one when the A-trap returns.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>


  Commit: 8e6bc6cdc82d45f203bc9fc4342c0452214c74fe
      
https://github.com/qemu/qemu/commit/8e6bc6cdc82d45f203bc9fc4342c0452214c74fe
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-12 (Fri, 12 Mar 2021)

  Changed paths:
    M target/m68k/cpu.c
    M target/m68k/cpu.h
    M target/m68k/op_helper.c
    M target/m68k/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-6.0-pull-request' 
into staging

Prepare MacOS ROM support:
  - add RTR instruction
  - fix unaligned access requirement
  - fix ATC bit (68040 MMU)

# gpg: Signature made Thu 11 Mar 2021 22:18:11 GMT
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" 
[full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-6.0-pull-request:
  target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature
  target/m68k: reformat m68k_features enum
  target/m68k: don't set SSW ATC bit for physical bus errors
  target/m68k: implement rtr instruction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/09b5d1ceadef...8e6bc6cdc82d