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[Qemu-commits] [qemu/qemu] a4ea92: arm/ast2600: Fix SMP booting with -ke
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] a4ea92: arm/ast2600: Fix SMP booting with -kernel |
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Date: |
Thu, 11 Mar 2021 05:56:55 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a4ea92013d265f636d71b58408b67dbecd679d1d
https://github.com/qemu/qemu/commit/a4ea92013d265f636d71b58408b67dbecd679d1d
Author: Joel Stanley <joel@jms.id.au>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
arm/ast2600: Fix SMP booting with -kernel
The ast2600 machines do not have PSCI firmware, so this property should
have never been set. Removing this node fixes SMP booting Linux kernels
that have PSCI enabled, as Linux fails to find PSCI in the device tree
and falls back to the soc-specific method for enabling secondary CPUs.
The comment is out of date as Qemu has supported -kernel booting since
9bb6d14081ce ("aspeed: Add boot stub for smp booting"), in v5.1.
Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210303010505.635621-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d029c7293140610f96b0786b88e6f9cdf1106adc
https://github.com/qemu/qemu/commit/d029c7293140610f96b0786b88e6f9cdf1106adc
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
hw/arm/aspeed: Fix location of firmware images in documentation
Firmware images can be found on the OpenBMC jenkins site and on the
OpenBMC GitHub release page.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20210303072743.1551329-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 957ad79f7316816433f772b1a9ebdfe0a3818cb2
https://github.com/qemu/qemu/commit/957ad79f7316816433f772b1a9ebdfe0a3818cb2
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
This appears to be a requirement of the GIC model. The AST2600 allocates
197 GIC IRQs, which we will adjust shortly.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-2-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b151de69f6478a05b27f4be2eb4a906f7b5b8cfa
https://github.com/qemu/qemu/commit/b151de69f6478a05b27f4be2eb4a906f7b5b8cfa
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
The datasheet says we have 197 IRQs allocated, and we need more than 128
to describe IRQs from LPC devices. Raise the value now to allow
modelling of the LPC devices.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-3-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6820588efa4fbab9ab6f0457f2c83c3bc7498ae3
https://github.com/qemu/qemu/commit/6820588efa4fbab9ab6f0457f2c83c3bc7498ae3
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
hw/arm: ast2600: Correct the iBT interrupt ID
The AST2600 allocates distinct GIC IRQs for the LPC subdevices such as
the iBT device. Previously on the AST2400 and AST2500 the LPC subdevices
shared a single LPC IRQ.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-4-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2ecf17264debe1bc3399fe587690c78d03e8401b
https://github.com/qemu/qemu/commit/2ecf17264debe1bc3399fe587690c78d03e8401b
Author: Cédric Le Goater <clg@kaod.org>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
A hw/misc/aspeed_lpc.c
M hw/misc/meson.build
M include/hw/arm/aspeed_soc.h
A include/hw/misc/aspeed_lpc.h
Log Message:
-----------
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: c59f781e3bcca4a80aef5d229488fd45dbfdbd9a
https://github.com/qemu/qemu/commit/c59f781e3bcca4a80aef5d229488fd45dbfdbd9a
Author: Andrew Jeffery <andrew@aj.id.au>
Date: 2021-03-09 (Tue, 09 Mar 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/misc/aspeed_lpc.c
M include/hw/arm/aspeed_soc.h
M include/hw/misc/aspeed_lpc.h
Log Message:
-----------
hw/misc: Model KCS devices in the Aspeed LPC controller
Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC
IO cycles from the BMC to the host.
Expose support on the BMC side by implementing the usual MMIO
behaviours, and expose the ability to inspect the KCS registers in
"host" style by accessing QOM properties associated with each register.
The model caters to the IRQ style of both the AST2600 and the earlier
SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC
sub-device, while there is a single IRQ shared across all subdevices on
the AST2400 and AST2500.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210302014317.915120-6-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 363fc963054d8e82cfd55fa9b9aa130692a8dbd7
https://github.com/qemu/qemu/commit/363fc963054d8e82cfd55fa9b9aa130692a8dbd7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-11 (Thu, 11 Mar 2021)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
A hw/misc/aspeed_lpc.c
M hw/misc/meson.build
M include/hw/arm/aspeed_soc.h
A include/hw/misc/aspeed_lpc.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210309'
into staging
Aspeed patches :
* New model for the Aspeed LPC controller
* Misc cleanups
# gpg: Signature made Tue 09 Mar 2021 11:54:25 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-aspeed-20210309:
hw/misc: Model KCS devices in the Aspeed LPC controller
hw/misc: Add a basic Aspeed LPC controller model
hw/arm: ast2600: Correct the iBT interrupt ID
hw/arm: ast2600: Set AST2600_MAX_IRQ to value from datasheet
hw/arm: ast2600: Force a multiple of 32 of IRQs for the GIC
hw/arm/aspeed: Fix location of firmware images in documentation
arm/ast2600: Fix SMP booting with -kernel
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d689ecad073e...363fc963054d