qemu-commits
[Top][All Lists]
Advanced
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] 355935: hw/dma: Implement a Xilinx CSU DMA mo

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 355935: hw/dma: Implement a Xilinx CSU DMA model
Date: Wed, 10 Mar 2021 05:58:07 -0800 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 35593573b25f8774ce16be8a7d703b7740964e81
      
https://github.com/qemu/qemu/commit/35593573b25f8774ce16be8a7d703b7740964e81
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-03-08 (Mon, 08 Mar 2021)

  Changed paths:
    M hw/dma/Kconfig
    M hw/dma/meson.build
    A hw/dma/xlnx_csu_dma.c
    A include/hw/dma/xlnx_csu_dma.h

  Log Message:
  -----------
  hw/dma: Implement a Xilinx CSU DMA model

ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
crash. This is observed when testing VxWorks 7.

This adds a Xilinx CSU DMA model and the implementation is based on
https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c.
The DST part of the model is verified along with ZynqMP GQSPI model.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 21bce3717e2cb70e3bea06e8684bae111c9f4dda
      
https://github.com/qemu/qemu/commit/21bce3717e2cb70e3bea06e8684bae111c9f4dda
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm: xlnx-zynqmp: Clean up coding convention issues

There are some coding convention warnings in xlnx-zynqmp.c and
xlnx-zynqmp.h, as reported by:

  $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h
  $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c

Let's clean them up.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 668351a54883b6283e7ae94daf4d4eca1a071158
      
https://github.com/qemu/qemu/commit/668351a54883b6283e7ae94daf4d4eca1a071158
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI

Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 3754eed4206f2472b5f4e4c3d84a1d39f0cd5d7c
      
https://github.com/qemu/qemu/commit/3754eed4206f2472b5f4e4c3d84a1d39f0cd5d7c
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  hw/ssi: xilinx_spips: Clean up coding convention issues

There are some coding convention warnings in xilinx_spips.c,
as reported by:

  $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c

Let's clean them up.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-5-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: d6bafaf45c5ff31ad7d7d87c3c3d37ae675684cc
      
https://github.com/qemu/qemu/commit/d6bafaf45c5ff31ad7d7d87c3c3d37ae675684cc
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips

Now that the Xilinx CSU DMA model is implemented, the existing
DMA related dead codes in the ZynqMP QSPI are useless and should
be removed. The maximum register number is also updated to only
include the QSPI registers.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 02f8fe11f7af92bacc6fc7f661ea5076e8a63e43
      
https://github.com/qemu/qemu/commit/02f8fe11f7af92bacc6fc7f661ea5076e8a63e43
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/timer/renesas_tmr.c

  Log Message:
  -----------
  hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_

The #defines INTERNAL and CASCADING represent different possible
values for the TCCR.CSS register field; prefix them with CSS_ to make
this more obvious, before we add more defines to represent the
other possible values of the field in the next commit.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219223241.16344-2-peter.maydell@linaro.org


  Commit: 81b3ddaf8772ec6f88d372e52f9b433cfa46bc46
      
https://github.com/qemu/qemu/commit/81b3ddaf8772ec6f88d372e52f9b433cfa46bc46
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M hw/timer/renesas_tmr.c

  Log Message:
  -----------
  hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()

The read_tcnt() function calculates the TCNT register values for the
two channels of the timer module; it sets these up in the local
tcnt[] array, and eventually returns either one or both of them,
depending on whether the access is 8 or 16 bits.  However, not all of
the code paths through this function set both elements of this array:
if the guest has programmed the TCCR.CSS register fields to values
which are either documented as not to be used or which QEMU does not
implement, then the function will return uninitialized data.  (This
was spotted by Coverity.)

Add the missing CSS cases to this code, so that we return a
consistent value instead of uninitialized data, and so the code
structure indicates what's happening.

Fixes: CID 1429976
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219223241.16344-3-peter.maydell@linaro.org


  Commit: 5c6295a45b4fceac913c11abc62488c49c02b9fd
      
https://github.com/qemu/qemu/commit/5c6295a45b4fceac913c11abc62488c49c02b9fd
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-10 (Wed, 10 Mar 2021)

  Changed paths:
    M MAINTAINERS
    M docs/devel/clocks.rst
    M docs/system/arm/mps2.rst
    M hw/adc/npcm7xx_adc.c
    M hw/arm/Kconfig
    M hw/arm/armsse.c
    M hw/arm/mps2-tz.c
    M hw/arm/xlnx-zynqmp.c
    M hw/char/cadence_uart.c
    M hw/char/ibex_uart.c
    M hw/char/pl011.c
    M hw/core/clock.c
    M hw/core/qdev-clock.c
    M hw/dma/Kconfig
    M hw/dma/meson.build
    A hw/dma/xlnx_csu_dma.c
    M hw/mips/cps.c
    M hw/misc/Kconfig
    A hw/misc/armsse-cpu-pwrctrl.c
    M hw/misc/bcm2835_cprman.c
    M hw/misc/iotkit-secctl.c
    M hw/misc/iotkit-sysctl.c
    M hw/misc/iotkit-sysinfo.c
    M hw/misc/meson.build
    M hw/misc/mps2-fpgaio.c
    M hw/misc/mps2-scc.c
    M hw/misc/npcm7xx_clk.c
    M hw/misc/npcm7xx_pwm.c
    M hw/misc/trace-events
    M hw/misc/zynq_slcr.c
    M hw/ssi/xilinx_spips.c
    M hw/timer/Kconfig
    M hw/timer/cmsdk-apb-dualtimer.c
    M hw/timer/cmsdk-apb-timer.c
    M hw/timer/meson.build
    M hw/timer/npcm7xx_timer.c
    M hw/timer/renesas_tmr.c
    A hw/timer/sse-counter.c
    A hw/timer/sse-timer.c
    M hw/timer/trace-events
    M hw/watchdog/cmsdk-apb-watchdog.c
    A include/hw/arm/armsse-version.h
    M include/hw/arm/armsse.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/clock.h
    A include/hw/dma/xlnx_csu_dma.h
    A include/hw/misc/armsse-cpu-pwrctrl.h
    M include/hw/misc/iotkit-secctl.h
    M include/hw/misc/iotkit-sysctl.h
    M include/hw/misc/iotkit-sysinfo.h
    M include/hw/misc/mps2-fpgaio.h
    M include/hw/qdev-clock.h
    M include/hw/ssi/xilinx_spips.h
    A include/hw/timer/sse-counter.h
    A include/hw/timer/sse-timer.h
    M target/arm/cpu.c
    M target/arm/cpu_tcg.c
    M target/mips/cpu.c
    M tests/qtest/meson.build
    A tests/qtest/sse-timer-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210310' 
into staging

target-arm queue:
 * Add new mps3-an547 board
 * target/arm: Restrict v7A TCG cpus to TCG accel
 * Implement a Xilinx CSU DMA model
 * hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()

# gpg: Signature made Wed 10 Mar 2021 13:56:20 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210310: (54 commits)
  hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
  hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
  hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
  hw/ssi: xilinx_spips: Clean up coding convention issues
  hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
  hw/arm: xlnx-zynqmp: Clean up coding convention issues
  hw/dma: Implement a Xilinx CSU DMA model
  target/arm: Restrict v7A TCG cpus to TCG accel
  tests/qtest/sse-timer-test: Test counter scaling changes
  tests/qtest/sse-timer-test: Test the system timer
  tests/qtest/sse-timer-test: Add simple test of the SSE counter
  docs/system/arm/mps2.rst: Document the new mps3-an547 board
  hw/arm/mps2-tz: Add new mps3-an547 board
  hw/arm/mps2-tz: Make initsvtor0 setting board-specific
  hw/arm/mps2-tz: Support running APB peripherals on different clock
  hw/misc/mps2-scc: Implement changes for AN547
  hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
  hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
  hw/arm/mps2-tz: Make UART overflow IRQ board-specific
  hw/arm/armsse: Add SSE-300 support
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/bd5664de7e6c...5c6295a45b4f
reply via email to
[Prev in Thread] Current Thread [Next in Thread]