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[Qemu-commits] [qemu/qemu] 5ee0ab: clock: Add ClockEvent parameter to ca
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 5ee0ab: clock: Add ClockEvent parameter to callbacks |
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Date: |
Wed, 10 Mar 2021 03:10:57 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 5ee0abed51231949ef91d7f8e1115be69ed91e93
https://github.com/qemu/qemu/commit/5ee0abed51231949ef91d7f8e1115be69ed91e93
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M docs/devel/clocks.rst
M hw/adc/npcm7xx_adc.c
M hw/arm/armsse.c
M hw/char/cadence_uart.c
M hw/char/ibex_uart.c
M hw/char/pl011.c
M hw/core/clock.c
M hw/core/qdev-clock.c
M hw/mips/cps.c
M hw/misc/bcm2835_cprman.c
M hw/misc/npcm7xx_clk.c
M hw/misc/npcm7xx_pwm.c
M hw/misc/zynq_slcr.c
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/npcm7xx_timer.c
M hw/watchdog/cmsdk-apb-watchdog.c
M include/hw/clock.h
M include/hw/qdev-clock.h
M target/mips/cpu.c
Log Message:
-----------
clock: Add ClockEvent parameter to callbacks
The Clock framework allows users to specify a callback which is
called after the clock's period has been updated. Some users need to
also have a callback which is called before the clock period is
updated.
As the first step in adding support for notifying Clock users on
pre-update events, add an argument to the ClockCallback to specify
what event is being notified, and add an argument to the various
functions for registering a callback to specify which events are
of interest to that callback.
Note that the documentation update renders correct the previously
incorrect claim in 'Adding a new clock' that callbacks "will be
explained in a following section".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-2-peter.maydell@linaro.org
Commit: e4341623a3b87e7eca87d42b7b88da967cd21c49
https://github.com/qemu/qemu/commit/e4341623a3b87e7eca87d42b7b88da967cd21c49
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M docs/devel/clocks.rst
M hw/core/clock.c
M include/hw/clock.h
Log Message:
-----------
clock: Add ClockPreUpdate callback event type
Add a new callback event type ClockPreUpdate, which is called on
period changes before the period is updated.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144617.4782-3-peter.maydell@linaro.org
Commit: cd3a53b727d2f86e9db795cee69cc142332ca079
https://github.com/qemu/qemu/commit/cd3a53b727d2f86e9db795cee69cc142332ca079
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M docs/devel/clocks.rst
M include/hw/clock.h
Log Message:
-----------
clock: Add clock_ns_to_ticks() function
Add a clock_ns_to_ticks() function which does the opposite of
clock_ticks_to_ns(): given a duration in nanoseconds, it returns the
number of clock ticks that would happen in that time. This is useful
for devices that have a free running counter register whose value can
be calculated when it is read.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144617.4782-4-peter.maydell@linaro.org
Commit: c7db11b0992f8d97107ec30139ffe1a09559c77e
https://github.com/qemu/qemu/commit/c7db11b0992f8d97107ec30139ffe1a09559c77e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/timer/npcm7xx_timer.c
Log Message:
-----------
hw/timer/npcm7xx_timer: Use new clock_ns_to_ticks()
Use the new clock_ns_to_ticks() function in npcm7xx_timer where
appropriate.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144617.4782-5-peter.maydell@linaro.org
Commit: 419a7f8075e24734ee22c3ceef6a446ba5306b27
https://github.com/qemu/qemu/commit/419a7f8075e24734ee22c3ceef6a446ba5306b27
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M hw/misc/iotkit-sysctl.c
A include/hw/arm/armsse-version.h
M include/hw/misc/iotkit-sysctl.h
Log Message:
-----------
hw/arm/armsse: Introduce SSE subsystem version property
We model Arm "Subsystems for Embedded" SoC subsystems using generic
code which is split into various sub-devices which are configurable
by QOM properties to handle the behaviour differences between the SSE
subsystems we implement. Currently the only sub-device which needs
to change is the IOTKIT_SYSCTL device, and we do this with a mix of
properties that directly specify divergent behaviours (eg
CPUWAIT_RST) and passing it the SYS_VERSION register value as a way
for it to distinguish IoTKit from SSE-200.
The "pass SYS_VERSION" approach is already a bit hacky, since the
IOTKIT_SYSCTL device has to know that the different part of the
register value happens to be bits [31:28]. For SSE-300 this register
is renamed SOC_IDENTITY and has a different format entirely, all of
whose fields can be configured by the SoC integrator when they
integrate the SSE into their SoC, and so "pass SYS_VERSION" breaks
down completely.
Switch to using a simple integer property representing an
internal-to-QEMU enumeration of the SSE flavour. For the moment we
only need this in IOTKIT_SYSCTL, but as we add SSE-300 support a few
of the other devices will also need to know.
We define and permit a value for the SSE-300 so we can start using
it in subsequent commits which add SSE-300 support.
The now-redundant is_sse200 flag in IoTKitSysCtl will be removed
in the following commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-6-peter.maydell@linaro.org
Commit: 1cbd6fe4b8d5ae77de583b298d7834c8abe6ff46
https://github.com/qemu/qemu/commit/1cbd6fe4b8d5ae77de583b298d7834c8abe6ff46
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
M include/hw/misc/iotkit-sysctl.h
Log Message:
-----------
hw/misc/iotkit-sysctl: Remove is_sse200 flag
Remove the is_sse200 flag in favour of just directly testing the new
sse_version field.
Since some of these registers exist in the SSE-300 but some do not or
have different behaviour, we expand out the if() statements in the
read and write functions into switch()es, so we have an easy place to
put SSE-300 specific behaviour.
(Until we do add the SSE-300 behaviour, the thing preventing us
reaching the "unreachable" default cases is that armsse.c doesn't
yet pass us an ARMSSE_SSE300 version.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-7-peter.maydell@linaro.org
Commit: 0eb6b0ad16dfb3c4834c6943c3132b8d96294730
https://github.com/qemu/qemu/commit/0eb6b0ad16dfb3c4834c6943c3132b8d96294730
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M hw/misc/iotkit-secctl.c
M include/hw/misc/iotkit-secctl.h
Log Message:
-----------
hw/misc/iotkit-secctl.c: Implement SSE-300 PID register values
The versions of the Secure Access Configuration Register Block
and Non-secure Access Configuration Register Block in the SSE-300
are the same as those in the SSE-200, but the CIDR/PIDR ID
register values are different.
Plumb through the sse-version property and use it to select
the correct ID register values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-8-peter.maydell@linaro.org
Commit: 407664539d76523222a4a4a3ef273645593f75b2
https://github.com/qemu/qemu/commit/407664539d76523222a4a4a3ef273645593f75b2
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M hw/misc/iotkit-sysinfo.c
M include/hw/misc/iotkit-sysinfo.h
Log Message:
-----------
hw/misc/iotkit-sysinfo.c: Implement SSE-300 PID register values
The version of the SYSINFO Register Block in the SSE-300 has
different CIDR/PIDR register values to the SSE-200; pass in
the sse-version property and use it to select the correct
ID register values.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-9-peter.maydell@linaro.org
Commit: c89cef3a2cdfb355258890db8cfd2175add5bbee
https://github.com/qemu/qemu/commit/c89cef3a2cdfb355258890db8cfd2175add5bbee
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
hw/arm/armsse.c: Use correct SYS_CONFIG0 register value for SSE-300
In the SSE-300, the format of the SYS_CONFIG0 register has changed again;
pass through the correct value to the SYSINFO register block device.
We drop the old SysConfigFormat enum, which was implemented in the
hope that different flavours of SSE would share the same format;
since they all seem to be different and we now have an sse_version
enum to key off, just use that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-10-peter.maydell@linaro.org
Commit: 446587a914cfa57c2ce529056a9ca2215bde7111
https://github.com/qemu/qemu/commit/446587a914cfa57c2ce529056a9ca2215bde7111
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M hw/misc/iotkit-sysinfo.c
M include/hw/misc/iotkit-sysinfo.h
Log Message:
-----------
hw/misc/iotkit-sysinfo.c: Implement SYS_CONFIG1 and IIDR
For SSE-300, the SYSINFO register block has two new registers:
* SYS_CONFIG1 indicates the config for a potential CPU2 and CPU3;
since the SSE-300 can only be configured with a single CPU it
is always zero
* IIDR is the subsystem implementation identity register;
its value is set by the SoC integrator, so we plumb this in from
the armsse.c code as we do with SYS_VERSION and SYS_CONFIG
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-11-peter.maydell@linaro.org
Commit: 0d10df30384c22c5f683cbfebc42cee6cf83fed4
https://github.com/qemu/qemu/commit/0d10df30384c22c5f683cbfebc42cee6cf83fed4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M MAINTAINERS
M hw/arm/Kconfig
M hw/timer/Kconfig
M hw/timer/meson.build
A hw/timer/sse-counter.c
M hw/timer/trace-events
A include/hw/timer/sse-counter.h
Log Message:
-----------
hw/timer/sse-counter: Model the SSE Subsystem System Counter
The SSE-300 includes a counter module; implement a model of it.
This counter is documented in the SSE-123 Example Subsystem
Technical Reference Manual:
https://developer.arm.com/documentation/101370/latest/
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-12-peter.maydell@linaro.org
Commit: 0b8ceee822ae6d3bc4033c9b406c5f8d8c71ee6d
https://github.com/qemu/qemu/commit/0b8ceee822ae6d3bc4033c9b406c5f8d8c71ee6d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M MAINTAINERS
M hw/arm/Kconfig
M hw/timer/Kconfig
M hw/timer/meson.build
A hw/timer/sse-timer.c
M hw/timer/trace-events
A include/hw/timer/sse-timer.h
Log Message:
-----------
hw/timer/sse-timer: Model the SSE Subsystem System Timer
The SSE-300 includes some timers which are a different kind to
those in the SSE-200. Model them.
These timers are documented in the SSE-123 Example Subsystem
Technical Reference Manual:
https://developer.arm.com/documentation/101370/latest/
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-13-peter.maydell@linaro.org
Commit: 31b0c6b17691b16175cb4bb01068df15d3b3b08c
https://github.com/qemu/qemu/commit/31b0c6b17691b16175cb4bb01068df15d3b3b08c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
Log Message:
-----------
hw/misc/iotkit-sysctl: Add SSE-300 cases which match SSE-200 behaviour
The SSE-300's iokit-sysctl device is similar to the SSE-200, but
some registers have moved address or have different behaviours.
In this commit we add case statements for the registers where
the SSE-300 and SSE-200 have the same behaviour. Some registers
are the same on all SSE versions and so need no code change at all.
Putting both of these categories together covers:
0x0 SECDBGSTAT
0x4 SECDBGSET
0x8 SECDBGCLR
0xc SCSECCTRL
0x10 CLK_CFG0 -- this is like SSE-200 FCLK_DIV but with a
different set of clocks being controlled; our implementation
is a dummy reads-as-written anyway
0x14 CLK_CFG1 -- similar to SSE-200 SYSCLK_DIV; our implementation
is a dummy
0x18 CLK_FORCE -- similar to SSE-200 but different bit allocations;
we have a dummy implementation
0x100 RESET_SYNDROME -- bit allocation differs from SSE-200 but our
implementation is a dummy
0x104 RESET_MASK -- bit allocation differs from SSE-200 but our
implementation is a dummy
0x108 SWRESET
0x10c GRETREG
0x200 PDCM_PD_SYS_SENSE -- some bit allocations differ, but our
implementation is a dummy
We also need to migrate the state of these registers which are shared
between the SSE-200 and SSE-300, so update the vmstate 'needed'
function to do this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-14-peter.maydell@linaro.org
Commit: 92ecf2d5eeaecec2454e95acf2416162538c1225
https://github.com/qemu/qemu/commit/92ecf2d5eeaecec2454e95acf2416162538c1225
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
Log Message:
-----------
hw/misc/iotkit-sysctl: Handle CPU_WAIT, NMI_ENABLE for SSE-300
In the SSE-300 the CPU_WAIT and NMI_ENABLE registers have
moved offsets, so they are now where the SSE-200's WICCTRL
and EWCTRL were. The SSE-300 does not have WICCTLR or EWCTRL
at all, and the old offsets are reserved:
Offset SSE-200 SSE-300
-----------------------------------
0x118 CPUWAIT reserved
0x118 NMI_ENABLE reserved
0x120 WICCTRL CPUWAIT
0x124 EWCTRL NMI_ENABLE
Handle this reshuffle, and the fact that SSE-300 has only
one CPU and so only one active bit in CPUWAIT.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-15-peter.maydell@linaro.org
Commit: 246dbeb76319fdaa7030403ea0273617331f6a44
https://github.com/qemu/qemu/commit/246dbeb76319fdaa7030403ea0273617331f6a44
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
Log Message:
-----------
hw/misc/iotkit-sysctl: Handle INITSVTOR* for SSE-300
The SSE-300 has only one CPU and so no INITSVTOR1. It does
have INITSVTOR0, but unlike the SSE-200 this register now
has a LOCK bit which can be set to 1 to prevent any further
writes to the register. Implement these differences.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-16-peter.maydell@linaro.org
Commit: 2672a6ca72311bdf97f9e324ab2e71ff60bd2db9
https://github.com/qemu/qemu/commit/2672a6ca72311bdf97f9e324ab2e71ff60bd2db9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
M include/hw/misc/iotkit-sysctl.h
Log Message:
-----------
hw/misc/iotkit-sysctl: Implement dummy version of SSE-300 PWRCTRL register
The SSE-300 has a new PWRCTRL register at offset 0x1fc (previously
reserved). This register controls accessibility of some registers
in the Power Policy Units (PPUs). Since QEMU doesn't implement
the PPUs, we don't need to implement any real behaviour for this
register, so we just handle the UNLOCK bit which controls whether
writes to the register itself are permitted and otherwise make it
be reads-as-written.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-17-peter.maydell@linaro.org
Commit: c5ffe6c8dd5623f1893f54971e23e7c1ddf094ee
https://github.com/qemu/qemu/commit/c5ffe6c8dd5623f1893f54971e23e7c1ddf094ee
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
M include/hw/misc/iotkit-sysctl.h
Log Message:
-----------
hw/misc/iotkit-sysctl: Handle SSE-300 changes to PDCM_PD_*_SENSE registers
The sysctl PDCM_PD_*_SENSE registers control various power domains in
the system and allow the guest to configure which conditions keep a
power domain awake and what power state to use when the domain is in
a low power state. QEMU doesn't model power domains, so for us these
registers are dummy reads-as-written implementations.
The SSE-300 has a different power domain setup, so the set of
registers is slightly different:
Offset SSE-200 SSE-300
---------------------------------------------------
0x200 PDCM_PD_SYS_SENSE PDCM_PD_SYS_SENSE
0x204 reserved PDCM_PD_CPU0_SENSE
0x208 reserved reserved
0x20c PDCM_PD_SRAM0_SENSE reserved
0x210 PDCM_PD_SRAM1_SENSE reserved
0x214 PDCM_PD_SRAM2_SENSE PDCM_PD_VMR0_SENSE
0x218 PDCM_PD_SRAM3_SENSE PDCM_PD_VMR1_SENSE
Offsets 0x200 and 0x208 are the same for both, so handled in a
previous commit; here we deal with 0x204, 0x20c, 0x210, 0x214, 0x218.
(We can safely add new lines to the SSE300 vmstate because no board
uses this device in an SSE300 yet.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-18-peter.maydell@linaro.org
Commit: 6069bbc904503dd4f4c2cfd7ff883300a6bddeeb
https://github.com/qemu/qemu/commit/6069bbc904503dd4f4c2cfd7ff883300a6bddeeb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/iotkit-sysctl.c
Log Message:
-----------
hw/misc/iotkit-sysctl: Implement SSE-200 and SSE-300 PID register values
The SSE-200 and SSE-300 have different PID register values from the
IoTKit for the sysctl register block. We incorrectly implemented the
SSE-200 with the same PID values as IoTKit. Fix the SSE-200 bug and
report these register values for SSE-300.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-19-peter.maydell@linaro.org
Commit: 370d75d935c4f58a3f94597a9e6609aefbc5bb34
https://github.com/qemu/qemu/commit/370d75d935c4f58a3f94597a9e6609aefbc5bb34
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/Kconfig
M hw/misc/Kconfig
Log Message:
-----------
hw/arm/Kconfig: Move ARMSSE_CPUID and ARMSSE_MHU stanzas to hw/misc
The ARMSSE_CPUID and ARMSSE_MHU Kconfig stanzas are for the devices
implemented by hw/misc/cpuid.c and hw/misc/armsse-mhu.c. Move them
to hw/misc/Kconfig where they belong.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-20-peter.maydell@linaro.org
Commit: 4239b311467bea86578d9da3cd22909de69d7af7
https://github.com/qemu/qemu/commit/4239b311467bea86578d9da3cd22909de69d7af7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M MAINTAINERS
M hw/arm/Kconfig
M hw/misc/Kconfig
A hw/misc/armsse-cpu-pwrctrl.c
M hw/misc/meson.build
M hw/misc/trace-events
A include/hw/misc/armsse-cpu-pwrctrl.h
Log Message:
-----------
hw/misc/sse-cpu-pwrctrl: Implement SSE-300 CPU<N>_PWRCTRL register block
The SSE-300 has a new register block CPU<N>_PWRCTRL. There is one
instance of this per CPU in the system (so just one for the SSE-300),
and as well as the usual CIDR/PIDR ID registers it has just one
register, CPUPWRCFG. This register allows the guest to configure
behaviour of the system in power-down and deep-sleep states. Since
QEMU does not model those, we make the register a dummy
reads-as-written implementation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-21-peter.maydell@linaro.org
Commit: 91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688
https://github.com/qemu/qemu/commit/91eb4f64eb49ea8dc7e5ebf5fdb377008ee0b688
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Use an array for apb_ppc fields in the state structure
Convert the apb_ppc0 and apb_ppc1 fields in the ARMSSE state struct
to use an array instead of two separate fields. We already had one
place in the code that wanted to be able to refer to the PPC by
index, and we're about to add more code like that.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-22-peter.maydell@linaro.org
Commit: 3378873802afe8af0355c4fac3e11e6510fc1f27
https://github.com/qemu/qemu/commit/3378873802afe8af0355c4fac3e11e6510fc1f27
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add a define for number of IRQs used by the SSE itself
The SSE uses 32 interrupts for its own devices, and then passes through
its expansion IRQ inputs to the CPU's interrupts 33 and upward.
Add a define for the number of IRQs the SSE uses for itself, instead
of hardcoding 32.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-23-peter.maydell@linaro.org
Commit: e94d7723b5c0e7e51775ee8fc94a10e975392d0b
https://github.com/qemu/qemu/commit/e94d7723b5c0e7e51775ee8fc94a10e975392d0b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add framework for data-driven device placement
The SSE-300 is mostly the same as the SSE-200, but it has moved some
of the devices in the memory map and uses different device types in
some cases. To accommodate this, add a framework where the placement
and wiring of some devices can be specified in a data table.
This commit adds the framework for this data-driven device placement,
and makes the CMSDK APB timer devices use it. Subsequent commits
will convert the other devices which differ between SSE-200 and
SSE-300.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-24-peter.maydell@linaro.org
Commit: 7e8e25dbd385403569ce2df07b60b4f8a61f2266
https://github.com/qemu/qemu/commit/7e8e25dbd385403569ce2df07b60b4f8a61f2266
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
hw/arm/armsse: Move dual-timer device into data-driven framework
Move the CMSDK dualtimer device handling into the data-driven
device placement framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-25-peter.maydell@linaro.org
Commit: 1292b93289f8545f416f1d25ee701caa91d24415
https://github.com/qemu/qemu/commit/1292b93289f8545f416f1d25ee701caa91d24415
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Move watchdogs into data-driven framework
Move the CMSDK watchdog device handling into the data-driven device
placement framework. This is slightly more complicated because these
devices might wire their IRQs up to the NMI line, and because one of
them uses the slow 32KHz clock rather than the main clock.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-26-peter.maydell@linaro.org
Commit: 99865afc66bafca6f734712a897c0b68460f7757
https://github.com/qemu/qemu/commit/99865afc66bafca6f734712a897c0b68460f7757
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Move s32ktimer into data-driven framework
Move the CMSDK timer that uses the S32K slow clock into the data-driven
device placement framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-27-peter.maydell@linaro.org
Commit: 39bd0bb15f4849c24b1fe6a235f245479b8aac22
https://github.com/qemu/qemu/commit/39bd0bb15f4849c24b1fe6a235f245479b8aac22
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
hw/arm/armsse: Move sysinfo register block into data-driven framework
Move the sysinfo register block into the data-driven framework.
While we are moving the code for configuring this device around,
regularize on using &error_abortw when setting the integer
properties: they are all simple DEFINE_PROP_UINT32 properties so the
setting can never fail.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-28-peter.maydell@linaro.org
Commit: 9de4ddb49595670fcbf8da16c3a6bceb083c34ce
https://github.com/qemu/qemu/commit/9de4ddb49595670fcbf8da16c3a6bceb083c34ce
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
hw/arm/armsse: Move sysctl register block into data-driven framework
Move the sysctl register block into the data-driven device placement
framework.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-29-peter.maydell@linaro.org
Commit: a459e849aa2b683fac20fc72db9b4b1d90a4b4b9
https://github.com/qemu/qemu/commit/a459e849aa2b683fac20fc72db9b4b1d90a4b4b9
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Move PPUs into data-driven framework
Move the PPUs into the data-driven device placement framework.
We don't implement them, so they are just TYPE_UNIMPLEMENTED stubs.
Because the SSE-200 and the IotKit diverge here (the IoTKit does
not have the PPUs) we need to separate out the ARMSSEDeviceInfo
for the two variants, and only add the PPUs to the SSE-200.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-30-peter.maydell@linaro.org
Commit: 6fe8acb41ed5a4b033ae7b5f876968e568476129
https://github.com/qemu/qemu/commit/6fe8acb41ed5a4b033ae7b5f876968e568476129
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add missing SSE-200 SYS_PPU
We forgot to implement a TYPE_UNIMPLEMENTED_DEVICE stub
for the SYS_PPU in the SSE-200, which is at 0x50022000.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-31-peter.maydell@linaro.org
Commit: 1aa9e174b4b8de9ea52f9583c476e295065b96e3
https://github.com/qemu/qemu/commit/1aa9e174b4b8de9ea52f9583c476e295065b96e3
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
Log Message:
-----------
hw/arm/armsse: Indirect irq_is_common[] through ARMSSEInfo
The SSE-300 has a slightly different set of shared-per-CPU interrupts,
allow the irq_is_common[] array to be different per SSE variant.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-32-peter.maydell@linaro.org
Commit: 9febd175415dbc84e6ff7bda9bf6d90fe060181e
https://github.com/qemu/qemu/commit/9febd175415dbc84e6ff7bda9bf6d90fe060181e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add support for SSE variants with a system counter
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has the counter in a different location.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-33-peter.maydell@linaro.org
Commit: f11de23158528c90b51c603c0cc3b2286e71d3fc
https://github.com/qemu/qemu/commit/f11de23158528c90b51c603c0cc3b2286e71d3fc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add support for TYPE_SSE_TIMER in ARMSSEDeviceInfo
The SSE-300 has four timers of type TYPE_SSE_TIMER; add support in
the code for having these in an ARMSSEDeviceInfo array.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-34-peter.maydell@linaro.org
Commit: 4668b441cb667619916d4bc6a204f3df06730dfb
https://github.com/qemu/qemu/commit/4668b441cb667619916d4bc6a204f3df06730dfb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Support variants with ARMSSE_CPU_PWRCTRL block
Support SSE variants like the SSE-300 with an ARMSSE_CPU_PWRCTRL register
block. Because this block is per-CPU and does not clash with any of the
SSE-200 devices, we handle it with a has_cpu_pwrctrl flag like the
existing has_cachectrl, has_cpusectrl and has_cpuid, rather than
trying to add per-CPU-device support to the devinfo array handling code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-35-peter.maydell@linaro.org
Commit: 8901bb414a2416a3ad3bc870770daaebb08c3aa8
https://github.com/qemu/qemu/commit/8901bb414a2416a3ad3bc870770daaebb08c3aa8
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/armsse.c
M include/hw/arm/armsse.h
Log Message:
-----------
hw/arm/armsse: Add SSE-300 support
Now we have sufficiently parameterised the code, we can add SSE-300
support by adding a new entry to the armsse_variants[] array.
Note that the main watchdog (unlike the s32k watchdog) in the SSE-300
is a different device from the CMSDK watchdog; we don't have a model
of it so we leave it as a TYPE_UNIMPLEMENTED_DEVICE stub.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-36-peter.maydell@linaro.org
Commit: 8b4b5c23f92df5ebc2c4aa55b01d4e1d9d06548e
https://github.com/qemu/qemu/commit/8b4b5c23f92df5ebc2c4aa55b01d4e1d9d06548e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make UART overflow IRQ board-specific
The AN547 puts the combined UART overflow IRQ at 48, not 47 like the
other images. Make this setting board-specific.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-37-peter.maydell@linaro.org
Commit: 7fa859914f58607bf874b9efecbe4be5726d91ac
https://github.com/qemu/qemu/commit/7fa859914f58607bf874b9efecbe4be5726d91ac
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/mps2-fpgaio.c
Log Message:
-----------
hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
We've already broken migration compatibility for all the MPS
boards, so we might as well take advantage of this to simplify
the vmstate for the FPGAIO device by folding the counters
subsection into the main vmstate description.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-38-peter.maydell@linaro.org
Commit: 39901aea063fb4be77a89d7badfed3998ad8fb4a
https://github.com/qemu/qemu/commit/39901aea063fb4be77a89d7badfed3998ad8fb4a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
M hw/misc/mps2-fpgaio.c
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
For the AN547 image, the FPGAIO block has an extra DBGCTRL register,
which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs
to the CPU. These signals control when the CPU permits use of the
external debug interface. Our CPU models don't implement the
external debug interface, so we model the register as
reads-as-written.
Implement the register, with a property defining whether it is
present, and allow mps2-tz boards to specify that it is present.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-39-peter.maydell@linaro.org
Commit: 6ac80818941829c01363e9feeefe08e8bc693ab7
https://github.com/qemu/qemu/commit/6ac80818941829c01363e9feeefe08e8bc693ab7
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/misc/mps2-scc.c
Log Message:
-----------
hw/misc/mps2-scc: Implement changes for AN547
Implement the minor changes required to the SCC block for AN547 images:
* CFG2 and CFG5 exist (like AN524)
* CFG3 is reserved (like AN524)
* CFG0 bit 1 is CPU_WAIT; we don't implement it, but note this
in the TODO comment
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-40-peter.maydell@linaro.org
Commit: ad28ca7e9fb99242d4b8ba22e5234f73db59bff4
https://github.com/qemu/qemu/commit/ad28ca7e9fb99242d4b8ba22e5234f73db59bff4
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Support running APB peripherals on different clock
The AN547 runs the APB peripherals outside the SSE-300 on a different
and slightly slower clock than it runs the SSE-300 with. Support
making the APB peripheral clock frequency board-specific. (For our
implementation only the UARTs actually take a clock.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-41-peter.maydell@linaro.org
Commit: 9fe1ea11264914d7e1303d903059acfecff98421
https://github.com/qemu/qemu/commit/9fe1ea11264914d7e1303d903059acfecff98421
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Make initsvtor0 setting board-specific
The AN547 configures the SSE-300 with a different initsvtor0
setting from its default; make this a board-specific setting.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-42-peter.maydell@linaro.org
Commit: eb09d533d87fd83c79dc659a882770c9897e73db
https://github.com/qemu/qemu/commit/eb09d533d87fd83c79dc659a882770c9897e73db
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Add new mps3-an547 board
Add support for the mps3-an547 board; this is an SSE-300 based
FPGA image that runs on the MPS3.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210219144617.4782-43-peter.maydell@linaro.org
Commit: dd750743ecd01352ad7697cabd58cb26abf11efd
https://github.com/qemu/qemu/commit/dd750743ecd01352ad7697cabd58cb26abf11efd
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M docs/system/arm/mps2.rst
Log Message:
-----------
docs/system/arm/mps2.rst: Document the new mps3-an547 board
Add brief documentation of the new mps3-an547 board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144617.4782-44-peter.maydell@linaro.org
Commit: 1eca58aa1db79b077abf8c031c4d600998a5438d
https://github.com/qemu/qemu/commit/1eca58aa1db79b077abf8c031c4d600998a5438d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M MAINTAINERS
M tests/qtest/meson.build
A tests/qtest/sse-timer-test.c
Log Message:
-----------
tests/qtest/sse-timer-test: Add simple test of the SSE counter
Add a simple qtest to exercise the new system counter device in the
SSE-300.
We'll add tests of the system timer device here too, so this includes
scaffolding (register definitions, etc) for those.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219144617.4782-45-peter.maydell@linaro.org
Commit: f277d1c373edab24530e2c13b35323019dd12bce
https://github.com/qemu/qemu/commit/f277d1c373edab24530e2c13b35323019dd12bce
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M tests/qtest/sse-timer-test.c
Log Message:
-----------
tests/qtest/sse-timer-test: Test the system timer
Add a test which tests various parts of the functionality of the
SSE system timer.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: bf7ca80386cd361a429c8eef4798bd2afe0219dc
https://github.com/qemu/qemu/commit/bf7ca80386cd361a429c8eef4798bd2afe0219dc
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M tests/qtest/sse-timer-test.c
Log Message:
-----------
tests/qtest/sse-timer-test: Test counter scaling changes
Test that when we change the scaling of the system counter that the
system timer responds appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 80485d88f90777648519ec39eb25f6f5ca28a80b
https://github.com/qemu/qemu/commit/80485d88f90777648519ec39eb25f6f5ca28a80b
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu_tcg.c
Log Message:
-----------
target/arm: Restrict v7A TCG cpus to TCG accel
KVM requires the target cpu to be at least ARMv8 architecture
(support on ARMv7 has been dropped in commit 82bf7ae84ce:
"target/arm: Remove KVM support for 32-bit Arm hosts").
A KVM-only build won't be able to run TCG cpus, move the
v7A CPU definitions to cpu_tcg.c.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210306151801.2388182-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a7b5dffb2a58282bcebdd9b294b0e986abddc396
https://github.com/qemu/qemu/commit/a7b5dffb2a58282bcebdd9b294b0e986abddc396
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/dma/Kconfig
M hw/dma/meson.build
A hw/dma/xlnx_csu_dma.c
A include/hw/dma/xlnx_csu_dma.h
Log Message:
-----------
hw/dma: Implement a Xilinx CSU DMA model
ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
crash. This is observed when testing VxWorks 7.
This adds a Xilinx CSU DMA model and the implementation is based on
https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c.
The DST part of the model is verified along with ZynqMP GQSPI model.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-2-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 78407ba993962820d8709a0e3911cd955adcbb6e
https://github.com/qemu/qemu/commit/78407ba993962820d8709a0e3911cd955adcbb6e
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
hw/arm: xlnx-zynqmp: Clean up coding convention issues
There are some coding convention warnings in xlnx-zynqmp.c and
xlnx-zynqmp.h, as reported by:
$ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h
$ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 12e8d8bac2308f4b015f4a1295da06a22b311de6
https://github.com/qemu/qemu/commit/12e8d8bac2308f4b015f4a1295da06a22b311de6
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/arm/Kconfig
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
link of GQSPI to CSU DMA.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-4-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4ff0fa08ae1b8924dad1355dc51605d7eb6020e8
https://github.com/qemu/qemu/commit/4ff0fa08ae1b8924dad1355dc51605d7eb6020e8
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/ssi/xilinx_spips.c
Log Message:
-----------
hw/ssi: xilinx_spips: Clean up coding convention issues
There are some coding convention warnings in xilinx_spips.c,
as reported by:
$ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-5-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 45ddc397e0c1fea02163380786dfe0e253c7609d
https://github.com/qemu/qemu/commit/45ddc397e0c1fea02163380786dfe0e253c7609d
Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/ssi/xilinx_spips.c
M include/hw/ssi/xilinx_spips.h
Log Message:
-----------
hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
Now that the Xilinx CSU DMA model is implemented, the existing
DMA related dead codes in the ZynqMP QSPI are useless and should
be removed. The maximum register number is also updated to only
include the QSPI registers.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c2bdb23d50bbd703dfd8457f83c9b70888729fc6
https://github.com/qemu/qemu/commit/c2bdb23d50bbd703dfd8457f83c9b70888729fc6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/timer/renesas_tmr.c
Log Message:
-----------
hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
The #defines INTERNAL and CASCADING represent different possible
values for the TCCR.CSS register field; prefix them with CSS_ to make
this more obvious, before we add more defines to represent the
other possible values of the field in the next commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219223241.16344-2-peter.maydell@linaro.org
Commit: da2140183ac3a04b1ccb861aeac1f2c048c71b66
https://github.com/qemu/qemu/commit/da2140183ac3a04b1ccb861aeac1f2c048c71b66
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M hw/timer/renesas_tmr.c
Log Message:
-----------
hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
The read_tcnt() function calculates the TCNT register values for the
two channels of the timer module; it sets these up in the local
tcnt[] array, and eventually returns either one or both of them,
depending on whether the access is 8 or 16 bits. However, not all of
the code paths through this function set both elements of this array:
if the guest has programmed the TCCR.CSS register fields to values
which are either documented as not to be used or which QEMU does not
implement, then the function will return uninitialized data. (This
was spotted by Coverity.)
Add the missing CSS cases to this code, so that we return a
consistent value instead of uninitialized data, and so the code
structure indicates what's happening.
Fixes: CID 1429976
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210219223241.16344-3-peter.maydell@linaro.org
Commit: bd5664de7e6c3b793bde3c3344060536dc5d71b5
https://github.com/qemu/qemu/commit/bd5664de7e6c3b793bde3c3344060536dc5d71b5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-10 (Wed, 10 Mar 2021)
Changed paths:
M MAINTAINERS
M docs/devel/clocks.rst
M docs/system/arm/mps2.rst
M hw/adc/npcm7xx_adc.c
M hw/arm/Kconfig
M hw/arm/armsse.c
M hw/arm/mps2-tz.c
M hw/arm/xlnx-zynqmp.c
M hw/char/cadence_uart.c
M hw/char/ibex_uart.c
M hw/char/pl011.c
M hw/core/clock.c
M hw/core/qdev-clock.c
M hw/dma/Kconfig
M hw/dma/meson.build
A hw/dma/xlnx_csu_dma.c
M hw/mips/cps.c
M hw/misc/Kconfig
A hw/misc/armsse-cpu-pwrctrl.c
M hw/misc/bcm2835_cprman.c
M hw/misc/iotkit-secctl.c
M hw/misc/iotkit-sysctl.c
M hw/misc/iotkit-sysinfo.c
M hw/misc/meson.build
M hw/misc/mps2-fpgaio.c
M hw/misc/mps2-scc.c
M hw/misc/npcm7xx_clk.c
M hw/misc/npcm7xx_pwm.c
M hw/misc/trace-events
M hw/misc/zynq_slcr.c
M hw/ssi/xilinx_spips.c
M hw/timer/Kconfig
M hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/cmsdk-apb-timer.c
M hw/timer/meson.build
M hw/timer/npcm7xx_timer.c
M hw/timer/renesas_tmr.c
A hw/timer/sse-counter.c
A hw/timer/sse-timer.c
M hw/timer/trace-events
M hw/watchdog/cmsdk-apb-watchdog.c
A include/hw/arm/armsse-version.h
M include/hw/arm/armsse.h
M include/hw/arm/xlnx-zynqmp.h
M include/hw/clock.h
A include/hw/dma/xlnx_csu_dma.h
A include/hw/misc/armsse-cpu-pwrctrl.h
M include/hw/misc/iotkit-secctl.h
M include/hw/misc/iotkit-sysctl.h
M include/hw/misc/iotkit-sysinfo.h
M include/hw/misc/mps2-fpgaio.h
M include/hw/qdev-clock.h
M include/hw/ssi/xilinx_spips.h
A include/hw/timer/sse-counter.h
A include/hw/timer/sse-timer.h
M target/arm/cpu.c
M target/arm/cpu_tcg.c
M target/mips/cpu.c
M tests/qtest/meson.build
A tests/qtest/sse-timer-test.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20210308-1' into staging
* Add new mps3-an547 board
* target/arm: Restrict v7A TCG cpus to TCG accel
* Implement a Xilinx CSU DMA model
* hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
# gpg: Signature made Mon 08 Mar 2021 17:32:02 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210308-1: (54 commits)
hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt()
hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_
hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips
hw/ssi: xilinx_spips: Clean up coding convention issues
hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI
hw/arm: xlnx-zynqmp: Clean up coding convention issues
hw/dma: Implement a Xilinx CSU DMA model
target/arm: Restrict v7A TCG cpus to TCG accel
tests/qtest/sse-timer-test: Test counter scaling changes
tests/qtest/sse-timer-test: Test the system timer
tests/qtest/sse-timer-test: Add simple test of the SSE counter
docs/system/arm/mps2.rst: Document the new mps3-an547 board
hw/arm/mps2-tz: Add new mps3-an547 board
hw/arm/mps2-tz: Make initsvtor0 setting board-specific
hw/arm/mps2-tz: Support running APB peripherals on different clock
hw/misc/mps2-scc: Implement changes for AN547
hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate
hw/arm/mps2-tz: Make UART overflow IRQ board-specific
hw/arm/armsse: Add SSE-300 support
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/a557b00469bc...bd5664de7e6c
- [Qemu-commits] [qemu/qemu] 5ee0ab: clock: Add ClockEvent parameter to callbacks,
Peter Maydell <=