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[Qemu-commits] [qemu/qemu] 707b45: tcg/aarch64: Fix constant subtraction
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 707b45: tcg/aarch64: Fix constant subtraction in tcg_out_a... |
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Date: |
Tue, 09 Mar 2021 03:21:52 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 707b45a2475e25709f0dee00f8fdf39d346ed21e
https://github.com/qemu/qemu/commit/707b45a2475e25709f0dee00f8fdf39d346ed21e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Fix constant subtraction in tcg_out_addsub2
An hppa guest executing
0x000000000000e05c: ldil L%10000,r4
0x000000000000e060: ldo 0(r4),r4
0x000000000000e064: sub r3,r4,sp
produces
---- 000000000000e064 000000000000e068
sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0
after folding and constant propagation. Then we hit
tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed.
because aimm is in fact -16, but unsigned.
The ((bl < 0) ^ sub) condition which negates bl is incorrect and will
always lead to this abort. If the constant is positive, sub will make
it negative; if the constant is negative, sub will keep it negative.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6c2c7772f69bcd7e7a88308fd6aaf19debb7ada4
https://github.com/qemu/qemu/commit/6c2c7772f69bcd7e7a88308fd6aaf19debb7ada4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Fix I3617_CMLE0
Fix a typo in the encodeing of the cmle (zero) instruction.
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d81bad24dfea6ec0331599de1f31d822aba9dae1
https://github.com/qemu/qemu/commit/d81bad24dfea6ec0331599de1f31d822aba9dae1
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Fix generation of "scalar" vector operations
For some vector operations, "1D" is not a valid type, and there
are separate instructions for the 64-bit scalar operation.
Tested-by: Stefan Weil <sw@weilnetz.de>
Buglink: https://bugs.launchpad.net/qemu/+bug/1916112
Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0
https://github.com/qemu/qemu/commit/dc09f047eddec8f4a1991c4f5f4a428d7aa3f2c0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Use exec/cpu_ldst.h interfaces
Use the provided cpu_ldst.h interfaces. This fixes the build vs
the unconverted uses of g2h(), adds missed memory trace events,
and correctly recognizes when a SIGSEGV belongs to the guest via
set_helper_retaddr().
Fixes: 3e8f1628e864
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: db6b7d0c6936cd209e3e8d95aea61ad29ceef5e6
https://github.com/qemu/qemu/commit/db6b7d0c6936cd209e3e8d95aea61ad29ceef5e6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Split out tcg_raise_tb_overflow
Allow other places in tcg to restart with a smaller tb.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0610067ec032eb7fab3c3f68ec3fea5adbf4ec40
https://github.com/qemu/qemu/commit/0610067ec032eb7fab3c3f68ec3fea5adbf4ec40
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Manage splitwx in tc_ptr_to_region_tree by hand
The use in tcg_tb_lookup is given a random pc that comes from the pc
of a signal handler. Do not assert that the pointer is already within
the code gen buffer at all, much less the writable mirror of it.
Fixes: db0c51a3803
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c764f8cc2ca6cbdd16dd6dfdce0cff0ac25559fd
https://github.com/qemu/qemu/commit/c764f8cc2ca6cbdd16dd6dfdce0cff0ac25559fd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Merge identical cases in generation (arithmetic opcodes)
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 1/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 1e9ac76625535047ba5e5864d2f199dae502e623
https://github.com/qemu/qemu/commit/1e9ac76625535047ba5e5864d2f199dae502e623
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Merge identical cases in generation (exchange opcodes)
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 2/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: da9a5e0b413fbfdbc938918a9519cb124cb3ec95
https://github.com/qemu/qemu/commit/da9a5e0b413fbfdbc938918a9519cb124cb3ec95
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Merge identical cases in generation (deposit opcode)
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 3/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-4-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 88c3e909039b94507fe3c58bc291c97b638d694d
https://github.com/qemu/qemu/commit/88c3e909039b94507fe3c58bc291c97b638d694d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Merge identical cases in generation (conditional opcodes)
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 4/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a73605a73c67943855b633e13bf3a2275126dd0a
https://github.com/qemu/qemu/commit/a73605a73c67943855b633e13bf3a2275126dd0a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Merge identical cases in generation (load/store opcodes)
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge
cases that are identical between 32-bit and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org>
[PMD: Split patch as 5/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210218232840.1760806-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a7391bc0157bf20f41ff14dbf2ec66ec60cb633c
https://github.com/qemu/qemu/commit/a7391bc0157bf20f41ff14dbf2ec66ec60cb633c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r8
Use explicit casts for ext8u opcodes, and allow truncation
to happen with the store for st8 opcodes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9758c8cbbdeaefc4e065c7614a6d10c9db810c25
https://github.com/qemu/qemu/commit/9758c8cbbdeaefc4e065c7614a6d10c9db810c25
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r8s
Use explicit casts for ext8s opcodes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0dd0170cb1f697f4d8b8d6fa0243363f22c9649e
https://github.com/qemu/qemu/commit/0dd0170cb1f697f4d8b8d6fa0243363f22c9649e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r16
Use explicit casts for ext16u opcodes, and allow truncation
to happen with the store for st16 opcodes, and with the call
for bswap16 opcodes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 994edd6719c32b7e9fec15d6f098ae8b899f806b
https://github.com/qemu/qemu/commit/994edd6719c32b7e9fec15d6f098ae8b899f806b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r16s
Use explicit casts for ext16s opcodes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 984ae87314e24fa272d9c868307236b5caff0a30
https://github.com/qemu/qemu/commit/984ae87314e24fa272d9c868307236b5caff0a30
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r32
Use explicit casts for ext32u opcodes, and allow truncation
to happen for other users.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dcf2af266237457344d18a52083b37e3affeb5a7
https://github.com/qemu/qemu/commit/dcf2af266237457344d18a52083b37e3affeb5a7
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove tci_read_r32s
Use explicit casts for ext32s opcodes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 09c8b8b90d1bf8b5a48190f190440cf49b6cead9
https://github.com/qemu/qemu/commit/09c8b8b90d1bf8b5a48190f190440cf49b6cead9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Reduce use of tci_read_r64
In all cases restricted to 64-bit hosts, tcg_read_r is
identical. We retain the 64-bit symbol for the single
case of INDEX_op_qemu_st_i64.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: dd2bb20e41d54410a685517f41ec86cc7d87b36b
https://github.com/qemu/qemu/commit/dd2bb20e41d54410a685517f41ec86cc7d87b36b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge basic arithmetic operations
This includes add, sub, mul, and, or, xor.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 13a1d64045cf0ea6a0f1f317dfaaa3995d9d4863
https://github.com/qemu/qemu/commit/13a1d64045cf0ea6a0f1f317dfaaa3995d9d4863
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge extension operations
This includes ext8s, ext8u, ext16s, ext16u.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fe2b13bb7c5c53791de5ce1d94c74440f9758cbf
https://github.com/qemu/qemu/commit/fe2b13bb7c5c53791de5ce1d94c74440f9758cbf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge bswap operations
This includes bswap16 and bswap32.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9e9acb7b348570f8a9ed62fcbad299424fe61501
https://github.com/qemu/qemu/commit/9e9acb7b348570f8a9ed62fcbad299424fe61501
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge mov, not and neg operations
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6f04cb1c8f481cf02fbc4657fefba985a1fe725f
https://github.com/qemu/qemu/commit/6f04cb1c8f481cf02fbc4657fefba985a1fe725f
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-runtime.c
M include/exec/tb-lookup.h
Log Message:
-----------
accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
Having a function return either and valid TB and some system state
seems excessive. It will make the subsequent re-factoring easier if we
lookup the current state where we are.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c0ae396a81e13e5a09846f86a702bc61733a8885
https://github.com/qemu/qemu/commit/c0ae396a81e13e5a09846f86a702bc61733a8885
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-runtime.c
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/exec/tb-lookup.h
M softmmu/physmem.c
Log Message:
-----------
accel/tcg: move CF_CLUSTER calculation to curr_cflags
There is nothing special about this compile flag that doesn't mean we
can't just compute it with curr_cflags() which we should be using when
building a new set.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: bf253ac606de4a934e41ba178bf4f1338c554cec
https://github.com/qemu/qemu/commit/bf253ac606de4a934e41ba178bf4f1338c554cec
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-runtime.c
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/exec/tb-lookup.h
Log Message:
-----------
accel/tcg: drop the use of CF_HASH_MASK and rename params
We don't really deal in cf_mask most of the time. The one time it's
relevant is when we want to remove an invalidated TB from the QHT
lookup. Everywhere else we should be looking up things without
CF_INVALID set.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 872ebd884dd68ecef4c6f9f86c5da519f18bd31e
https://github.com/qemu/qemu/commit/872ebd884dd68ecef4c6f9f86c5da519f18bd31e
Author: Alex Bennée <alex.bennee@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M include/exec/exec-all.h
Log Message:
-----------
include/exec: lightly re-arrange TranslationBlock
Lets make sure all the flags we compare when looking up blocks are
together in the same place.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6cc9d67c6f682cf04eea2d6e64a252b63a7eccdf
https://github.com/qemu/qemu/commit/6cc9d67c6f682cf04eea2d6e64a252b63a7eccdf
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-03-06 (Sat, 06 Mar 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops-mttcg.c
M accel/tcg/tcg-accel-ops-rr.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/tcg-accel-ops.h
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/hw/core/cpu.h
M linux-user/main.c
M linux-user/sh4/signal.c
M linux-user/syscall.c
Log Message:
-----------
accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
The primary motivation is to remove a dozen insns along
the fast-path in tb_lookup. As a byproduct, this allows
us to completely remove parallel_cpus.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 74fd46ed44f60a230804dc1050bae76eb9420ecb
https://github.com/qemu/qemu/commit/74fd46ed44f60a230804dc1050bae76eb9420ecb
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-03-08 (Mon, 08 Mar 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops-mttcg.c
M accel/tcg/tcg-accel-ops-rr.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/tcg-accel-ops.h
M accel/tcg/tcg-runtime.c
M accel/tcg/translate-all.c
M include/exec/exec-all.h
M include/exec/tb-lookup.h
M include/hw/core/cpu.h
M linux-user/main.c
M linux-user/sh4/signal.c
M linux-user/syscall.c
M softmmu/physmem.c
M tcg/aarch64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210306' into
staging
TCI build fix and cleanup
Streamline tb_lookup
Fixes for tcg/aarch64
# gpg: Signature made Sat 06 Mar 2021 21:34:46 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210306: (27 commits)
accel/tcg: Precompute curr_cflags into cpu->tcg_cflags
include/exec: lightly re-arrange TranslationBlock
accel/tcg: drop the use of CF_HASH_MASK and rename params
accel/tcg: move CF_CLUSTER calculation to curr_cflags
accel/tcg: rename tb_lookup__cpu_state and hoist state extraction
tcg/tci: Merge mov, not and neg operations
tcg/tci: Merge bswap operations
tcg/tci: Merge extension operations
tcg/tci: Merge basic arithmetic operations
tcg/tci: Reduce use of tci_read_r64
tcg/tci: Remove tci_read_r32s
tcg/tci: Remove tci_read_r32
tcg/tci: Remove tci_read_r16s
tcg/tci: Remove tci_read_r16
tcg/tci: Remove tci_read_r8s
tcg/tci: Remove tci_read_r8
tcg/tci: Merge identical cases in generation (load/store opcodes)
tcg/tci: Merge identical cases in generation (conditional opcodes)
tcg/tci: Merge identical cases in generation (deposit opcode)
tcg/tci: Merge identical cases in generation (exchange opcodes)
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/229a834518b9...74fd46ed44f6