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[Qemu-commits] [qemu/qemu] 6f0377: target/riscv: Declare csr_ops[] with

From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 6f0377: target/riscv: Declare csr_ops[] with a known size
Date: Fri, 05 Mar 2021 02:48:20 -0800 
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 6f03770daccaffc39a4ce61854ab126020374112
      
https://github.com/qemu/qemu/commit/6f03770daccaffc39a4ce61854ab126020374112
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Declare csr_ops[] with a known size

csr_ops[] is currently declared with an unknown size in cpu.h.
Since the array size is known, let's do a complete declaration.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a033d8008d1b2b35332597eacc92a1a4b14121ad
      
https://github.com/qemu/qemu/commit/a033d8008d1b2b35332597eacc92a1a4b14121ad
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/misc/sifive_u_otp.c

  Log Message:
  -----------
  hw/misc: sifive_u_otp: Use error_report() when block operation fails

At present when blk_pread() / blk_pwrite() fails, a guest error
is logged, but this is not really a guest error. Change to use
error_report() instead.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1611026585-29971-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 454d1e7cf29ff04c11acbef79fdeecdb07118d81
      
https://github.com/qemu/qemu/commit/454d1e7cf29ff04c11acbef79fdeecdb07118d81
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
    M roms/opensbi

  Log Message:
  -----------
  roms/opensbi: Upgrade from v0.8 to v0.9

Upgrade OpenSBI from v0.8 to v0.9 and the pre-built bios images.

The v0.9 release includes the following commits:

35bc810 docs/platform: Update QEMU parameter for fw_payload
78afe11 config.mk: Update QEMU run command for generic and sifive fu540 
platforms
ec3e5b1 docs/platform: sifive_fu540: Update U-Boot instructions
7d61a68 README.md: fix markdown link formatting
a5f9104 lib/utils: fdt: Update FDT expand size to 1024 for reserved memory node
ec1abf6 include: sbi_bitops: Remove dead shift assignment in ffs/fls
8e47649 lib: Add sbi_strncmp implementation
2845d2d lib: utils: Add a macro in libfdt_env.h for strncmp
2cfd2fc lib: utils: Use strncmp in fdt_parse_hart_id()
937caee lib: sbi_misaligned_ldst: Determine transformed instruction length 
correctly
4b18a2a firmware: fw_base: Improve exception stack setup in trap handler
9d56961 lib: sbi_trap: Fix hstatus.SPVP update in sbi_trap_redirect()
d7f87d9 platform: kendryte/k210: fixup FDT
e435ba0 lib: sbi_init: Avoid thundering hurd problem with coldboot_lock
4f3bad6 lib: sbi: Handle the case where MTVAL has illegal instruction address
7b0b289 lib: sbi: Remove redundant SBI_HART_HAS_PMP feature
74d1db7 lib: sbi: Improve PMP CSR detection and progamming
2c341f7 lib: sbi: Detect and print MHPM counters at boot-time
162d453 include: sbi: Few cosmetic changes in riscv_encoding.h
ebc8ebc lib: sbi: Improve HPM CSR read/write emulation
dcb10c0 lib: sbi: Don't handle VS-mode ecall in sbi_trap_handler()
bef63d6 include: Rename ECALL defines to match latest RISC-V spec
c1c7c3e lib: sbi_trap: Allow M-mode to M-mode ECALLs
6734304 lib: sbi: Allow specifying start mode to sbi_hsm_hart_start() API
7ccf6bf lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API
9f935a4 lib: utils: Improve fdt_cpu_fixup() implementation
172fa16 lib: sbi: Ensure coldboot HART supports next privilege mode
aaeca7e platform: generic: Don't mark non-MMU HARTs as invalid
7701ea1 lib: sbi: Fix PMP CSR detection
79bf80b lib: sbi_scratch: typo scatch
a04c465 makefile: fix clean directive
af4b50f Makefile: Build ELF, BIN and LD script in platform build directory
6ca0969 firmware: Add common FW_FDT_PATH compile-time option
9c07c51 firmware: Remove FW_PAYLOAD_FDT_PATH compile-time option
e9a4bfb Makefile: Allow padding zeros when converting DTB to C source
a0f2d4a platform: kendryte/k210: Add some padding for FDT fixups
dbeeacb include: sbi: Remove redundant includes from sbi_platform.h
a12d46a include: sbi: Remove pmp_region callbacks from sbi_platform_operations
a126886 lib: sbi: Configure PMP late in coldboot and warmboot path
f81d6f6 lib: sbi: Remove redundant hartid parameter from sbi_hart_init()
8b65005 include: sbi: Make hartmask pointer const in sbi_hartmask_test_hart()
b1678af lib: sbi: Add initial domain support
e73b92d lib: sbi: Extend sbi_hsm_hart_started_mask() for domains
3a30d2c lib: sbi: Extend sbi_hsm_hart_start() for domains
530e95b lib: sbi: Optimize sbi_hsm_hart_started_mask() implementation
3e20037 lib: sbi: Extend sbi_system_reset() for domains
5edbb7c lib: utils: Update fdt_reserved_memory_fixup() to use current domain
5fd99db lib: utils: Update fdt_cpu_fixup() to use current domain
e856462 lib: sbi: Remove redundant sbi_hart_pmp_xyz() functions
c10c30b lib: sbi: Configure PMP based on domain memory regions
c347408 lib: sbi: Display domain details in boot prints
fdf5d5c docs: Add initial documentation for domain support
74c0ea1 lib: utils: Implement "ranges" property parsing
bf21632 lib: sbi: Detect PMP granularity and number of address bits
a809f40 lib: sbi: Improve boot time print with additional PMP information
914f81f Makefile: Add option to use toolchain default ABI and ISA string
48616b3 lib: sbi: Improve boot prints in cold boot sequence
781cafd docs: fix a typo error
54a7734 include: sbi: Add SBI SRST extension related defines
c4acc60 include: sbi: Remove opensbi specific reset type defines
da07479 platform: Remove dummy system reset functions
5c429ae lib: sbi: Improve system reset platform operations
548d03e lib: sbi: Implement System Reset (SRST) SBI extension
2677324 firmware: fw_base: Optimize trap handler for RV32 systems
8d2edc4 lib: sbi: Fix sbi_hart_switch_mode() for u-mode
3d921fa lib: sbi: Fix typo in sbi_domain_finalize()
4e37022 lib: sbi: Fix domain_count check in sbi_domain_finalize()
c709d40 lib: sbi: Auto start domain only if boot HART within limits
c1f6d89 include: sbi: Use lower bits for domain memory region permissions
62ea4f4 lib: sbi: Override domain boot HART when coldboot HART assigned to it
555e737 lib: sbi: Add error prints in sbi_domain_finalize()
9b65dca include: sbi: Add domains_init() platform operation
c0d2baa docs: Add domain device tree binding documentation
ba741ea lib: utils: Add helper routines to populate domains from FDT
4fffb53 platform: generic: Populate domains from FDT
e7da0b4 lib: utils/libfdt: Upgrade to v1.6.0 release
2179777 lib: utils: Allow FDT domain iteration functions to fail
7baccfc lib: sbi: Add function to register new domain
6fc1986 lib: utils: Remove fdt_domain_get() function
a029bd9 lib: sbi: Remove domain_get() platform callback function
7dcb1e1 lib: sbi: Fix sign-extension in sbi_misaligned_load_handler()
80bc506 lib: sbi: Replace args with trap registers in ecall handler
b7df5e4 lib: sbi: Introduce sbi_trap_exit() API
12394a2 lib: sbi: Allow custom local TLB flush function
0d49c3b lib: utils: Fix shakti uart implementation
db56341 lib: sbi: Allow platforms to provide root domain memory regions
e884416 include: sbi: No need to pack struct sbi_trap_regs
386eba2 include: sbi: No need to pack struct sbi_scratch
1bbf361 include: sbi: Don't pack struct sbi_platform and sbi_platform_operations
da5293f platform: template: Fix compile error
234ed8e include: Bump-up version to 0.9

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: 20210119234438.10132-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 43a9658889c32a2d8b4a4c1f7ac6a7f7741aa781
      
https://github.com/qemu/qemu/commit/43a9658889c32a2d8b4a4c1f7ac6a7f7741aa781
  Author: Yifei Jiang <jiangyifei@huawei.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    A target/riscv/arch_dump.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/meson.build

  Log Message:
  -----------
  target-riscv: support QMP dump-guest-memory

Add the support needed for creating prstatus elf notes. This allows
us to use QMP dump-guest-memory.

Now ELF notes of RISC-V only contain prstatus elf notes.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 20210201124458.1248-2-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 10509e1095c9910957c4c2b93bbf2f1833838e68
      
https://github.com/qemu/qemu/commit/10509e1095c9910957c4c2b93bbf2f1833838e68
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block: m25p80: Add ISSI SPI flash support

This adds the ISSI SPI flash support. The number of dummy cycles in
fast read, fast read dual output and fast read quad output commands
is currently using the default 8. Likewise, the same default value
is used for fast read dual/quad I/O command. Per the datasheet [1],
the number of dummy cycles is configurable, but this is not modeled
at present.

For flash whose size is larger than 16 MiB, the sequence of 3-byte
address along with EXTADD bit in the bank address register (BAR) is
not supported. We assume that guest software always uses op codes
with 4-byte address sequence. Fortunately, this is the case for both
U-Boot and Linux spi-nor drivers.

QPI (Quad Peripheral Interface) that supports 2-cycle instruction
has different default values for dummy cycles of fast read family
commands, and is unsupported at the time being.

[1] http://www.issi.com/WW/pdf/25LP-WP256.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 62d1076678a4c3d2385cc492283061b710bb0a60
      
https://github.com/qemu/qemu/commit/62d1076678a4c3d2385cc492283061b710bb0a60
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block: m25p80: Add various ISSI flash information

This updates the flash information table to include various ISSI
flashes that are supported by upstream U-Boot and Linux kernel.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
      
https://github.com/qemu/qemu/commit/0694dabe9763847f3010b54ab3ec7d367d2f0ff0
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/ssi/Kconfig
    M hw/ssi/meson.build
    A hw/ssi/sifive_spi.c
    A include/hw/ssi/sifive_spi.h

  Log Message:
  -----------
  hw/ssi: Add SiFive SPI controller support

This adds the SiFive SPI controller model for the FU540 SoC.
The direct memory-mapped SPI flash mode is unsupported.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 145b299139da92fb1b1048b393865bc96597d6b9
      
https://github.com/qemu/qemu/commit/145b299139da92fb1b1048b393865bc96597d6b9
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Add QSPI0 controller and connect a flash

This adds the QSPI0 controller to the SoC, and connects an ISSI
25WP256 flash to it. The generation of corresponding device tree
source fragment is also added.

Since the direct memory-mapped mode is not supported by the SiFive
SPI model, the <reg> property does not populate the second group
which represents the memory mapped address of the SPI flash.

With this commit, upstream U-Boot for the SiFive HiFive Unleashed
board can boot on QEMU 'sifive_u' out of the box. This allows users
to develop and test the recommended RISC-V boot flow with a real
world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to
L2LIM, then U-Boot SPL loads the payload from SPI flash that is
combined with OpenSBI fw_dynamic firmware and U-Boot proper.

Specify machine property `msel` to 6 to allow booting from the SPI
flash. U-Boot spl is directly loaded via `-bios`, and subsequent
payload is stored in the SPI flash image. Example command line:

$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \
    -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 722f1352b6c248ead94efd77ff5726aa0cba949b
      
https://github.com/qemu/qemu/commit/722f1352b6c248ead94efd77ff5726aa0cba949b
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/Kconfig
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card

This adds the QSPI2 controller to the SoC, and connects an SD
card to it. The generation of corresponding device tree source
fragment is also added.

Specify machine property `msel` to 11 to boot the same upstream
U-Boot SPL and payload image for the SiFive HiFive Unleashed board.
Note subsequent payload is stored in the SD card image.

$ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \
    -bios u-boot-spl.bin -drive file=sdcard.img,if=sd

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8e3c886870d4cc5c3b93f2817edcc3699af31adc
      
https://github.com/qemu/qemu/commit/8e3c886870d4cc5c3b93f2817edcc3699af31adc
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value

All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1921e4276d4e0e41df8c4be87fbbdd5d121bdfdc
      
https://github.com/qemu/qemu/commit/1921e4276d4e0e41df8c4be87fbbdd5d121bdfdc
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M docs/system/targets.rst

  Log Message:
  -----------
  docs/system: Sort targets in alphabetical order

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-8-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d6d98968142f9c2541ee28e239d6a95b117499da
      
https://github.com/qemu/qemu/commit/d6d98968142f9c2541ee28e239d6a95b117499da
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    A docs/system/target-riscv.rst
    M docs/system/targets.rst

  Log Message:
  -----------
  docs/system: Add RISC-V documentation

Add RISC-V system emulator documentation for generic information.
`Board-specific documentation` and `RISC-V CPU features` are only
a placeholder and will be added in the future.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210126060007.12904-9-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 01153d2b606ccef3414cbedd3309e7c965902b6b
      
https://github.com/qemu/qemu/commit/01153d2b606ccef3414cbedd3309e7c965902b6b
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    A docs/system/riscv/sifive_u.rst
    M docs/system/target-riscv.rst

  Log Message:
  -----------
  docs/system: riscv: Add documentation for sifive_u machine

This adds detailed documentation for RISC-V `sifive_u` machine,
including the following information:

- Supported devices
- Hardware configuration information
- Boot options
- Machine-specific options
- Running Linux kernel
- Running VxWorks kernel
- Running U-Boot, and with an alternate configuration

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 20210126060007.12904-10-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 6b9409ba5f79b93411f32d2589fd3a3a3e4e62e2
      
https://github.com/qemu/qemu/commit/6b9409ba5f79b93411f32d2589fd3a3a3e4e62e2
  Author: Laurent Vivier <laurent@vivier.eu>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/rtc/goldfish_rtc.c

  Log Message:
  -----------
  goldfish_rtc: re-arm the alarm after migration

After a migration the clock offset is updated, but we also
need to re-arm the alarm if needed.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201220112615.933036-7-laurent@vivier.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 4fcad931566c86514f56bbbeda1e30858b331f34
      
https://github.com/qemu/qemu/commit/4fcad931566c86514f56bbbeda1e30858b331f34
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add a SiFive machine section

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 
6bc077e5ae4a9512c8adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com


  Commit: 732612856a8948a6ba1148322651743aa963b51c
      
https://github.com/qemu/qemu/commit/732612856a8948a6ba1148322651743aa963b51c
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: Drop 'struct MemmapEntry'

There is already a MemMapEntry type defined in hwaddr.h. Let's drop
the RISC-V defined `struct MemmapEntry` and use the existing one.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210220144807.819-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 2fa3c7b6eee83d3ca1bd3d69669cf2fb8a11223b
      
https://github.com/qemu/qemu/commit/2fa3c7b6eee83d3ca1bd3d69669cf2fb8a11223b
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()

`link_up` is never used in gpex_pcie_init(). Drop it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210220144807.819-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: cfeb8a17c88f50c2a6dbf1cd4b9a279df5a30ec9
      
https://github.com/qemu/qemu/commit/cfeb8a17c88f50c2a6dbf1cd4b9a279df5a30ec9
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Limit RAM size in a 32-bit system

RV32 supports 34-bit physical address hence the maximum RAM size
should be limited. Limit the RAM size to 10 GiB, which leaves
some room for PCIe high mmio space.

For 32-bit host, this is not needed as machine->ram_size cannot
represent a RAM size that big. Use a #if size test to only do
the size limitation for the 64-bit host.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210220144807.819-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 19800265d407f09f333cf80dba3e975eb7bc1872
      
https://github.com/qemu/qemu/commit/19800265d407f09f333cf80dba3e975eb7bc1872
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-03-04 (Thu, 04 Mar 2021)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  hw/riscv: virt: Map high mmio for PCIe

Some peripherals require 64-bit PCI address, so let's map the high
mmio space for PCIe.

For RV32, the address is hardcoded to below 4 GiB from the highest
accessible physical address. For RV64, the base address depends on
top of RAM and is aligned to its size which is using 16 GiB for now.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210220144807.819-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 9a7beaad3dbba982f7a461d676b55a5c3851d312
      
https://github.com/qemu/qemu/commit/9a7beaad3dbba982f7a461d676b55a5c3851d312
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-03-05 (Fri, 05 Mar 2021)

  Changed paths:
    M MAINTAINERS
    A docs/system/riscv/sifive_u.rst
    A docs/system/target-riscv.rst
    M docs/system/targets.rst
    M hw/block/m25p80.c
    M hw/misc/sifive_u_otp.c
    M hw/riscv/Kconfig
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M hw/rtc/goldfish_rtc.c
    M hw/ssi/Kconfig
    M hw/ssi/meson.build
    A hw/ssi/sifive_spi.c
    M include/hw/riscv/sifive_u.h
    A include/hw/ssi/sifive_spi.h
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.elf
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.elf
    M roms/opensbi
    A target/riscv/arch_dump.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/meson.build

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging

RISC-V PR for 6.0

This PR is a collection of RISC-V patches:
 - Improvements to SiFive U OTP
 - Upgrade OpenSBI to v0.9
 - Support the QMP dump-guest-memory
 - Add support for the SiFive SPI controller (sifive_u)
 - Initial RISC-V system documentation
 - A fix for the Goldfish RTC
 - MAINTAINERS updates
 - Support for high PCIe memory in the virt machine

# gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210304:
  hw/riscv: virt: Map high mmio for PCIe
  hw/riscv: virt: Limit RAM size in a 32-bit system
  hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()
  hw/riscv: Drop 'struct MemmapEntry'
  MAINTAINERS: Add a SiFive machine section
  goldfish_rtc: re-arm the alarm after migration
  docs/system: riscv: Add documentation for sifive_u machine
  docs/system: Add RISC-V documentation
  docs/system: Sort targets in alphabetical order
  hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
  hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card
  hw/riscv: sifive_u: Add QSPI0 controller and connect a flash
  hw/ssi: Add SiFive SPI controller support
  hw/block: m25p80: Add various ISSI flash information
  hw/block: m25p80: Add ISSI SPI flash support
  target-riscv: support QMP dump-guest-memory
  roms/opensbi: Upgrade from v0.8 to v0.9
  hw/misc: sifive_u_otp: Use error_report() when block operation fails
  target/riscv: Declare csr_ops[] with a known size

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fe352f5c0056...9a7beaad3dbb
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