[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] ac9b01: hw/mips: loongson3: Drop 'struct Memm
|
From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] ac9b01: hw/mips: loongson3: Drop 'struct MemmapEntry' |
|
Date: |
Sun, 21 Feb 2021 13:17:53 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: ac9b0117d545d4e318c6827251fdf654385188f5
https://github.com/qemu/qemu/commit/ac9b0117d545d4e318c6827251fdf654385188f5
Author: Bin Meng <bin.meng@windriver.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/mips/loongson3_bootp.h
M hw/mips/loongson3_virt.c
Log Message:
-----------
hw/mips: loongson3: Drop 'struct MemmapEntry'
There is already a MemMapEntry type defined in hwaddr.h. Let's drop
the loongson3 defined `struct MemmapEntry` and use the existing one.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210122122404.11970-1-bmeng.cn@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3ebbf86128f5607831ba5a3dec8bac02271a9390
https://github.com/qemu/qemu/commit/3ebbf86128f5607831ba5a3dec8bac02271a9390
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
A hw/mips/bootloader.c
M hw/mips/meson.build
A include/hw/mips/bootloader.h
Log Message:
-----------
hw/mips: Add a bootloader helper
Add a bootloader helper to generate simple bootloaders for kernel.
It can help us reduce inline hex hack and also keep MIPS release 6
compatibility easier.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210127065424.114125-2-jiaxun.yang@flygoat.com>
[PMD: Restricted bl_reg enum to C source,
inverted bl_gen_write() args,
added license in hw/mips/bootloader.h]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 4d0c59fa07933f64ba8df9da1f76154869ba9425
https://github.com/qemu/qemu/commit/4d0c59fa07933f64ba8df9da1f76154869ba9425
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/mips/fuloong2e.c
Log Message:
-----------
hw/mips/fuloong2e: Use bl_gen_kernel_jump to generate bootloaders
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201215064507.30148-2-jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split original patch as one for each machine (here fuloong2e)]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 112658eb26382a7e9717d8bef716ac4675799719
https://github.com/qemu/qemu/commit/112658eb26382a7e9717d8bef716ac4675799719
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Use bl_gen_kernel_jump to generate bootloaders
Replace embedded binary with generated code.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201215064507.30148-2-jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split original patch as one for each machine (here boston)]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 283eae174e4944e4f26160aceeec444a13e52b03
https://github.com/qemu/qemu/commit/283eae174e4944e4f26160aceeec444a13e52b03
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Use bootloader helper to set GCRs
Translate embedded assembly into IO writes which is more
readable.
Also hardcode cm_base at boot time instead of reading from CP0.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210127065424.114125-5-jiaxun.yang@flygoat.com>
[PMD: Kept code comments]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 6902759965852ae9fc099bb32af8f8dc4a098733
https://github.com/qemu/qemu/commit/6902759965852ae9fc099bb32af8f8dc4a098733
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/intc/loongson_liointc.c
Log Message:
-----------
hw/intc/loongson_liointc: Fix per core ISR handling
Per core ISR is a set of 32-bit registers spaced by 8 bytes.
This patch fixed calculation of it's size and also added check
of alignment at reading & writing.
Fixes: Coverity CID 1438965 and CID 1438967
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Huacai Chen <chenhuacai@kernel.org>
Message-Id: <20210112012527.28927-1-jiaxun.yang@flygoat.com>
[PMD: Added Coverity CID]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: c0928e6ddcbd8c8e8d3d2901eb0fd076ee2dd17d
https://github.com/qemu/qemu/commit/c0928e6ddcbd8c8e8d3d2901eb0fd076ee2dd17d
Author: Jiaxun Yang <jiaxun.yang@flygoat.com>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M MAINTAINERS
A tests/acceptance/machine_mips_loongson3v.py
Log Message:
-----------
tests/acceptance: Test PMON with Loongson-3A1000 CPU
Test booting of PMON bootloader on loongson3-virt platform.
$ (venv) AVOCADO_ALLOW_UNTRUSTED_CODE=1 \
avocado --show=app,console \
run -t machine:loongson3-virt tests/acceptance
Fetching asset from
tests/acceptance/machine_mips_loongson3v.py:MipsLoongson3v.test_pmon_serial_console
JOB ID : 8e202b3727847c9104d0d3d6546ed225d35f6706
JOB LOG :
/home/flygoat/avocado/job-results/job-2021-01-12T10.02-8e202b3/job.log
(1/1)
tests/acceptance/machine_mips_loongson3v.py:MipsLoongson3v.test_pmon_serial_console:
console: PMON2000 MIPS Initializing. Standby...
console: 00000000Jump to 9fc
console: Init Memory done.
console: The uncache data is:
console: 00000000: 5555555555555555
console: 00000008: aaaaaaaaaaaaaaaa
console: 00000010: 3333333333333333
console: 00000018: cccccccccccccccc
console: 00000020: 7777777777777777
console: 00000028: 8888888888888888
console: 00000030: 1111111111111111
console: 00000038: eeeeeeeeeeeeeeee
console: The cached data is:
console: 00000000: 5555555555555555
console: 00000008: aaaaaaaaaaaaaaaa
console: 00000010: 3333333333333333
console: 00000018: cccccccccccccccc
console: 00000020: 7777777777777777
console: 00000028: 8888888888888888
console: 00000030: 1111111111111111
console: 00000038: eeeeeeeeeeeeeeee
console: Copy PMON to execute location...
console: start = 0x8f900000
console: s0 = 0x30300000
console: _edata = 0x8f989010
console: _end = 0x8f98a028copy text section done.
console: Copy PMON to execute location done.
console: sp=8f8fc000
console: Uncompressing
Bios............................................................................OK,Booting
Bios
console: FREQ
console: DONE
console: DEVI
console: ENVI
console: MAPV
console: NVRAM@8f7ff898
console: STDV
console: 80100000: memory between 8f7ff400-8f800000 is already been
allocated,heap is already above this point
console: SBDD
console: P12PCIH
console: PCIH
console: PCID
console: setting up 1 bus
console: PCI bus 0 slot 1: probe...completed
console: PCI bus 0 slot 1/0: vendor/product: 0x106b/0x003f (serialbus, USB,
interface: 0x10, revision: 0x00)
console: PCI bus 0 slot 1/0: reg 0x10 = 0xffffff00
console: PCI bus 0 slot 2: probe...completed
console: PCI bus 0 slot 2/0: vendor/product: 0x1af4/0x1000 (network, ethernet,
interface: 0x00, revision: 0x00)
console: PCI bus 0 slot 2/0: reg 0x10 = 0xffffffe1
console: PCI bus 0 slot 2/0: reg 0x14 = 0xfffff000
console: PCI bus 0 slot 2/0: reg 0x20 = 0xffffc00c
console: PCI bus 0 slot 2/0: reg 0x30 = 0xfffc0000
console: PCI bus 0 slot 3: probe...completed
console: PCI bus 0 slot 4: probe...completed
console: PCI bus 0 slot 5: probe...completed
console: PCI bus 0 slot 6: probe...completed
console: PCI bus 0 slot 7: probe...completed
console: PCI bus 0 slot 8: probe...completed
console: PCI bus 0 slot 9: probe...completed
console: PCI bus 0 slot 10: probe...completed
console: PCI bus 0 slot 11: probe...completed
console: PCI bus 0 slot 12: probe...completed
console: PCI bus 0 slot 13: probe...completed
console: PCI bus 0 slot 14: probe...completed
console: PCI bus 0 slot 15: probe...completed
console: PCI bus 0 slot 16: probe...completed
console: PCI bus 0 slot 17: probe...completed
console: PCI bus 0 slot 18: probe...completed
console: PCI bus 0 slot 19: probe...completed
console: PCI bus 0 slot 20: probe...completed
console: PCI bus 0 slot 21: probe...completed
console: PCI bus 0 slot 22: probe...completed
console: PCI bus 0 slot 23: probe...completed
console: PCI bus 0 slot 24: probe...completed
console: PCI bus 0 slot 25: probe...completed
console: PCI bus 0 slot 26: probe...completed
console: PCI bus 0 slot 27: probe...completed
console: PCI bus 0 slot 28: probe...completed
console: PCI bus 0 slot 29: probe...completed
console: PCI bus 0 slot 30: probe...completed
console: PCI bus 0 slot 31: probe...completed
console: PCIS
console: PCIR
console: PCIW
console: PCI bus 0 slot 2/0: mem @0x40000000, reg 0x30 262144 bytes
console: PCI bus 0 slot 2/0: mem @0x40040000, reg 0x20 16384 bytes
console: PCI bus 0 slot 2/0: mem @0x40044000, reg 0x14 4096 bytes
console: PCI bus 0 slot 1/0: mem @0x40045000, reg 0x10 256 bytes
console: PCI bus 0 slot 2/0: exp @0x40000000, 262144 bytes
console: PCI bus 0 slot 2/0: i/o @0x00004000, reg 0x10 32 bytes
console: NETI
console: RTCL
console: PCID
console: VGAI
console: memorysize=c000000,base=8f6ff508,sysMem=8f6ef500
console: in setup_int_vect!done!VESA
console: vga bios init failed, rc=-1
console: in configure
console: mainbus0 (root)
console: localbus0 at mainbus0
console: loopdev0 at mainbus0pcibr0 at mainbus0
console: pci0 at pcibr0 bus 0
console: ohci0 at pci0 dev 1 function 0 vendor/product: 0x106b/0x003f
(serialbus, USB, interface: 0x10, revision: 0x00)usb base addr : 0xc0045000,
bus_base is : 0xc0000000
console: OHCI revision: 0x00000010
console: RH: a: 0x00000203 b: 0x00000000
console: early period(0x0)
console: OHCI 8c01ec00 initialized ok
console: New Device 0
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 110
console: bDeviceClass =9
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: set address 1
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 110
console: bDeviceClass =9
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: idVendor =0
console: idProduct =0
console: bcdDevice =0
console: iManufacturer=0
console: iProduct =1
console: iSerialNumber=0
console: bNumConfigurations=1
console: usb_get_descriptor
console: usb_get_descriptor
console: get_conf_no 0 Result 25, wLength 25
console: if 0, ep 0
console: bLength=9
console: bDescriptorType=2
console: wTotalLength=19
console: bNumInterfaces=1
console: bConfigurationValue=1
console: iConfiguration=0
console: bmAttributes=40
console: MaxPower=0
console: 09 04 00 00 01 09 00 00 00 07 05 81 03 02 00 ff
console: ##EP epmaxpacketin[1] = 2
console: set configuration 1
console: new device strings: Mfr=0, Product=1, SerialNumber=0
console: USB device number 1 default language ID 0x409
console: Manufacturer
console: Product OHCI Root Hub
console: SerialNumber
console: New Device 1
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 200
console: bDeviceClass =0
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: set address 2
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 200
console: bDeviceClass =0
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: idVendor =627
console: idProduct =1
console: bcdDevice =0
console: iManufacturer=1
console: iProduct =4
console: iSerialNumber=b
console: bNumConfigurations=1
console: usb_get_descriptor
console: usb_get_descriptor
console: get_conf_no 0 Result 34, wLength 34
console: unknown Description Type : 21
console: 09 21 11 01 00 01 22 3F 00
console: if 0, ep 0
console: bLength=9
console: bDescriptorType=2
console: wTotalLength=22
console: bNumInterfaces=1
console: bConfigurationValue=1
console: iConfiguration=8
console: bmAttributes=a0
console: MaxPower=32
console: 09 04 00 00 01 03 01 01 00 09 21 11 01 00 01 22 3f 00 07 05 81 03 08
00 0a
console: ##EP epmaxpacketin[1] = 8
console: set configuration 1
console: new device strings: Mfr=1, Product=4, SerialNumber=11
console: USB device number 2 default language ID 0x409
console: Manufacturer QEMU
console: Product QEMU USB Keyboard
console: SerialNumber 68284-0000:00:01.0-1
console: drive at ohci0 devnum 2, Product QEMU USB Keyboard
console: not configured
console: New Device 2
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 200
console: bDeviceClass =0
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: set address 3
console: usb_get_descriptor
console: bLength = 12
console: bDescriptorType =1
console: bcdUSB = 200
console: bDeviceClass =0
console: bDeviceSubClass =0
console: bDeviceProtocol =0
console: bMaxPacketSize0 =8
console: idVendor =627
console: idProduct =1
console: bcdDevice =0
console: iManufacturer=1
console: iProduct =3
console: iSerialNumber=a
console: bNumConfigurations=1
console: usb_get_descriptor
console: usb_get_descriptor
console: get_conf_no 0 Result 34, wLength 34
console: unknown Description Type : 21
console: 09 21 01 00 00 01 22 4A 00
console: if 0, ep 0
console: bLength=9
console: bDescriptorType=2
console: wTotalLength=22
console: bNumInterfaces=1
console: bConfigurationValue=1
console: iConfiguration=7
console: bmAttributes=a0
console: MaxPower=32
console: 09 04 00 00 01 03 00 00 00 09 21 01 00 00 01 22 4a 00 07 05 81 03 08
00 0a
console: ##EP epmaxpacketin[1] = 8
console: set configuration 1
console: new device strings: Mfr=1, Product=3, SerialNumber=10
console: USB device number 3 default language ID 0x409
console: Manufacturer QEMU
console: Product QEMU USB Tablet
console: SerialNumber 28754-0000:00:01.0-2
console: drive at ohci0 devnum 3, Product QEMU USB Tablet
console: not configured
console: drive at ohci0 devnum 1, Product OHCI Root Hub
console: not configured
console: vendor/product: 0x1af4/0x1000 (network, ethernet, interface: 0x00,
revision: 0x00) at pci0 dev 2 function 0 not configured
console: out configure
console: Press <Del> to set BIOS,waiting for 3 seconds here.....
console: devconfig done.
console: ifinit done.
console: domaininit done.
console: init_proc....
console: HSTI
console: SYMI
console: SBDE
console:
[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[
console: [[ [[[[[[[[[ [[[[[ [[[[ [[[[[ [[[[[ [[[[[
[[[[[ [[[[ [[[[[ [[
console: [[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[[ [[[[ [[[ [[[[
[[[ [[[[ [[[ [[[[ [[
console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [ [[[ [[[ [[[[[[[[[[[[
[[[[[[[ [[[[[[ [[[ [ [[[ [[
console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[ [[ [[[ [[[ [[[[[[[
[[[[ [[[[[[ [[[ [[ [[ [[
console: [[ [[[[[[[[ [[[[[[ [[[ [[[[[[ [[[ [[[ [ [[[ [[[[[ [[[[[[[[[[
[[[ [[[[[[ [[[ [[[ [ [[
console: [[ [[[[[[[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[[ [[[ [[[
[[[[ [[[[ [[[ [[[[ [[
console: [[ [[[[ [[[[[ [[[[ [[[[[ [[[[ [[[[[
[[[[[[ [[[[ [[[[[ [[
console: [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[2011
Loongson][[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[
console: Configuration [Bonito,EL,NET,SCSI,IDE]
console: Version: PMON2000 3.3 (Bonito) #0: Tue Dec 22 01:58:09 UTC 2020 commit
b3ece66234adbf7d4e453f0ba4f326c099ac2a76 Author: Jiaxun Yang
<jiaxun.yang@flygoat.com> Date: Tue Dec 22 09:51:10 2020 +0800 .
console: Supported loaders [txt, srec, elf, bin]
console: Supported filesystems [net, fat, fs, disk, iso9660, socket, tty, ram]
console: This software may be redistributed under the BSD copyright.
console: Copyright 2000-2002, Opsycon AB, Sweden.
console: Copyright 2005, ICT CAS.
console: CPU GODSON3 BogoMIPS: 1327
PASS (3.89 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 4.38 s
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210112020708.62922-1-jiaxun.yang@flygoat.com>
[PMD: Set timeout to 60sec, simply test for ''CPU GODSON3 BogoMIPS']
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 0ab8e33a48414e094e74bcc48b0914325def85ac
https://github.com/qemu/qemu/commit/0ab8e33a48414e094e74bcc48b0914325def85ac
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: fetch code with translator_ld
Similarly to commits ae82adc8e29..7f93879e444, use the
translator_ld*() API introduced in commit 409c1a0bf0f
to fetch the code on the MIPS target.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210125105818.2707067-1-f4bug@amsat.org>
Commit: afe2fe4d04d3b260c1802adb59d851905f3bcb3c
https://github.com/qemu/qemu/commit/afe2fe4d04d3b260c1802adb59d851905f3bcb3c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Remove access_type argument from map_address() handler
TLB map_address() handlers don't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-2-f4bug@amsat.org>
Commit: 496892282520d7e55ce3b48b7cdc772199a44ad4
https://github.com/qemu/qemu/commit/496892282520d7e55ce3b48b7cdc772199a44ad4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Remove access_type argument from get_seg_physical_address
get_seg_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-3-f4bug@amsat.org>
Commit: 0230a13793b1b30b6b06fd5be1272556a5880ded
https://github.com/qemu/qemu/commit/0230a13793b1b30b6b06fd5be1272556a5880ded
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Remove access_type arg from get_segctl_physical_address()
get_segctl_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-4-f4bug@amsat.org>
Commit: 935c103490eb628dfd6166819ddbbbde87285e69
https://github.com/qemu/qemu/commit/935c103490eb628dfd6166819ddbbbde87285e69
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Remove access_type argument from get_physical_address()
get_physical_address() doesn't use the 'access_type' argument,
remove it to simplify.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-5-f4bug@amsat.org>
Commit: e78d4ab6aae78c3de2eb324e4dc484ece2f8f090
https://github.com/qemu/qemu/commit/e78d4ab6aae78c3de2eb324e4dc484ece2f8f090
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/cpu.h
Log Message:
-----------
target/mips: Remove unused MMU definitions
Remove these confusing and unused definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-6-f4bug@amsat.org>
Commit: fd305527e3b2dd66240ba2fede5ca3709aeb2392
https://github.com/qemu/qemu/commit/fd305527e3b2dd66240ba2fede5ca3709aeb2392
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/op_helper.c
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Replace magic value by MMU_DATA_LOAD definition
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-7-f4bug@amsat.org>
Commit: 1190c53e822a287f2767ebddf792d290dd760db0
https://github.com/qemu/qemu/commit/1190c53e822a287f2767ebddf792d290dd760db0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/op_helper.c
Log Message:
-----------
target/mips: Let do_translate_address() take MMUAccessType argument
The single caller, HELPER_LD_ATOMIC(), passes MMUAccessType to
do_translate_address(). Let the prototype use it as argument,
as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-9-f4bug@amsat.org>
Commit: 48b28c6a8e9ff64498efa244b1b3ee1bbcd01202
https://github.com/qemu/qemu/commit/48b28c6a8e9ff64498efa244b1b3ee1bbcd01202
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Let cpu_mips_translate_address() take MMUAccessType arg
The single caller, do_translate_address(), passes MMUAccessType
to cpu_mips_translate_address(). Let the prototype use it as
argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-10-f4bug@amsat.org>
Commit: ca354f00047a1065a43286debbb8ead0a6d0fe08
https://github.com/qemu/qemu/commit/ca354f00047a1065a43286debbb8ead0a6d0fe08
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Let raise_mmu_exception() take MMUAccessType argument
Both mips_cpu_tlb_fill() and cpu_mips_translate_address() pass
MMUAccessType to raise_mmu_exception(). Let the prototype use it
as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-11-f4bug@amsat.org>
Commit: 7c6e2049f099e1bbdbf9dbc219be963d1ff509c0
https://github.com/qemu/qemu/commit/7c6e2049f099e1bbdbf9dbc219be963d1ff509c0
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Let get_physical_address() take MMUAccessType argument
All these functions:
- mips_cpu_get_phys_page_debug()
- cpu_mips_translate_address()
- mips_cpu_tlb_fill()
- page_table_walk_refill()
- walk_directory()
call get_physical_address() passing a MMUAccessType type. Let the
prototype use it as argument, as it is stricter than an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-12-f4bug@amsat.org>
Commit: 67b663d6fadaa4755bd9e1263deb36122c2e05b9
https://github.com/qemu/qemu/commit/67b663d6fadaa4755bd9e1263deb36122c2e05b9
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Let get_seg*_physical_address() take MMUAccessType arg
get_physical_address() calls get_seg_physical_address() and
get_segctl_physical_address() passing a MMUAccessType type.
Let the prototypes use it as argument, as it is stricter than
an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-13-f4bug@amsat.org>
Commit: edbd4992fb5d782c858f5196ecb452d61dbc6ab1
https://github.com/qemu/qemu/commit/edbd4992fb5d782c858f5196ecb452d61dbc6ab1
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/internal.h
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType
get_seg_physical_address() calls CPUMIPSTLBContext::map_address()
handlers passing a MMUAccessType type. Update the prototype
handlers to take a MMUAccessType argument, as it is stricter than
an integer.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20210128144125.3696119-14-f4bug@amsat.org>
Commit: bca3763be27adbc12fa65aeab51e429fd75a58cd
https://github.com/qemu/qemu/commit/bca3763be27adbc12fa65aeab51e429fd75a58cd
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/tlb_helper.c
Log Message:
-----------
target/mips: Remove unused 'rw' argument from page_table_walk_refill()
As the 'rw' argument is unused, remove it.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210220202026.2305667-1-f4bug@amsat.org>
Commit: 1e3b675b3e946f5c2b4b1aa96dc6413af8db9f04
https://github.com/qemu/qemu/commit/1e3b675b3e946f5c2b4b1aa96dc6413af8db9f04
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/msa_helper.c
Log Message:
-----------
target/mips: Include missing "tcg/tcg.h" header
Commit 83be6b54123 ("Fix MSA instructions LD.<B|H|W|D> on big endian
host") introduced use of typedef/prototypes declared in "tcg/tcg.h"
without including it. This was not a problem because "tcg/tcg.h" is
pulled in by "exec/cpu_ldst.h". To be able to remove this header
there, we first need to include it here in op_helper.c, else we get:
[222/337] Compiling C object
libqemu-mips-softmmu.fa.p/target_mips_msa_helper.c.o
target/mips/msa_helper.c: In function ‘helper_msa_ld_b’:
target/mips/msa_helper.c:8214:9: error: unknown type name ‘TCGMemOpIdx’
8214 | TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
| ^~~~~~~~~~~
target/mips/msa_helper.c:8224:5: note: in expansion of macro ‘MEMOP_IDX’
8224 | MEMOP_IDX(DF_BYTE)
| ^~~~~~~~~
target/mips/msa_helper.c:8214:26: error: implicit declaration of function
‘make_memop_idx’ [-Werror=implicit-function-declaration]
8214 | TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
| ^~~~~~~~~~~~~~
target/mips/msa_helper.c:8227:18: error: implicit declaration of function
‘helper_ret_ldub_mmu’ [-Werror=implicit-function-declaration]
8227 | pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi,
GETPC());
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210207232310.2505283-4-f4bug@amsat.org>
Commit: 9f5f7691dee18b0a0d6e0d8e291b7c12da85de17
https://github.com/qemu/qemu/commit/9f5f7691dee18b0a0d6e0d8e291b7c12da85de17
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Make cpu_HI/LO registers public
We will access the cpu_HI/LO registers outside of translate.c.
Make them publicly accessible.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-4-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3
https://github.com/qemu/qemu/commit/cefd68f6b1e20639ba95d4eb8b4a99b5e00d93d3
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/cpu.h
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Promote 128-bit multimedia registers as global ones
The cpu::mmr[] array contains the upper halves of 128-bit GPR
registers. While they are only used by the R5900 CPU, the
concept is generic and could be used by another MIPS implementation.
Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global.
When the code is similar to the GPR lower halves, move it
close by.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-5-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: b5b63d43a0d2b3c3a914a30b0443ce3f04c0db5c
https://github.com/qemu/qemu/commit/b5b63d43a0d2b3c3a914a30b0443ce3f04c0db5c
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Rename 128-bit upper halve GPR registers
TCG displays the upper halve registers with the same name
as their lower halves. Rename the upper halves with the
'[hi]' suffix.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-6-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4
https://github.com/qemu/qemu/commit/61f4e0ec0dcedd2ade310aeb536ae750a0f7eef4
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/translate.c
M target/mips/translate.h
Log Message:
-----------
target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-7-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3bc313c4f51a213ebcb172286b575f8d591c634f
https://github.com/qemu/qemu/commit/3bc313c4f51a213ebcb172286b575f8d591c634f
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M target/mips/translate.c
Log Message:
-----------
target/mips: Use GPR move functions in gen_HILO1_tx79()
We have handy functions to access GPR. Use gen_store_gpr() for
Move From HI/LO Register and gen_load_gpr() for Move To opcodes.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-8-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 6be6e4bc7697ec902c536140b3d28938f2f68ba6
https://github.com/qemu/qemu/commit/6be6e4bc7697ec902c536140b3d28938f2f68ba6
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Move superio memory region to SuperIOConfig struct
The superio memory region holds the io space index/data registers used
to access the superio config registers that are implemented in struct
SuperIOConfig. To keep these related things together move the memory
region to SuperIOConfig and rename it accordingly.
Also remove the unused "data" member of SuperIOConfig which is not
needed as we store actual data values in the regs array.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id:
<dc3c4e7632716ca73c10506bd02ee93b39c28705.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 94349bffda0ae13b4d7c9c042bd6c94fc6a5b9bf
https://github.com/qemu/qemu/commit/94349bffda0ae13b4d7c9c042bd6c94fc6a5b9bf
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Reorganise code
Move lines around so that object definitions become consecutive and
not scattered around. This brings functions belonging to an object
together so it's clearer what is defined and what parts belong to
which object.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<9f942989dba46fc1c23b881f6cb135948f818c2f.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 911629e6d3773a8adeab48b488fadece0d7996b1
https://github.com/qemu/qemu/commit/911629e6d3773a8adeab48b488fadece0d7996b1
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
Log Message:
-----------
vt82c686: Fix SMBus IO base and configuration registers
The base address of the SMBus io ports and its enabled status is set
by registers in the PCI config space but this was not correctly
emulated. Instead the SMBus registers were mapped on realize to the
base address set by a property to the address expected by fuloong2e
firmware.
Fix the base and config register handling to more closely model
hardware which allows to remove the property and allows the guest to
control this mapping. Do all this in reset instead of realize so it's
correctly updated on reset.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id:
<f2ca2ad5f08ba8cee07afd9d67b4e75cda21db09.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 35e360ed67400f792fae88627268440a6326a511
https://github.com/qemu/qemu/commit/35e360ed67400f792fae88627268440a6326a511
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/trace-events
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Make vt82c686-pm an I/O tracing region
Previously just an empty RAM region was mapped on realize, now we add
an empty io range logging access instead. I think the pm timer should
be hooked up here but not sure guests need it. PMON on fuloong2e sets
a base address but does not seem to enable region; the pegasos2
firmware pokes some regs but continues anyway so don't know if
anything would make use of these facilities. Therefore this is just a
clean up of previous state for now and not intending to fully
implement missing functionality which could be done later if some
guests need it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 1/4
(make 'vt82c686-pm' an I/O tracing region)]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 40a0bba1e3feff9c3aa05e56db07eec9e72393e5
https://github.com/qemu/qemu/commit/40a0bba1e3feff9c3aa05e56db07eec9e72393e5
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Correct vt82c686-pm I/O size
Section "Offset 4B-48 – Power Management I/O Base" describes:
Port Address for the base of the 128-byte Power
Management I/O Register block.
Correct the vt82c686-pm I/O region size.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 2/4, reduced size to 128B]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 9af8e529b91d6e8a0c2911281b39179f184f09bf
https://github.com/qemu/qemu/commit/9af8e529b91d6e8a0c2911281b39179f184f09bf
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Correctly reset all registers to default values on reset
Reset the registers in the DeviceReset() handler which is called
on each device reset, not in DeviceRealize() which is called once.
Bit 0 of 'Power Mgmt I/O Base' register (offset 0x48) is always set.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split original patch, this is part 3/4 (move to reset), document]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3ab1eea6bced10e314625cfa13fc9c9fa586486f
https://github.com/qemu/qemu/commit/3ab1eea6bced10e314625cfa13fc9c9fa586486f
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Fix up power management io base and config
Similar to the SMBus io registers there is a power management io range
that is set via similar base address reg and enable bit. Some handling
of this was already there but with several problems: using the wrong
registers and bits, wrong size range, not acually updating mapping and
handling reset correctly, nor emulating any of the actual io
registers. Some of these errors are fixed up here.
After this patch we use the correct base address register, enable bit
and region size and allow guests to map/unmap this region, but we
still don't emulate any of the registers in this range.
PMD notes regarding the Configuration Space Power Management Registers:
- 0x40 General Configuration 0
- 0x41 General Configuration 1
. Bit 7: I/O Enable for ACPI I/O Base
- 0x48 Power Mgmt I/O Base
. Bit 0: Always set
. Bits 7-15: Power Management I/O Register Base Address
(this explains the change 0xffc0 -> 0xff80)
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<cff9b2442d3e2e1cfbdcbc2dfbb559031b4b1cc1.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch, this is part 4/4, added notes]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 084bf4b41d40ead572e45c47c6e5fca5b3eb997c
https://github.com/qemu/qemu/commit/084bf4b41d40ead572e45c47c6e5fca5b3eb997c
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Set user_creatable=false for VT82C686B_PM
This device is part of the multifunction VIA superio/south bridge chip
so not useful in itself.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id:
<d0a806fed5e8055aee4fcf5b2f4790e6dd0f9dc6.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: e1a69736e5985ac2d45977d4d6482ab9cca71db8
https://github.com/qemu/qemu/commit/e1a69736e5985ac2d45977d4d6482ab9cca71db8
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
M include/hw/isa/vt82c686.h
M include/hw/pci/pci_ids.h
Log Message:
-----------
vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on
it
The vt82c686b-pm model can be shared between VT82C686B and VT8231. The
only difference between the two is the device id in what we emulate so
make an abstract via-pm model by renaming appropriately and add types
for vt82c686b-pm and vt8231-pm based on it.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<34969fc7be984fa070479bfb9f748993a0aef31b.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 9859ad1c4b6d6d505ce202e42fd5a74a7ef6e149
https://github.com/qemu/qemu/commit/9859ad1c4b6d6d505ce202e42fd5a74a7ef6e149
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Simplify vt82c686b_realize()
Remove unneeded variables and setting value to 0 on zero initialised
data and replace check for error with error_fatal. Rationalise loop
that sets PCI config header fields read only.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<e4caf35ca10a68f5c74ae3f93fa0bcfa9457beea.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 3dc31cb849053c2748e0cf0595bd25475572b28a
https://github.com/qemu/qemu/commit/3dc31cb849053c2748e0cf0595bd25475572b28a
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
M hw/mips/fuloong2e.c
Log Message:
-----------
vt82c686: Move creation of ISA devices to the ISA bridge
Currently the ISA devices that are part of the VIA south bridge,
superio chip are wired up by board code. Move creation of these ISA
devices to the VIA ISA bridge model so that board code does not need
to access ISA bus. This also allows vt82c686b-superio to be made
internal to vt82c686 which allows implementing its configuration via
registers in subseqent commits.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id:
<bf9400cc8e4ddd3129aa5678de4d3cf38384805f.1610223397.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: c953bf7118261a6af8f306108d5072b5d4efccd0
https://github.com/qemu/qemu/commit/c953bf7118261a6af8f306108d5072b5d4efccd0
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Remove index field of SuperIOConfig
Remove the separate index value from SuperIOConfig and store
the index at reg 0 which is reserved and returns 0 on read.
This simplifies the object state.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch in 5, this is part 1/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 2b98dca9571a1019fcc97694b6220f9301dddd7d
https://github.com/qemu/qemu/commit/2b98dca9571a1019fcc97694b6220f9301dddd7d
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Reduce indentation by returning early
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split patch original in 5, this is part 2/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: b7741b7742573aff43398dd34c6bd4c6eed0fce7
https://github.com/qemu/qemu/commit/b7741b7742573aff43398dd34c6bd4c6eed0fce7
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Simplify by returning earlier
By returning earlier we can remove the 'can_write' boolean variable.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split original patch in 5, this is part 3/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 2c4c556e0616a003c37d53f005b7bc1b65b234ab
https://github.com/qemu/qemu/commit/2c4c556e0616a003c37d53f005b7bc1b65b234ab
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Log superio_cfg unimplemented accesses
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: Split original patch in 5, this is part 4/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: cc2b4550115baf77d556341f17eb464d18953cee
https://github.com/qemu/qemu/commit/cc2b4550115baf77d556341f17eb464d18953cee
Author: BALATON Zoltan <balaton@eik.bme.hu>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Fix superio_cfg_{read,write}() functions
These functions are memory region callbacks so we have to check
against relative address not the mapped address.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id:
<15b2968fd300a12d06b42368d084f6f80d3c3be5.1610223397.git.balaton@eik.bme.hu>
[PMD: Split original patch in 5, this is part 5/5]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Commit: 00d8ba9e0d62ea1c7459c25aeabf9c8bb7659462
https://github.com/qemu/qemu/commit/00d8ba9e0d62ea1c7459c25aeabf9c8bb7659462
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-02-21 (Sun, 21 Feb 2021)
Changed paths:
M MAINTAINERS
M hw/intc/loongson_liointc.c
M hw/isa/trace-events
M hw/isa/vt82c686.c
A hw/mips/bootloader.c
M hw/mips/boston.c
M hw/mips/fuloong2e.c
M hw/mips/loongson3_bootp.h
M hw/mips/loongson3_virt.c
M hw/mips/meson.build
M include/hw/isa/vt82c686.h
A include/hw/mips/bootloader.h
M include/hw/pci/pci_ids.h
M target/mips/cpu.h
M target/mips/internal.h
M target/mips/msa_helper.c
M target/mips/op_helper.c
M target/mips/tlb_helper.c
M target/mips/translate.c
M target/mips/translate.h
A tests/acceptance/machine_mips_loongson3v.py
Log Message:
-----------
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into
staging
MIPS patches queue
- Drop redundant struct MemmapEntry (Bin)
- Fix for Coverity CID 1438965 and 1438967 (Jiaxun)
- Add MIPS bootloader API (Jiaxun)
- Use MIPS bootloader API on fuloong2e and boston machines (Jiaxun)
- Add PMON test for Loongson-3A1000 CPU (Jiaxun)
- Convert to translator API (Philippe)
- MMU cleanups (Philippe)
- Promote 128-bit multimedia registers as global ones (Philippe)
- Various cleanups/fixes on the VT82C686B southbridge (Zoltan)
# gpg: Signature made Sun 21 Feb 2021 18:43:57 GMT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/mips-20210221: (43 commits)
vt82c686: Fix superio_cfg_{read,write}() functions
vt82c686: Log superio_cfg unimplemented accesses
vt82c686: Simplify by returning earlier
vt82c686: Reduce indentation by returning early
vt82c686: Remove index field of SuperIOConfig
vt82c686: Move creation of ISA devices to the ISA bridge
vt82c686: Simplify vt82c686b_realize()
vt82c686: Make vt82c686b-pm an abstract base class and add vt8231-pm based on
it
vt82c686: Set user_creatable=false for VT82C686B_PM
vt82c686: Fix up power management io base and config
vt82c686: Correctly reset all registers to default values on reset
vt82c686: Correct vt82c686-pm I/O size
vt82c686: Make vt82c686-pm an I/O tracing region
vt82c686: Fix SMBus IO base and configuration registers
vt82c686: Reorganise code
vt82c686: Move superio memory region to SuperIOConfig struct
target/mips: Use GPR move functions in gen_HILO1_tx79()
target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers
target/mips: Rename 128-bit upper halve GPR registers
target/mips: Promote 128-bit multimedia registers as global ones
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/4115aec9af2a...00d8ba9e0d62