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[Qemu-commits] [qemu/qemu] af903c: target/arm: Don't migrate CPUARMState
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] af903c: target/arm: Don't migrate CPUARMState.features |
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Date: |
Fri, 12 Feb 2021 02:07:53 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: af903caed9fc62cc60a589da75e61ea8008c8265
https://github.com/qemu/qemu/commit/af903caed9fc62cc60a589da75e61ea8008c8265
Author: Aaron Lindsay <aaron@os.amperecomputing.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Don't migrate CPUARMState.features
As feature flags are added or removed, the meanings of bits in the
`features` field can change between QEMU versions, causing migration
failures. Additionally, migrating the field is not useful because it is
a constant function of the CPU being used.
Fixes: LP:1914696
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5
https://github.com/qemu/qemu/commit/10d0ef3e6cfe228df4b2d3e27325f1b0e2b71fd5
Author: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix SCR RES1 handling
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
to 1 only when there is no support for AArch32 at EL1 or above.
The reset value will be 0x30 only if the CPU is AArch64-only; if there
is support for AArch32 at EL1 or above, it will be reset to 0.
Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
is supported at EL1 or above.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 377a3ba25c984303029588e9032002235f157d34
https://github.com/qemu/qemu/commit/377a3ba25c984303029588e9032002235f157d34
Author: Hao Wu <wuhaotsh@google.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M hw/arm/npcm7xx.c
Log Message:
-----------
hw/arm: Remove GPIO from unimplemented NPCM7XX
NPCM7XX GPIO devices have been implemented in hw/gpio/npcm7xx-gpio.c. So
we removed them from the unimplemented devices list.
Reviewed-by: Doug Evans<dje@google.com>
Reviewed-by: Tyrong Ting<kfting@nuvoton.com>
Signed-off-by: Hao Wu<wuhaotsh@google.com>
Message-id: 20210129005845.416272-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: dc8b18534ea1dcc90d80ad9a61a3b0aa7eb312fb
https://github.com/qemu/qemu/commit/dc8b18534ea1dcc90d80ad9a61a3b0aa7eb312fb
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Add support for FEAT_DIT, Data Independent Timing
Add support for FEAT_DIT. DIT (Data Independent Timing) is a required
feature for ARMv8.4. Since virtual machine execution is largely
nondeterministic and TCG is outside of the security domain, it's
implemented as a NOP.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210208065700.19454-2-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f944a854ce4007000accf7c191b5b52916947198
https://github.com/qemu/qemu/commit/f944a854ce4007000accf7c191b5b52916947198
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
cpsr has been treated as being the same as spsr, but it isn't.
Since PSTATE_SS isn't in cpsr, remove it and move it into env->pstate.
This allows us to add support for CPSR_DIT, adding helper functions
to merge SPSR_ELx to and from CPSR.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210208065700.19454-3-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2bf1eff9e9125a3d73901991dcfb9cb2ace03be1
https://github.com/qemu/qemu/commit/2bf1eff9e9125a3d73901991dcfb9cb2ace03be1
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210208065700.19454-4-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5385320c2b3183f2e18dbc55c23ecba9272500c2
https://github.com/qemu/qemu/commit/5385320c2b3183f2e18dbc55c23ecba9272500c2
Author: Rebecca Cran <rebecca@nuviainc.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
Enable FEAT_DIT for the "max" 32-bit CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210208065700.19454-5-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 932a8d1f11ccfbf196ee6fb4a5ccdf274b14a78c
https://github.com/qemu/qemu/commit/932a8d1f11ccfbf196ee6fb4a5ccdf274b14a78c
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/musca.c
M hw/misc/arm_integrator_debug.c
M hw/timer/arm_timer.c
M include/hw/dma/pl080.h
M include/hw/misc/arm_integrator_debug.h
M include/hw/ssi/pl022.h
Log Message:
-----------
arm: Update infocenter.arm.com URLs
Update infocenter.arm.com URLs for various pieces of Arm
documentation to the new developer.arm.com equivalents. (There is a
redirection in place from the old URLs, but we might as well update
our comments in case the redirect ever disappears in future.)
This patch covers all the URLs which are not MPS2/SSE-200/IoTKit
related (those are dealt with in a different patch).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210205171456.19939-1-peter.maydell@linaro.org
Commit: e6a41a045c298538d303cd8fe8d7ae29a0c066ad
https://github.com/qemu/qemu/commit/e6a41a045c298538d303cd8fe8d7ae29a0c066ad
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
accel/tcg: Add URL of clang bug to comment about our workaround
In cpu_exec() we have a longstanding workaround for compilers which
do not correctly implement the part of the sigsetjmp()/siglongjmp()
spec which requires that local variables which are not changed
between the setjmp and the longjmp retain their value.
I recently ran across the upstream clang bug report for this; add a
link to it to the comment describing the workaround, and generally
expand the comment, so that we have a reasonable chance in future of
understanding why it's there and determining when we can remove it,
assuming clang eventually fixes the bug.
Remove the /* buggy compiler */ comments on the #else and #endif:
they don't add anything to understanding and are somewhat misleading
since they're sandwiching the code path for *non*-buggy compilers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210129130330.30820-1-peter.maydell@linaro.org
Commit: 4565d826163d2e3a4ca3a5ebf3904e6b3b04a487
https://github.com/qemu/qemu/commit/4565d826163d2e3a4ca3a5ebf3904e6b3b04a487
Author: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M hw/arm/xlnx-versal.c
Log Message:
-----------
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
Use nr_apu_cpus in favor of hard coding 2.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20210210142048.3125878-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
https://github.com/qemu/qemu/commit/d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621
Author: Daniel Müller <muellerd@fb.com>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correctly initialize MDCR_EL2.HPMN
When working with performance monitoring counters, we look at
MDCR_EL2.HPMN as part of the check whether a counter is enabled. This
check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no
counters are "enabled" for < EL2.
That's in violation of the Arm specification, which states that
> On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in
> PMCR_EL0.N
That's also what a comment in the code acknowledges, but the necessary
adjustment seems to have been forgotten when support for more counters
was added.
This change fixes the issue by setting the reset value to PMCR.N, which
is four.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: eac92d316351b855ba79eb374dd21cc367f1f9c1
https://github.com/qemu/qemu/commit/eac92d316351b855ba79eb374dd21cc367f1f9c1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-02-11 (Thu, 11 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M hw/arm/aspeed_ast2600.c
M hw/arm/musca.c
M hw/arm/npcm7xx.c
M hw/arm/xlnx-versal.c
M hw/misc/arm_integrator_debug.c
M hw/timer/arm_timer.c
M include/hw/dma/pl080.h
M include/hw/misc/arm_integrator_debug.h
M include/hw/ssi/pl022.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper-a64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/machine.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20210211-1' into staging
target-arm queue:
* Correctly initialize MDCR_EL2.HPMN
* versal: Use nr_apu_cpus in favor of hard coding 2
* accel/tcg: Add URL of clang bug to comment about our workaround
* Add support for FEAT_DIT, Data Independent Timing
* Remove GPIO from unimplemented NPCM7XX
* Fix SCR RES1 handling
* Don't migrate CPUARMState.features
# gpg: Signature made Thu 11 Feb 2021 19:56:40 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210211-1:
target/arm: Correctly initialize MDCR_EL2.HPMN
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
accel/tcg: Add URL of clang bug to comment about our workaround
arm: Update infocenter.arm.com URLs
target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate
target/arm: Add support for FEAT_DIT, Data Independent Timing
hw/arm: Remove GPIO from unimplemented NPCM7XX
target/arm: Fix SCR RES1 handling
target/arm: Don't migrate CPUARMState.features
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/c973f06521b0...eac92d316351