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[Qemu-commits] [qemu/qemu] 8e43c5: tcg/s390: Fix compare instruction fro
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 8e43c5: tcg/s390: Fix compare instruction from extended-im... |
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Date: |
Sat, 06 Feb 2021 06:28:52 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 8e43c5a1f289ce002e9d26108af658c8d064dea1
https://github.com/qemu/qemu/commit/8e43c5a1f289ce002e9d26108af658c8d064dea1
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/s390/tcg-target.c.inc
Log Message:
-----------
tcg/s390: Fix compare instruction from extended-immediate facility
The code is currently comparing c2 to the type promotion of
uint32_t and int32_t. That is, the conversion rules are as:
(common_type) c2 == (common_type) (uint32_t)
(is_unsigned
? (uint32_t)c2
: (uint32_t)(int32_t)c2)
In the signed case we lose the desired sign extensions because
of the argument promotion rules of the ternary operator.
Solve the problem by doing the round-trip parsing through the
intermediate type and back to the desired common type (all at
one expression).
Fixes: a534bb15f30 ("tcg/s390: Use constant pool for cmpi")
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
Reported-by: Richard W.M. Jones <rjones@redhat.com>
Suggested-by: David Hildenbrand <david@redhat.com>
Suggested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210204182902.1742826-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 37c8c531d61e34b69750aaeb61f7a0d5e9d9de3d
https://github.com/qemu/qemu/commit/37c8c531d61e34b69750aaeb61f7a0d5e9d9de3d
Author: Philippe Mathieu-Daudé <f4bug@amsat.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M include/exec/cpu-defs.h
Log Message:
-----------
exec/cpu-defs: Remove TCG backends dependency
"exec/cpu-defs.h" contains generic CPU definitions for the
TCG frontends (mostly related to TLB). TCG backends definitions
aren't relevant here.
See tcg/README description:
4) Backend
tcg-target.h contains the target specific definitions. tcg-target.c.inc
contains the target specific code; it is #included by tcg/tcg.c, rather
than being a standalone C file.
So far only "tcg/tcg.h" requires these headers.
Remove the "target-tcg.h" header dependency on TCG frontends, so we
don't have to rebuild all frontends when hacking a single backend.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210204191423.1754158-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2dfa2f18717f3294e8612637a60fc58576ef55b5
https://github.com/qemu/qemu/commit/2dfa2f18717f3294e8612637a60fc58576ef55b5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Do not convert TCGArg to temps that are not temps
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd
argument is an integer, not a temporary, which now tickles
an assert added in e89b28a6350.
Previously, the value computed into v2 would be garbage for
rotli_vec, but as the value was unused it caused no harm.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c6fbea47664466e526e40300568324ef77e5f2cc
https://github.com/qemu/qemu/commit/c6fbea47664466e526e40300568324ef77e5f2cc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M configure
Log Message:
-----------
configure: Fix --enable-tcg-interpreter
The configure option was backward, and we failed to
pass the value on to meson.
Fixes: 23a77b2d18b ("build-system: clean up TCG/TCI configury")
Tested-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 13e71f08bf66646d9818f6430f337c965b241746
https://github.com/qemu/qemu/commit/13e71f08bf66646d9818f6430f337c965b241746
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M include/exec/exec-all.h
M tcg/tcg-common.c
M tcg/tci.c
Log Message:
-----------
tcg/tci: Make tci_tb_ptr thread-local
Each thread must have its own pc, even under TCI.
Remove the GETPC ifdef, because GETPC is always available for
helpers, and thus is always required. Move the assignment
under INDEX_op_call, because the value is only visible when
we make a call to a helper function.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204014509.882821-6-richard.henderson@linaro.org>
Commit: 49a5a75f3e74cf0cc2ae85003f0509334a69eef2
https://github.com/qemu/qemu/commit/49a5a75f3e74cf0cc2ae85003f0509334a69eef2
Author: Stefan Weil <sw@weilnetz.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Implement INDEX_op_ld16s_i32
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20210128024814.2056958-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cbec0754bed0d890a277746c68ce193cd3f1070d
https://github.com/qemu/qemu/commit/cbec0754bed0d890a277746c68ce193cd3f1070d
Author: Stefan Weil <sw@weilnetz.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Implement INDEX_op_ld8s_i64
That TCG opcode is used by debian-buster (arm64) running ffmpeg:
qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20210128020425.2055454-1-sw@weilnetz.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9592e8974f364daa372247c9240fd9e08b70c2ac
https://github.com/qemu/qemu/commit/9592e8974f364daa372247c9240fd9e08b70c2ac
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Inline tci_write_reg32s into the only caller
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 475a15611f1581f6d395c0be683dfa8893fe7d88
https://github.com/qemu/qemu/commit/475a15611f1581f6d395c0be683dfa8893fe7d88
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Inline tci_write_reg8 into its callers
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 43c8a4027953b170f718bb8507f2494f8279c24c
https://github.com/qemu/qemu/commit/43c8a4027953b170f718bb8507f2494f8279c24c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Inline tci_write_reg16 into the only caller
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 85bbbf7088dae27a110d6669801694af127c5158
https://github.com/qemu/qemu/commit/85bbbf7088dae27a110d6669801694af127c5158
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Inline tci_write_reg32 into all callers
For a 64-bit TCI, the upper bits of a 32-bit operation are
undefined (much like a native ppc64 32-bit operation). It
simplifies everything if we don't force-extend the result.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5410e4347b7914aa1f2aa29120cd976a9acd5b1d
https://github.com/qemu/qemu/commit/5410e4347b7914aa1f2aa29120cd976a9acd5b1d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Inline tci_write_reg64 into 64-bit callers
Note that we had two functions of the same name: a 32-bit version
which took two register numbers and a 64-bit version which was a
no-op wrapper for tcg_write_reg. After this, we are left with
only the 32-bit version.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7f33f5cd0ad13e2720f18f162b98ececc8abee85
https://github.com/qemu/qemu/commit/7f33f5cd0ad13e2720f18f162b98ececc8abee85
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_ld8u_{i32,i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 850163eb4db6a14cb9474cff393bec06f9d594c5
https://github.com/qemu/qemu/commit/850163eb4db6a14cb9474cff393bec06f9d594c5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_ld8s_{i32,i64}
Eliminating a TODO for ld8s_i32.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 77c38c7c3fdefb6097856bf6ccb1320566e0b968
https://github.com/qemu/qemu/commit/77c38c7c3fdefb6097856bf6ccb1320566e0b968
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_ld16u_{i32,i64}
Eliminating a TODO for ld16u_i32.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b09d78bf22238cad8f7ab58b5890afbb3256ce7c
https://github.com/qemu/qemu/commit/b09d78bf22238cad8f7ab58b5890afbb3256ce7c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_ld16s_{i32,i64}
Eliminating a TODO for ld16s_i64.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c1d77e94751e3c11ca5eb0b09cf876debf676641
https://github.com/qemu/qemu/commit/c1d77e94751e3c11ca5eb0b09cf876debf676641
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ba9a80c1e897660bb59fa4287f3373c56d22f15a
https://github.com/qemu/qemu/commit/ba9a80c1e897660bb59fa4287f3373c56d22f15a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_st8_{i32,i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 90be4dde247064082ab96c51a44b7bba30afb262
https://github.com/qemu/qemu/commit/90be4dde247064082ab96c51a44b7bba30afb262
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_st16_{i32,i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 53f405569cf84eb08756a53ad722d4dbe07023ec
https://github.com/qemu/qemu/commit/53f405569cf84eb08756a53ad722d4dbe07023ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Move stack bounds check to compile-time
The existing check was incomplete:
(1) Only applied to two of the 7 stores, and not to the loads at all.
(2) Only checked the upper, but not the lower bound of the stack.
Doing this at compile time means that we don't need to do it
at runtime as well.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b4d5bf0f9b2a6370d1e2e1a5c3f9297286bd500c
https://github.com/qemu/qemu/commit/b4d5bf0f9b2a6370d1e2e1a5c3f9297286bd500c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Merge INDEX_op_{st_i32,st32_i64}
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f6996f99f3d583d7811097368814acd0e5d4bee9
https://github.com/qemu/qemu/commit/f6996f99f3d583d7811097368814acd0e5d4bee9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Use g_assert_not_reached
Three TODO instances are never happen cases.
Other uses of tcg_abort are also indicating unreachable cases.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7abd007cbc145c1f3745c6b1ca0deea2ef5c8591
https://github.com/qemu/qemu/commit/7abd007cbc145c1f3745c6b1ca0deea2ef5c8591
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*
We do not simultaneously support div and div2 -- it's one
or the other. TCI is already using div, so remove div2.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ae40c098ac637b51ccf350d70765e76129b838a5
https://github.com/qemu/qemu/commit/ae40c098ac637b51ccf350d70765e76129b838a5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: Implement 64-bit division
Trivially implemented like other arithmetic.
Tested via check-tcg and the ppc64 target.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f6ff97ab565d4aa779ae3e07e8c5f13e7495a005
https://github.com/qemu/qemu/commit/f6ff97ab565d4aa779ae3e07e8c5f13e7495a005
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
Log Message:
-----------
tcg/tci: Remove TODO as unused
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 187f44d9da0ca8ac08451f03f62b259080596570
https://github.com/qemu/qemu/commit/187f44d9da0ca8ac08451f03f62b259080596570
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 552672bae63dd2c470fc533f276b746bae90b813
https://github.com/qemu/qemu/commit/552672bae63dd2c470fc533f276b746bae90b813
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Fix TCG_REG_R4 misusage
This was removed from tcg_target_reg_alloc_order and
tcg_target_call_iarg_regs on the assumption that it
was the stack. This was incorrectly copied from i386.
For tci, the stack is R15.
By adding R4 back to tcg_target_call_iarg_regs, adjust the other
entries so that 6 (or 12) entries are still present in the array,
and adjust the numbers in the interpreter.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2f74f45e32beb0ae24366128fdf685a5121c0f67
https://github.com/qemu/qemu/commit/2f74f45e32beb0ae24366128fdf685a5121c0f67
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target-con-set.h
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: Remove TCG_CONST
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e9e51b7154404efc9af8735ab87c658a9c434cfd
https://github.com/qemu/qemu/commit/e9e51b7154404efc9af8735ab87c658a9c434cfd
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M cpu.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/moxie/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/tricore/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: Introduce TCGCpuOperations struct
The TCG-specific CPU methods will be moved to a separate struct,
to make it easier to move accel-specific code outside generic CPU
code in the future. Start by moving tcg_initialize().
The new CPUClass.tcg_opts field may eventually become a pointer,
but keep it an embedded struct for now, to make code conversion
easier.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: move TCGCpuOperations inside include/hw/core/cpu.h]
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-2-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff
https://github.com/qemu/qemu/commit/6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: remove CONFIG_TCG, as it is always TCG
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-3-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7df5e3d6ad569f004d6aa943e8b60ab25875b577
https://github.com/qemu/qemu/commit/7df5e3d6ad569f004d6aa943e8b60ab25875b577
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M cpu.c
M hw/core/cpu.c
M include/exec/cpu-all.h
M include/hw/core/cpu.h
Log Message:
-----------
accel/tcg: split TCG-only code from cpu_exec_realizefn
move away TCG-only code, make it compile only on TCG.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-4-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ec62595bab1873c48a34849de70011093177e769
https://github.com/qemu/qemu/commit/ec62595bab1873c48a34849de70011093177e769
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/riscv/cpu.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
Log Message:
-----------
cpu: Move synchronize_from_tb() to tcg_ops
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped target code in CONFIG_TCG, reworded comments]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-5-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 48c1a3e303b5a2cca48679645ad3fbb914db741a
https://github.com/qemu/qemu/commit/48c1a3e303b5a2cca48679645ad3fbb914db741a
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: Move cpu_exec_* to tcg_ops
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-6-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e124536f37377cff5d68925d4976ad604d0ebf3a
https://github.com/qemu/qemu/commit/e124536f37377cff5d68925d4976ad604d0ebf3a
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/avr/cpu.c
M target/cris/cpu.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/moxie/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/tricore/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: Move tlb_fill to tcg_ops
[claudio: wrapped target code in CONFIG_TCG]
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-7-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: e9ce43e97a19090ae8975ef168b95ba3d29be991
https://github.com/qemu/qemu/commit/e9ce43e97a19090ae8975ef168b95ba3d29be991
Author: Eduardo Habkost <ehabkost@redhat.com>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/cpu.h
M target/arm/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/s390x/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: Move debug_excp_handler to tcg_ops
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-8-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 853bfef4e6d60244fd131ec55bbf1e7caa52599b
https://github.com/qemu/qemu/commit/853bfef4e6d60244fd131ec55bbf1e7caa52599b
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M target/arm/helper.c
M target/arm/kvm64.c
Log Message:
-----------
target/arm: do not use cc->do_interrupt for KVM directly
cc->do_interrupt is in theory a TCG callback used in accel/tcg only,
to prepare the emulated architecture to take an interrupt as defined
in the hardware specifications,
but in reality the _do_interrupt style of functions in targets are
also occasionally reused by KVM to prepare the architecture state in a
similar way where userspace code has identified that it needs to
deliver an exception to the guest.
In the case of ARM, that includes:
1) the vcpu thread got a SIGBUS indicating a memory error,
and we need to deliver a Synchronous External Abort to the guest to
let it know about the error.
2) the kernel told us about a debug exception (breakpoint, watchpoint)
but it is not for one of QEMU's own gdbstub breakpoints/watchpoints
so it must be a breakpoint the guest itself has set up, therefore
we need to deliver it to the guest.
So in order to reuse code, the same arm_do_interrupt function is used.
This is all fine, but we need to avoid calling it using the callback
registered in CPUClass, since that one is now TCG-only.
Fortunately this is easily solved by replacing calls to
CPUClass::do_interrupt() with explicit calls to arm_do_interrupt().
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20210204163931.7358-9-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0545608056a6161e7020cd7b9368d9636fa80051
https://github.com/qemu/qemu/commit/0545608056a6161e7020cd7b9368d9636fa80051
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/cpu-exec.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/cpu_tcg.c
M target/avr/cpu.c
M target/avr/helper.c
M target/cris/cpu.c
M target/cris/helper.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/moxie/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: move cc->do_interrupt to tcg_ops
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210204163931.7358-10-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c
https://github.com/qemu/qemu/commit/cbc183d2d9f5b8a33c2a6cf9cb242b04db1e8d5c
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M hw/mips/jazz.c
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
M target/sparc/cpu.c
M target/xtensa/cpu.c
M target/xtensa/helper.c
Log Message:
-----------
cpu: move cc->transaction_failed to tcg_ops
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY]
avoiding its use in headers used by common_ss code (should be poisoned).
Note: need to be careful with the use of CONFIG_USER_ONLY,
Message-Id: <20210204163931.7358-11-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
https://github.com/qemu/qemu/commit/8535dd702dd054a37a85e0c7971cfb43cc7b50e3
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M include/hw/core/cpu.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/hppa/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/nios2/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/s390x/cpu.c
M target/s390x/excp_helper.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: move do_unaligned_access to tcg_ops
make it consistently SOFTMMU-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[claudio: make the field presence in cpu.h unconditional, removing the ifdefs]
Message-Id: <20210204163931.7358-12-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 79fc8d45116b4b07eeab53feea1d209955b0ecdd
https://github.com/qemu/qemu/commit/79fc8d45116b4b07eeab53feea1d209955b0ecdd
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M softmmu/physmem.c
Log Message:
-----------
physmem: make watchpoint checking code TCG-only
cpu_check_watchpoint, watchpoint_address_matches are TCG-only.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-13-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 9ea9087bb4a86893e4ac6ff643837937dc9e5849
https://github.com/qemu/qemu/commit/9ea9087bb4a86893e4ac6ff643837937dc9e5849
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M hw/core/cpu.c
M include/hw/core/cpu.h
M softmmu/physmem.c
M target/arm/cpu.c
Log Message:
-----------
cpu: move adjust_watchpoint_address to tcg_ops
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs")
introduced this ARM-specific, TCG-specific hack to adjust the address,
before checking it with cpu_check_watchpoint.
Make adjust_watchpoint_address optional and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-14-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d
https://github.com/qemu/qemu/commit/c73bdb35a91fb6b17c2c93b1ba381fc88a406f8d
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M accel/tcg/user-exec.c
M hw/core/cpu.c
M include/hw/core/cpu.h
M softmmu/physmem.c
M target/arm/cpu.c
Log Message:
-----------
cpu: move debug_check_watchpoint to tcg_ops
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and
commit 3826121d9298 ("target-arm: Implement checking of fired")
introduced an ARM-specific hack for cpu_check_watchpoint.
Make debug_check_watchpoint optional, and move it to tcg_ops.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-15-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 78271684719f34c1cc19f895e089f2f19b69698d
https://github.com/qemu/qemu/commit/78271684719f34c1cc19f895e089f2f19b69698d
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M MAINTAINERS
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M hw/mips/jazz.c
M include/hw/core/cpu.h
A include/hw/core/tcg-cpu-ops.h
M softmmu/physmem.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/internals.h
M target/avr/cpu.c
M target/avr/helper.c
M target/cris/cpu.c
M target/cris/helper.c
M target/hppa/cpu.c
M target/i386/tcg/tcg-cpu.c
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/moxie/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/tricore/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 940e43aa30e0f793bd18b79221296cdf17724018
https://github.com/qemu/qemu/commit/940e43aa30e0f793bd18b79221296cdf17724018
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M MAINTAINERS
A accel/accel-common.c
A accel/accel-softmmu.c
A accel/accel-user.c
R accel/accel.c
M accel/meson.build
M accel/qtest/qtest.c
M accel/tcg/meson.build
M accel/tcg/tcg-all.c
M accel/xen/xen-all.c
M bsd-user/main.c
M include/hw/boards.h
A include/qemu/accel.h
R include/sysemu/accel.h
M include/sysemu/hvf.h
M include/sysemu/kvm.h
M include/sysemu/kvm_int.h
M linux-user/main.c
M softmmu/memory.c
M softmmu/qtest.c
M softmmu/vl.c
M target/i386/hax/hax-all.c
M target/i386/hvf/hvf-i386.h
M target/i386/hvf/hvf.c
M target/i386/hvf/x86_task.c
M target/i386/whpx/whpx-all.c
Log Message:
-----------
accel: extend AccelState and AccelClass to user-mode
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[claudio: rebased on Richard's splitwx work]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-17-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b86f59c71552591a17dd21ba8f09654bfa19a31e
https://github.com/qemu/qemu/commit/b86f59c71552591a17dd21ba8f09654bfa19a31e
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M MAINTAINERS
M accel/accel-common.c
M accel/accel-softmmu.c
A accel/accel-softmmu.h
A accel/kvm/kvm-accel-ops.c
M accel/kvm/kvm-all.c
R accel/kvm/kvm-cpus.c
M accel/kvm/kvm-cpus.h
M accel/kvm/meson.build
M accel/qtest/qtest.c
M accel/tcg/meson.build
A accel/tcg/tcg-accel-ops-icount.c
A accel/tcg/tcg-accel-ops-icount.h
A accel/tcg/tcg-accel-ops-mttcg.c
A accel/tcg/tcg-accel-ops-mttcg.h
A accel/tcg/tcg-accel-ops-rr.c
A accel/tcg/tcg-accel-ops-rr.h
A accel/tcg/tcg-accel-ops.c
A accel/tcg/tcg-accel-ops.h
M accel/tcg/tcg-all.c
R accel/tcg/tcg-cpus-icount.c
R accel/tcg/tcg-cpus-icount.h
R accel/tcg/tcg-cpus-mttcg.c
R accel/tcg/tcg-cpus-rr.c
R accel/tcg/tcg-cpus-rr.h
R accel/tcg/tcg-cpus.c
R accel/tcg/tcg-cpus.h
M accel/xen/xen-all.c
M bsd-user/main.c
M include/qemu/accel.h
A include/sysemu/accel-ops.h
M include/sysemu/cpus.h
M linux-user/main.c
M softmmu/cpus.c
M softmmu/vl.c
A target/i386/hax/hax-accel-ops.c
A target/i386/hax/hax-accel-ops.h
M target/i386/hax/hax-all.c
R target/i386/hax/hax-cpus.c
R target/i386/hax/hax-cpus.h
M target/i386/hax/hax-mem.c
M target/i386/hax/hax-posix.c
M target/i386/hax/hax-windows.c
M target/i386/hax/hax-windows.h
M target/i386/hax/meson.build
A target/i386/hvf/hvf-accel-ops.c
A target/i386/hvf/hvf-accel-ops.h
R target/i386/hvf/hvf-cpus.c
R target/i386/hvf/hvf-cpus.h
M target/i386/hvf/hvf.c
M target/i386/hvf/meson.build
M target/i386/hvf/x86hvf.c
M target/i386/whpx/meson.build
A target/i386/whpx/whpx-accel-ops.c
A target/i386/whpx/whpx-accel-ops.h
M target/i386/whpx/whpx-all.c
R target/i386/whpx/whpx-cpus.c
R target/i386/whpx/whpx-cpus.h
Log Message:
-----------
accel: replace struct CpusAccel with AccelOpsClass
This will allow us to centralize the registration of
the cpus.c module accelerator operations (in accel/accel-softmmu.c),
and trigger it automatically using object hierarchy lookup from the
new accel_init_interfaces() initialization step, depending just on
which accelerators are available in the code.
Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c,
kvm-accel-ops.c, etc, matching the object type names.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-18-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fb6916dd6ca8bb4b42d44baba9c67ecaf2279577
https://github.com/qemu/qemu/commit/fb6916dd6ca8bb4b42d44baba9c67ecaf2279577
Author: Claudio Fontana <cfontana@suse.de>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M MAINTAINERS
M accel/accel-common.c
A include/hw/core/accel-cpu.h
M include/hw/core/cpu.h
Log Message:
-----------
accel: introduce AccelCPUClass extending CPUClass
add a new optional interface to CPUClass, which allows accelerators
to extend the CPUClass with additional accelerator-specific
initializations.
This will allow to separate the target cpu code that is specific
to each accelerator, and register it automatically with object
hierarchy lookup depending on accelerator code availability,
as part of the accel_init_interfaces() initialization step.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-19-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 5b19cb63d9dfda41b412373b8c9fe14641bcab60
https://github.com/qemu/qemu/commit/5b19cb63d9dfda41b412373b8c9fe14641bcab60
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2021-02-05 (Fri, 05 Feb 2021)
Changed paths:
M MAINTAINERS
A accel/accel-common.c
A accel/accel-softmmu.c
A accel/accel-softmmu.h
A accel/accel-user.c
R accel/accel.c
A accel/kvm/kvm-accel-ops.c
M accel/kvm/kvm-all.c
R accel/kvm/kvm-cpus.c
M accel/kvm/kvm-cpus.h
M accel/kvm/meson.build
M accel/meson.build
M accel/qtest/qtest.c
M accel/tcg/cpu-exec.c
M accel/tcg/cputlb.c
M accel/tcg/meson.build
A accel/tcg/tcg-accel-ops-icount.c
A accel/tcg/tcg-accel-ops-icount.h
A accel/tcg/tcg-accel-ops-mttcg.c
A accel/tcg/tcg-accel-ops-mttcg.h
A accel/tcg/tcg-accel-ops-rr.c
A accel/tcg/tcg-accel-ops-rr.h
A accel/tcg/tcg-accel-ops.c
A accel/tcg/tcg-accel-ops.h
M accel/tcg/tcg-all.c
R accel/tcg/tcg-cpus-icount.c
R accel/tcg/tcg-cpus-icount.h
R accel/tcg/tcg-cpus-mttcg.c
R accel/tcg/tcg-cpus-rr.c
R accel/tcg/tcg-cpus-rr.h
R accel/tcg/tcg-cpus.c
R accel/tcg/tcg-cpus.h
M accel/tcg/user-exec.c
M accel/xen/xen-all.c
M bsd-user/main.c
M configure
M cpu.c
M hw/core/cpu.c
M hw/mips/jazz.c
M include/exec/cpu-all.h
M include/exec/cpu-defs.h
M include/exec/exec-all.h
M include/hw/boards.h
A include/hw/core/accel-cpu.h
M include/hw/core/cpu.h
A include/hw/core/tcg-cpu-ops.h
A include/qemu/accel.h
A include/sysemu/accel-ops.h
R include/sysemu/accel.h
M include/sysemu/cpus.h
M include/sysemu/hvf.h
M include/sysemu/kvm.h
M include/sysemu/kvm_int.h
M linux-user/main.c
M softmmu/cpus.c
M softmmu/memory.c
M softmmu/physmem.c
M softmmu/qtest.c
M softmmu/vl.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/cpu64.c
M target/arm/cpu_tcg.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm64.c
M target/avr/cpu.c
M target/avr/helper.c
M target/cris/cpu.c
M target/cris/helper.c
M target/hppa/cpu.c
A target/i386/hax/hax-accel-ops.c
A target/i386/hax/hax-accel-ops.h
M target/i386/hax/hax-all.c
R target/i386/hax/hax-cpus.c
R target/i386/hax/hax-cpus.h
M target/i386/hax/hax-mem.c
M target/i386/hax/hax-posix.c
M target/i386/hax/hax-windows.c
M target/i386/hax/hax-windows.h
M target/i386/hax/meson.build
A target/i386/hvf/hvf-accel-ops.c
A target/i386/hvf/hvf-accel-ops.h
R target/i386/hvf/hvf-cpus.c
R target/i386/hvf/hvf-cpus.h
M target/i386/hvf/hvf-i386.h
M target/i386/hvf/hvf.c
M target/i386/hvf/meson.build
M target/i386/hvf/x86_task.c
M target/i386/hvf/x86hvf.c
M target/i386/tcg/tcg-cpu.c
M target/i386/whpx/meson.build
A target/i386/whpx/whpx-accel-ops.c
A target/i386/whpx/whpx-accel-ops.h
M target/i386/whpx/whpx-all.c
R target/i386/whpx/whpx-cpus.c
R target/i386/whpx/whpx-cpus.h
M target/lm32/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/moxie/cpu.c
M target/nios2/cpu.c
M target/openrisc/cpu.c
M target/ppc/translate_init.c.inc
M target/riscv/cpu.c
M target/riscv/cpu_helper.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/s390x/excp_helper.c
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tilegx/cpu.c
M target/tricore/cpu.c
M target/unicore32/cpu.c
M target/xtensa/cpu.c
M target/xtensa/helper.c
M tcg/aarch64/tcg-target.c.inc
M tcg/s390/tcg-target.c.inc
M tcg/tcg-common.c
M tcg/tci.c
M tcg/tci/tcg-target-con-set.h
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210205' into
staging
TCGCPUOps cleanups (claudio)
tcg/s390 compare fix (phil)
tcg/aarch64 rotli_vec fix
tcg/tci cleanups and fixes
# gpg: Signature made Fri 05 Feb 2021 22:55:10 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210205: (46 commits)
accel: introduce AccelCPUClass extending CPUClass
accel: replace struct CpusAccel with AccelOpsClass
accel: extend AccelState and AccelClass to user-mode
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
cpu: move debug_check_watchpoint to tcg_ops
cpu: move adjust_watchpoint_address to tcg_ops
physmem: make watchpoint checking code TCG-only
cpu: move do_unaligned_access to tcg_ops
cpu: move cc->transaction_failed to tcg_ops
cpu: move cc->do_interrupt to tcg_ops
target/arm: do not use cc->do_interrupt for KVM directly
cpu: Move debug_excp_handler to tcg_ops
cpu: Move tlb_fill to tcg_ops
cpu: Move cpu_exec_* to tcg_ops
cpu: Move synchronize_from_tb() to tcg_ops
accel/tcg: split TCG-only code from cpu_exec_realizefn
target/riscv: remove CONFIG_TCG, as it is always TCG
cpu: Introduce TCGCpuOperations struct
tcg/tci: Remove TCG_CONST
tcg/tci: Fix TCG_REG_R4 misusage
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/d0dddab40e47...5b19cb63d9df