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[Qemu-commits] [qemu/qemu] 169585: hw/block: m25p80: Don't write to flas


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 169585: hw/block: m25p80: Don't write to flash if write is...
Date: Mon, 18 Jan 2021 02:52:06 -0800

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 1695854b371cdd4d17835a406675245a8dfe6cff
      
https://github.com/qemu/qemu/commit/1695854b371cdd4d17835a406675245a8dfe6cff
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block: m25p80: Don't write to flash if write is disabled

When write is disabled, the write to flash should be avoided
in flash_write8().

Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 1608688825-81519-1-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 465ef47abe3fd0722cf50a6073ccd9520bdbee95
      
https://github.com/qemu/qemu/commit/465ef47abe3fd0722cf50a6073ccd9520bdbee95
  Author: Xuzhou Cheng <xuzhou.cheng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  hw/block: m25p80: Implement AAI-WP command support for SST flashes

Auto Address Increment (AAI) Word-Program is a special command of
SST flashes. AAI-WP allows multiple bytes of data to be programmed
without re-issuing the next sequential address location.

Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 1608688825-81519-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: edf647864bdab84ed4b1a4f47ea05be6bb075c69
      
https://github.com/qemu/qemu/commit/edf647864bdab84ed4b1a4f47ea05be6bb075c69
  Author: Sylvain Pelissier <sylvain.pelissier@gmail.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  gdb: riscv: Add target description

Target description is not currently implemented in RISC-V
architecture. Thus GDB won't set it properly when attached.
The patch implements the target description response.

Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210106204141.14027-1-sylvain.pelissier@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1a475d39ef5467ca432c91beb67e9009304bb0bc
      
https://github.com/qemu/qemu/commit/1a475d39ef5467ca432c91beb67e9009304bb0bc
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/riscv/boot.c

  Log Message:
  -----------
  RISC-V: Place DTB at 3GB boundary instead of 4GB

Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a result, it can not process DT and panic if opensbi dynamic firmware
is used. While at it, place the DTB further away to avoid in memory placement
issues in future.

Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.

Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")

Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: d102f19a2085ac931cb998e6153b73248cca49f1
      
https://github.com/qemu/qemu/commit/d102f19a2085ac931cb998e6153b73248cca49f1
  Author: Atish Patra <atish.patra@wdc.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  target/riscv/pmp: Raise exception if no PMP entry is configured

As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201223192553.332508-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 1eaada8ae15f10f7a7f1e2505bd77dbb11a8be85
      
https://github.com/qemu/qemu/commit/1eaada8ae15f10f7a7f1e2505bd77dbb11a8be85
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type

SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
there is no need to use #idef to set the mc->default_cpu_type.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210109143637.29645-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 29b5fe0dcd512f9829475e3eb3f6fdc5e293b8f0
      
https://github.com/qemu/qemu/commit/29b5fe0dcd512f9829475e3eb3f6fdc5e293b8f0
  Author: Green Wan <green.wan@sifive.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/misc/sifive_u_otp.c

  Log Message:
  -----------
  hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite

Fix code coverage issues by checking return value and handling fail case
of blk_pread() and blk_pwrite(). Return default value 0xff if read fails.

Fixes: Coverity CID 1435959
Fixes: Coverity CID 1435960
Fixes: Coverity CID 1435961
Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201104092900.21214-1-green.wan@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 56118ee88ddf0498e0c8c4c81ef91d793c76866f
      
https://github.com/qemu/qemu/commit/56118ee88ddf0498e0c8c4c81ef91d793c76866f
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Make csr_ops[CSR_TABLE_SIZE] external

In preparation to generate the CSR register list for GDB stub
dynamically, change csr_ops[] to non-static so that it can be
referenced externally.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 8ceac5dc3d7ded3cc408255da09a7f0e52ae8416
      
https://github.com/qemu/qemu/commit/8ceac5dc3d7ded3cc408255da09a7f0e52ae8416
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Add CSR name in the CSR function table

In preparation to generate the CSR register list for GDB stub
dynamically, let's add the CSR name in the CSR function table.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1610427124-49887-3-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: b93777e1b4999b1f51f1fa3398f5d400f75a4aab
      
https://github.com/qemu/qemu/commit/b93777e1b4999b1f51f1fa3398f5d400f75a4aab
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  target/riscv: Generate the GDB XML file for CSR registers dynamically

At present QEMU RISC-V uses a hardcoded XML to report the feature
"org.gnu.gdb.riscv.csr" [1]. There are two major issues with the
approach being used currently:

- The XML does not specify the "regnum" field of a CSR entry, hence
  consecutive numbers are used by the remote GDB client to access
  CSRs. In QEMU we have to maintain a map table to convert the GDB
  number to the hardware number which is error prone.
- The XML contains some CSRs that QEMU does not implement at all,
  which causes an "E14" response sent to remote GDB client.

Change to generate the CSR register list dynamically, based on the
availability presented in the CSR function table. This new approach
will reflect a correct list of CSRs that QEMU actually implements.

[1] 
https://sourceware.org/gdb/current/onlinedocs/gdb/RISC_002dV-Features.html#RISC_002dV-Features

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210116054123.5457-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: 138ca49a82b978f035b709abee45324dd7ab3e68
      
https://github.com/qemu/qemu/commit/138ca49a82b978f035b709abee45324dd7ab3e68
  Author: Bin Meng <bin.meng@windriver.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M default-configs/targets/riscv32-linux-user.mak
    M default-configs/targets/riscv32-softmmu.mak
    M default-configs/targets/riscv64-linux-user.mak
    M default-configs/targets/riscv64-softmmu.mak
    R gdb-xml/riscv-32bit-csr.xml
    R gdb-xml/riscv-64bit-csr.xml

  Log Message:
  -----------
  target/riscv: Remove built-in GDB XML files for CSRs

Now that we have switched to generate the RISC-V CSR XML dynamically,
remove the built-in hardcoded XML files.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210116054123.5457-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>


  Commit: a8259b53230782f5e0a0d66013655c4ed5d71b7e
      
https://github.com/qemu/qemu/commit/a8259b53230782f5e0a0d66013655c4ed5d71b7e
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2021-01-16 (Sat, 16 Jan 2021)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  riscv: Pass RISCVHartArrayState by pointer

We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.

Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: 
f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com


  Commit: 20b8016ed847ac751e508c38aa27a9f8ecb93ac8
      
https://github.com/qemu/qemu/commit/20b8016ed847ac751e508c38aa27a9f8ecb93ac8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2021-01-18 (Mon, 18 Jan 2021)

  Changed paths:
    M default-configs/targets/riscv32-linux-user.mak
    M default-configs/targets/riscv32-softmmu.mak
    M default-configs/targets/riscv64-linux-user.mak
    M default-configs/targets/riscv64-softmmu.mak
    R gdb-xml/riscv-32bit-csr.xml
    R gdb-xml/riscv-64bit-csr.xml
    M hw/block/m25p80.c
    M hw/misc/sifive_u_otp.c
    M hw/riscv/boot.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/op_helper.c
    M target/riscv/pmp.c
    M target/riscv/pmp.h

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/alistair/tags/pull-riscv-to-apply-20210117-3' into staging

First RISC-V PR for 6.0

This PR:
 - Fixes some issues with the m25p80
 - Improves GDB support for RISC-V
 - Fixes some Linux boot issues, specifiaclly 32-bit boot failures
 - Enforces PMP exceptions correctly
 - Fixes some Coverity issues

# gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210117-3:
  riscv: Pass RISCVHartArrayState by pointer
  target/riscv: Remove built-in GDB XML files for CSRs
  target/riscv: Generate the GDB XML file for CSR registers dynamically
  target/riscv: Add CSR name in the CSR function table
  target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
  hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite
  hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
  target/riscv/pmp: Raise exception if no PMP entry is configured
  RISC-V: Place DTB at 3GB boundary instead of 4GB
  gdb: riscv: Add target description
  hw/block: m25p80: Implement AAI-WP command support for SST flashes
  hw/block: m25p80: Don't write to flash if write is disabled

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/e0cbcf1eea16...20b8016ed847



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